1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 32config GIC_NON_BANKED 33 bool 34 35config ARM_GIC_V3 36 bool 37 select IRQ_DOMAIN_HIERARCHY 38 select PARTITION_PERCPU 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 42config ARM_GIC_V3_ITS 43 bool 44 select GENERIC_MSI_IRQ 45 select IRQ_MSI_LIB 46 default ARM_GIC_V3 47 48config ARM_GIC_V3_ITS_FSL_MC 49 bool 50 depends on ARM_GIC_V3_ITS 51 depends on FSL_MC_BUS 52 default ARM_GIC_V3_ITS 53 54config ARM_NVIC 55 bool 56 select IRQ_DOMAIN_HIERARCHY 57 select GENERIC_IRQ_CHIP 58 59config ARM_VIC 60 bool 61 select IRQ_DOMAIN 62 63config ARM_VIC_NR 64 int 65 default 4 if ARCH_S5PV210 66 default 2 67 depends on ARM_VIC 68 help 69 The maximum number of VICs available in the system, for 70 power management. 71 72config IRQ_MSI_LIB 73 bool 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF 90 depends on HAS_IOMEM 91 select GENERIC_IRQ_CHIP 92 select IRQ_DOMAIN 93 help 94 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 95 96config ATMEL_AIC_IRQ 97 bool 98 select GENERIC_IRQ_CHIP 99 select IRQ_DOMAIN 100 select SPARSE_IRQ 101 102config ATMEL_AIC5_IRQ 103 bool 104 select GENERIC_IRQ_CHIP 105 select IRQ_DOMAIN 106 select SPARSE_IRQ 107 108config I8259 109 bool 110 select IRQ_DOMAIN 111 112config BCM6345_L1_IRQ 113 bool 114 select GENERIC_IRQ_CHIP 115 select IRQ_DOMAIN 116 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 117 118config BCM7038_L1_IRQ 119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 120 depends on ARCH_BRCMSTB || BMIPS_GENERIC 121 default ARCH_BRCMSTB || BMIPS_GENERIC 122 select GENERIC_IRQ_CHIP 123 select IRQ_DOMAIN 124 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 125 126config BCM7120_L2_IRQ 127 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 128 depends on ARCH_BRCMSTB || BMIPS_GENERIC 129 default ARCH_BRCMSTB || BMIPS_GENERIC 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config BRCMSTB_L2_IRQ 134 tristate "Broadcom STB generic L2 interrupt controller driver" 135 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 137 select GENERIC_IRQ_CHIP 138 select IRQ_DOMAIN 139 140config DAVINCI_CP_INTC 141 bool 142 select GENERIC_IRQ_CHIP 143 select IRQ_DOMAIN 144 145config DW_APB_ICTL 146 bool 147 select GENERIC_IRQ_CHIP 148 select IRQ_DOMAIN_HIERARCHY 149 150config FARADAY_FTINTC010 151 bool 152 select IRQ_DOMAIN 153 select SPARSE_IRQ 154 155config HISILICON_IRQ_MBIGEN 156 bool 157 select ARM_GIC_V3 158 select ARM_GIC_V3_ITS 159 160config IMGPDC_IRQ 161 bool 162 select GENERIC_IRQ_CHIP 163 select IRQ_DOMAIN 164 165config IXP4XX_IRQ 166 bool 167 select IRQ_DOMAIN 168 select SPARSE_IRQ 169 170config LAN966X_OIC 171 tristate "Microchip LAN966x OIC Support" 172 select GENERIC_IRQ_CHIP 173 select IRQ_DOMAIN 174 help 175 Enable support for the LAN966x Outbound Interrupt Controller. 176 This controller is present on the Microchip LAN966x PCI device and 177 maps the internal interrupts sources to PCIe interrupt. 178 179 To compile this driver as a module, choose M here: the module 180 will be called irq-lan966x-oic. 181 182config MADERA_IRQ 183 tristate 184 185config IRQ_MIPS_CPU 186 bool 187 select GENERIC_IRQ_CHIP 188 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 189 select IRQ_DOMAIN 190 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 191 192config CLPS711X_IRQCHIP 193 bool 194 depends on ARCH_CLPS711X 195 select IRQ_DOMAIN 196 select SPARSE_IRQ 197 default y 198 199config OMPIC 200 bool 201 202config OR1K_PIC 203 bool 204 select IRQ_DOMAIN 205 206config OMAP_IRQCHIP 207 bool 208 select GENERIC_IRQ_CHIP 209 select IRQ_DOMAIN 210 211config ORION_IRQCHIP 212 bool 213 select IRQ_DOMAIN 214 215config PIC32_EVIC 216 bool 217 select GENERIC_IRQ_CHIP 218 select IRQ_DOMAIN 219 220config JCORE_AIC 221 bool "J-Core integrated AIC" if COMPILE_TEST 222 depends on OF 223 select IRQ_DOMAIN 224 help 225 Support for the J-Core integrated AIC. 226 227config RDA_INTC 228 bool 229 select IRQ_DOMAIN 230 231config RENESAS_INTC_IRQPIN 232 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 233 select IRQ_DOMAIN 234 help 235 Enable support for the Renesas Interrupt Controller for external 236 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 237 238config RENESAS_IRQC 239 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 240 select GENERIC_IRQ_CHIP 241 select IRQ_DOMAIN 242 help 243 Enable support for the Renesas Interrupt Controller for external 244 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 245 246config RENESAS_RZA1_IRQC 247 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 248 select IRQ_DOMAIN_HIERARCHY 249 help 250 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 251 to 8 external interrupts with configurable sense select. 252 253config RENESAS_RZG2L_IRQC 254 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 255 select GENERIC_IRQ_CHIP 256 select IRQ_DOMAIN_HIERARCHY 257 help 258 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 259 for external devices. 260 261config RENESAS_RZV2H_ICU 262 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 263 select GENERIC_IRQ_CHIP 264 select IRQ_DOMAIN_HIERARCHY 265 help 266 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 267 268config SL28CPLD_INTC 269 bool "Kontron sl28cpld IRQ controller" 270 depends on MFD_SL28CPLD=y || COMPILE_TEST 271 select REGMAP_IRQ 272 help 273 Interrupt controller driver for the board management controller 274 found on the Kontron sl28 CPLD. 275 276config ST_IRQCHIP 277 bool 278 select REGMAP 279 select MFD_SYSCON 280 help 281 Enables SysCfg Controlled IRQs on STi based platforms. 282 283config SUN4I_INTC 284 bool 285 286config SUN6I_R_INTC 287 bool 288 select IRQ_DOMAIN_HIERARCHY 289 select IRQ_FASTEOI_HIERARCHY_HANDLERS 290 291config SUNXI_NMI_INTC 292 bool 293 select GENERIC_IRQ_CHIP 294 295config TB10X_IRQC 296 bool 297 select IRQ_DOMAIN 298 select GENERIC_IRQ_CHIP 299 300config TS4800_IRQ 301 tristate "TS-4800 IRQ controller" 302 select IRQ_DOMAIN 303 depends on HAS_IOMEM 304 depends on SOC_IMX51 || COMPILE_TEST 305 help 306 Support for the TS-4800 FPGA IRQ controller 307 308config VERSATILE_FPGA_IRQ 309 bool 310 select IRQ_DOMAIN 311 312config VERSATILE_FPGA_IRQ_NR 313 int 314 default 4 315 depends on VERSATILE_FPGA_IRQ 316 317config XTENSA_MX 318 bool 319 select IRQ_DOMAIN 320 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 321 322config XILINX_INTC 323 bool "Xilinx Interrupt Controller IP" 324 depends on OF_ADDRESS 325 select IRQ_DOMAIN 326 help 327 Support for the Xilinx Interrupt Controller IP core. 328 This is used as a primary controller with MicroBlaze and can also 329 be used as a secondary chained controller on other platforms. 330 331config IRQ_CROSSBAR 332 bool 333 help 334 Support for a CROSSBAR ip that precedes the main interrupt controller. 335 The primary irqchip invokes the crossbar's callback which inturn allocates 336 a free irq and configures the IP. Thus the peripheral interrupts are 337 routed to one of the free irqchip interrupt lines. 338 339config KEYSTONE_IRQ 340 tristate "Keystone 2 IRQ controller IP" 341 depends on ARCH_KEYSTONE 342 help 343 Support for Texas Instruments Keystone 2 IRQ controller IP which 344 is part of the Keystone 2 IPC mechanism 345 346config MIPS_GIC 347 bool 348 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 349 select GENERIC_IRQ_IPI if SMP 350 select IRQ_DOMAIN_HIERARCHY 351 select MIPS_CM 352 353config INGENIC_IRQ 354 bool 355 depends on MACH_INGENIC 356 default y 357 358config INGENIC_TCU_IRQ 359 bool "Ingenic JZ47xx TCU interrupt controller" 360 default MACH_INGENIC 361 depends on MIPS || COMPILE_TEST 362 select MFD_SYSCON 363 select GENERIC_IRQ_CHIP 364 help 365 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 366 JZ47xx SoCs. 367 368 If unsure, say N. 369 370config IMX_GPCV2 371 bool 372 select IRQ_DOMAIN 373 help 374 Enables the wakeup IRQs for IMX platforms with GPCv2 block 375 376config IRQ_MXS 377 def_bool y if MACH_ASM9260 || ARCH_MXS 378 select IRQ_DOMAIN 379 select STMP_DEVICE 380 381config MSCC_OCELOT_IRQ 382 bool 383 select IRQ_DOMAIN 384 select GENERIC_IRQ_CHIP 385 386config MVEBU_GICP 387 select IRQ_MSI_LIB 388 bool 389 390config MVEBU_ICU 391 bool 392 393config MVEBU_ODMI 394 bool 395 select IRQ_MSI_LIB 396 select GENERIC_MSI_IRQ 397 398config MVEBU_PIC 399 bool 400 401config MVEBU_SEI 402 bool 403 404config LS_EXTIRQ 405 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 406 select MFD_SYSCON 407 408config LS_SCFG_MSI 409 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 410 depends on PCI_MSI 411 412config PARTITION_PERCPU 413 bool 414 415config STM32MP_EXTI 416 tristate "STM32MP extended interrupts and event controller" 417 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 418 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 419 select IRQ_DOMAIN_HIERARCHY 420 select GENERIC_IRQ_CHIP 421 help 422 Support STM32MP EXTI (extended interrupts and event) controller. 423 424config STM32_EXTI 425 bool 426 select IRQ_DOMAIN 427 select GENERIC_IRQ_CHIP 428 429config QCOM_IRQ_COMBINER 430 bool "QCOM IRQ combiner support" 431 depends on ARCH_QCOM && ACPI 432 select IRQ_DOMAIN_HIERARCHY 433 help 434 Say yes here to add support for the IRQ combiner devices embedded 435 in Qualcomm Technologies chips. 436 437config IRQ_UNIPHIER_AIDET 438 bool "UniPhier AIDET support" if COMPILE_TEST 439 depends on ARCH_UNIPHIER || COMPILE_TEST 440 default ARCH_UNIPHIER 441 select IRQ_DOMAIN_HIERARCHY 442 help 443 Support for the UniPhier AIDET (ARM Interrupt Detector). 444 445config MESON_IRQ_GPIO 446 tristate "Meson GPIO Interrupt Multiplexer" 447 depends on ARCH_MESON || COMPILE_TEST 448 default ARCH_MESON 449 select IRQ_DOMAIN_HIERARCHY 450 help 451 Support Meson SoC Family GPIO Interrupt Multiplexer 452 453config GOLDFISH_PIC 454 bool "Goldfish programmable interrupt controller" 455 depends on MIPS && (GOLDFISH || COMPILE_TEST) 456 select GENERIC_IRQ_CHIP 457 select IRQ_DOMAIN 458 help 459 Say yes here to enable Goldfish interrupt controller driver used 460 for Goldfish based virtual platforms. 461 462config QCOM_PDC 463 tristate "QCOM PDC" 464 depends on ARCH_QCOM 465 select IRQ_DOMAIN_HIERARCHY 466 help 467 Power Domain Controller driver to manage and configure wakeup 468 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 469 470config QCOM_MPM 471 tristate "QCOM MPM" 472 depends on ARCH_QCOM 473 depends on MAILBOX 474 select IRQ_DOMAIN_HIERARCHY 475 help 476 MSM Power Manager driver to manage and configure wakeup 477 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 478 479config CSKY_MPINTC 480 bool 481 depends on CSKY 482 help 483 Say yes here to enable C-SKY SMP interrupt controller driver used 484 for C-SKY SMP system. 485 In fact it's not mmio map in hardware and it uses ld/st to visit the 486 controller's register inside CPU. 487 488config CSKY_APB_INTC 489 bool "C-SKY APB Interrupt Controller" 490 depends on CSKY 491 help 492 Say yes here to enable C-SKY APB interrupt controller driver used 493 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 494 the controller's register. 495 496config IMX_IRQSTEER 497 bool "i.MX IRQSTEER support" 498 depends on ARCH_MXC || COMPILE_TEST 499 default ARCH_MXC 500 select IRQ_DOMAIN 501 help 502 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 503 504config IMX_INTMUX 505 bool "i.MX INTMUX support" if COMPILE_TEST 506 default y if ARCH_MXC 507 select IRQ_DOMAIN 508 help 509 Support for the i.MX INTMUX interrupt multiplexer. 510 511config IMX_MU_MSI 512 tristate "i.MX MU used as MSI controller" 513 depends on OF && HAS_IOMEM 514 depends on ARCH_MXC || COMPILE_TEST 515 default m if ARCH_MXC 516 select IRQ_DOMAIN 517 select IRQ_DOMAIN_HIERARCHY 518 select GENERIC_MSI_IRQ 519 select IRQ_MSI_LIB 520 help 521 Provide a driver for the i.MX Messaging Unit block used as a 522 CPU-to-CPU MSI controller. This requires a specially crafted DT 523 to make use of this driver. 524 525 If unsure, say N 526 527config LS1X_IRQ 528 bool "Loongson-1 Interrupt Controller" 529 depends on MACH_LOONGSON32 530 default y 531 select IRQ_DOMAIN 532 select GENERIC_IRQ_CHIP 533 help 534 Support for the Loongson-1 platform Interrupt Controller. 535 536config TI_SCI_INTR_IRQCHIP 537 bool 538 depends on TI_SCI_PROTOCOL 539 select IRQ_DOMAIN_HIERARCHY 540 help 541 This enables the irqchip driver support for K3 Interrupt router 542 over TI System Control Interface available on some new TI's SoCs. 543 If you wish to use interrupt router irq resources managed by the 544 TI System Controller, say Y here. Otherwise, say N. 545 546config TI_SCI_INTA_IRQCHIP 547 bool 548 depends on TI_SCI_PROTOCOL 549 select IRQ_DOMAIN_HIERARCHY 550 select TI_SCI_INTA_MSI_DOMAIN 551 help 552 This enables the irqchip driver support for K3 Interrupt aggregator 553 over TI System Control Interface available on some new TI's SoCs. 554 If you wish to use interrupt aggregator irq resources managed by the 555 TI System Controller, say Y here. Otherwise, say N. 556 557config TI_PRUSS_INTC 558 tristate 559 depends on TI_PRUSS 560 default TI_PRUSS 561 select IRQ_DOMAIN 562 help 563 This enables support for the PRU-ICSS Local Interrupt Controller 564 present within a PRU-ICSS subsystem present on various TI SoCs. 565 The PRUSS INTC enables various interrupts to be routed to multiple 566 different processors within the SoC. 567 568config RISCV_INTC 569 bool 570 depends on RISCV 571 select IRQ_DOMAIN_HIERARCHY 572 573config RISCV_APLIC 574 bool 575 depends on RISCV 576 select IRQ_DOMAIN_HIERARCHY 577 578config RISCV_APLIC_MSI 579 bool 580 depends on RISCV_APLIC 581 select GENERIC_MSI_IRQ 582 default RISCV_APLIC 583 584config RISCV_IMSIC 585 bool 586 depends on RISCV 587 select IRQ_DOMAIN_HIERARCHY 588 select GENERIC_IRQ_MATRIX_ALLOCATOR 589 select GENERIC_MSI_IRQ 590 591config RISCV_IMSIC_PCI 592 bool 593 depends on RISCV_IMSIC 594 depends on PCI 595 depends on PCI_MSI 596 default RISCV_IMSIC 597 598config SIFIVE_PLIC 599 bool 600 depends on RISCV 601 select IRQ_DOMAIN_HIERARCHY 602 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 603 604config STARFIVE_JH8100_INTC 605 bool "StarFive JH8100 External Interrupt Controller" 606 depends on ARCH_STARFIVE || COMPILE_TEST 607 default ARCH_STARFIVE 608 select IRQ_DOMAIN_HIERARCHY 609 help 610 This enables support for the INTC chip found in StarFive JH8100 611 SoC. 612 613 If you don't know what to do here, say Y. 614 615config THEAD_C900_ACLINT_SSWI 616 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" 617 depends on RISCV 618 depends on SMP 619 select IRQ_DOMAIN_HIERARCHY 620 select GENERIC_IRQ_IPI_MUX 621 help 622 This enables support for T-HEAD specific ACLINT SSWI device 623 support. 624 625 If you don't know what to do here, say Y. 626 627config EXYNOS_IRQ_COMBINER 628 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 629 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 630 help 631 Say yes here to add support for the IRQ combiner devices embedded 632 in Samsung Exynos chips. 633 634config IRQ_LOONGARCH_CPU 635 bool 636 select GENERIC_IRQ_CHIP 637 select IRQ_DOMAIN 638 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 639 select LOONGSON_HTVEC 640 select LOONGSON_LIOINTC 641 select LOONGSON_EIOINTC 642 select LOONGSON_PCH_PIC 643 select LOONGSON_PCH_MSI 644 select LOONGSON_PCH_LPC 645 help 646 Support for the LoongArch CPU Interrupt Controller. For details of 647 irq chip hierarchy on LoongArch platforms please read the document 648 Documentation/arch/loongarch/irq-chip-model.rst. 649 650config LOONGSON_LIOINTC 651 bool "Loongson Local I/O Interrupt Controller" 652 depends on MACH_LOONGSON64 653 default y 654 select IRQ_DOMAIN 655 select GENERIC_IRQ_CHIP 656 help 657 Support for the Loongson Local I/O Interrupt Controller. 658 659config LOONGSON_EIOINTC 660 bool "Loongson Extend I/O Interrupt Controller" 661 depends on LOONGARCH 662 depends on MACH_LOONGSON64 663 default MACH_LOONGSON64 664 select IRQ_DOMAIN_HIERARCHY 665 select GENERIC_IRQ_CHIP 666 help 667 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 668 669config LOONGSON_HTPIC 670 bool "Loongson3 HyperTransport PIC Controller" 671 depends on MACH_LOONGSON64 && MIPS 672 default y 673 select IRQ_DOMAIN 674 select GENERIC_IRQ_CHIP 675 help 676 Support for the Loongson-3 HyperTransport PIC Controller. 677 678config LOONGSON_HTVEC 679 bool "Loongson HyperTransport Interrupt Vector Controller" 680 depends on MACH_LOONGSON64 681 default MACH_LOONGSON64 682 select IRQ_DOMAIN_HIERARCHY 683 help 684 Support for the Loongson HyperTransport Interrupt Vector Controller. 685 686config LOONGSON_PCH_PIC 687 bool "Loongson PCH PIC Controller" 688 depends on MACH_LOONGSON64 689 default MACH_LOONGSON64 690 select IRQ_DOMAIN_HIERARCHY 691 select IRQ_FASTEOI_HIERARCHY_HANDLERS 692 help 693 Support for the Loongson PCH PIC Controller. 694 695config LOONGSON_PCH_MSI 696 bool "Loongson PCH MSI Controller" 697 depends on MACH_LOONGSON64 698 depends on PCI 699 default MACH_LOONGSON64 700 select IRQ_DOMAIN_HIERARCHY 701 select IRQ_MSI_LIB 702 select PCI_MSI 703 help 704 Support for the Loongson PCH MSI Controller. 705 706config LOONGSON_PCH_LPC 707 bool "Loongson PCH LPC Controller" 708 depends on LOONGARCH 709 depends on MACH_LOONGSON64 710 default MACH_LOONGSON64 711 select IRQ_DOMAIN_HIERARCHY 712 help 713 Support for the Loongson PCH LPC Controller. 714 715config MST_IRQ 716 bool "MStar Interrupt Controller" 717 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 718 default ARCH_MEDIATEK 719 select IRQ_DOMAIN 720 select IRQ_DOMAIN_HIERARCHY 721 help 722 Support MStar Interrupt Controller. 723 724config WPCM450_AIC 725 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 726 depends on ARCH_WPCM450 727 help 728 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 729 730config IRQ_IDT3243X 731 bool 732 select GENERIC_IRQ_CHIP 733 select IRQ_DOMAIN 734 735config APPLE_AIC 736 bool "Apple Interrupt Controller (AIC)" 737 depends on ARM64 738 depends on ARCH_APPLE || COMPILE_TEST 739 select GENERIC_IRQ_IPI_MUX 740 help 741 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 742 such as the M1. 743 744config MCHP_EIC 745 bool "Microchip External Interrupt Controller" 746 depends on ARCH_AT91 || COMPILE_TEST 747 select IRQ_DOMAIN 748 select IRQ_DOMAIN_HIERARCHY 749 help 750 Support for Microchip External Interrupt Controller. 751 752config SUNPLUS_SP7021_INTC 753 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 754 default SOC_SP7021 755 help 756 Support for the Sunplus SP7021 Interrupt Controller IP core. 757 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 758 chained controller, routing all interrupt source in P-Chip to 759 the primary controller on C-Chip. 760 761endmenu 762