xref: /freebsd/sys/dev/mii/lxtphyreg.h (revision 71625ec9ad2a9bc8c09784fbd23b759830e0ee5f)
1 /*	OpenBSD: lxtphyreg.h,v 1.1 1998/11/11 19:34:47 jason Exp 	*/
2 /*	NetBSD: lxtphyreg.h,v 1.1 1998/10/24 00:33:17 thorpej Exp 	*/
3 
4 /*-
5  * SPDX-License-Identifier: BSD-2-Clause
6  *
7  * Copyright (c) 1998 The NetBSD Foundation, Inc.
8  * All rights reserved.
9  *
10  * This code is derived from software contributed to The NetBSD Foundation
11  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
12  * NASA Ames Research Center.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in the
21  *    documentation and/or other materials provided with the distribution.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  * POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef _DEV_MII_LXTPHYREG_H_
37 #define	_DEV_MII_LXTPHYREG_H_
38 
39 /*
40  * LXT970 registers.
41  */
42 
43 #define	MII_LXTPHY_MIRROR	0x10	/* Mirror register */
44 	/* All bits user-defined */
45 
46 #define	MII_LXTPHY_IER		0x11	/* Interrupt Enable Register */
47 #define	IER_MIIDRVLVL		0x0008	/* Rediced MII driver levels */
48 #define	IER_LNK_CRITERIA	0x0004	/* Enhanced Link Loss Criteria */
49 #define	IER_INTEN		0x0002	/* Interrupt Enable */
50 #define	IER_TINT		0x0001	/* Force Interrupt */
51 
52 #define	MII_LXTPHY_ISR		0x12	/* Interrupt Status Register */
53 #define	ISR_MINT		0x8000	/* MII Interrupt Pending */
54 #define	ISR_XTALOK		0x4000	/* Clocks OK */
55 
56 #define	MII_LXTPHY_CONFIG	0x13	/* Configuration Register */
57 #define	CONFIG_TXMIT_TEST	0x4000	/* 100base-T Transmit Test */
58 #define	CONFIG_REPEATER		0x2000	/* Repeater Mode */
59 #define	CONFIG_MDIO_INT		0x1000	/* Enable intr signalling on MDIO */
60 #define	CONFIG_TPLOOP		0x0800	/* Disable 10base-T Loopback */
61 #define	CONFIG_SQE		0x0400	/* Enable SQE */
62 #define	CONFIG_DISJABBER	0x0200	/* Disable Jabber */
63 #define	CONFIG_DISLINKTEST	0x0100	/* Disable Link Test */
64 #define	CONFIG_LEDC1		0x0080	/* LEDC configuration */
65 #define	CONFIG_LEDC0		0x0040	/* ... */
66 					/* 0 0 LEDC indicates collision */
67 					/* 0 1 LEDC is off */
68 					/* 1 0 LEDC indicates activity */
69 					/* 1 1 LEDC is on */
70 #define	CONFIG_ADVTXCLK		0x0020	/* Advance TX clock */
71 #define	CONFIG_5BSYMBOL		0x0010	/* 5-bit Symbol mode */
72 #define	CONFIG_SCRAMBLER	0x0008	/* Bypass scrambler */
73 #define	CONFIG_100BASEFX	0x0004	/* 100base-FX */
74 #define	CONFIG_TXDISCON		0x0001	/* Disconnect TP transmitter */
75 
76 #define	MII_LXTPHY_CSR		0x14	/* Chip Status Register */
77 #define	CSR_LINK		0x2000	/* Link is up */
78 #define	CSR_DUPLEX		0x1000	/* Full-duplex */
79 #define	CSR_SPEED		0x0800	/* 100Mbps */
80 #define	CSR_ACOMP		0x0400	/* Autonegotiation complete */
81 #define	CSR_PAGERCVD		0x0200	/* Link page received */
82 #define	CSR_LOWVCC		0x0004	/* Low Voltage Fault */
83 
84 #endif /* _DEV_MII_LXTPHYREG_H_ */
85