1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select PARTITION_PERCPU 40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 41 select HAVE_ARM_SMCCC_DISCOVERY 42 select IRQ_MSI_IOMMU 43 44config ARM_GIC_ITS_PARENT 45 bool 46 47config ARM_GIC_V3_ITS 48 bool 49 select GENERIC_MSI_IRQ 50 select IRQ_MSI_LIB 51 select ARM_GIC_ITS_PARENT 52 default ARM_GIC_V3 53 select IRQ_MSI_IOMMU 54 55config ARM_GIC_V3_ITS_FSL_MC 56 bool 57 depends on ARM_GIC_V3_ITS 58 depends on FSL_MC_BUS 59 default ARM_GIC_V3_ITS 60 61config ARM_GIC_V5 62 bool 63 select IRQ_DOMAIN_HIERARCHY 64 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 65 select GENERIC_MSI_IRQ 66 select IRQ_MSI_LIB 67 select ARM_GIC_ITS_PARENT 68 69config ARM_NVIC 70 bool 71 select IRQ_DOMAIN_HIERARCHY 72 select GENERIC_IRQ_CHIP 73 74config ARM_VIC 75 bool 76 select IRQ_DOMAIN 77 78config ARM_VIC_NR 79 int 80 default 4 if ARCH_S5PV210 81 default 2 82 depends on ARM_VIC 83 help 84 The maximum number of VICs available in the system, for 85 power management. 86 87config IRQ_MSI_LIB 88 bool 89 select GENERIC_MSI_IRQ 90 91config ARMADA_370_XP_IRQ 92 bool 93 select GENERIC_IRQ_CHIP 94 select PCI_MSI if PCI 95 select IRQ_MSI_LIB if PCI 96 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 97 98config ALPINE_MSI 99 bool 100 depends on PCI 101 select PCI_MSI 102 select IRQ_MSI_LIB 103 select GENERIC_IRQ_CHIP 104 105config AL_FIC 106 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 107 depends on OF 108 depends on HAS_IOMEM 109 select GENERIC_IRQ_CHIP 110 select IRQ_DOMAIN 111 help 112 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 113 114config ATMEL_AIC_IRQ 115 bool 116 select GENERIC_IRQ_CHIP 117 select IRQ_DOMAIN 118 select SPARSE_IRQ 119 120config ATMEL_AIC5_IRQ 121 bool 122 select GENERIC_IRQ_CHIP 123 select IRQ_DOMAIN 124 select SPARSE_IRQ 125 126config I8259 127 bool 128 select IRQ_DOMAIN 129 130config BCM2712_MIP 131 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 132 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 133 default m if ARCH_BRCMSTB || ARCH_BCM2835 134 depends on ARM_GIC 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN_HIERARCHY 137 select GENERIC_MSI_IRQ 138 select IRQ_MSI_LIB 139 help 140 Enable support for the Broadcom BCM2712 MSI-X target peripheral 141 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 142 Raspberry Pi 5. 143 144 If unsure say n. 145 146config BCM6345_L1_IRQ 147 bool 148 select GENERIC_IRQ_CHIP 149 select IRQ_DOMAIN 150 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 151 152config BCM7038_L1_IRQ 153 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 154 depends on ARCH_BRCMSTB || BMIPS_GENERIC 155 default ARCH_BRCMSTB || BMIPS_GENERIC 156 select GENERIC_IRQ_CHIP 157 select IRQ_DOMAIN 158 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 159 160config BCM7120_L2_IRQ 161 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 162 depends on ARCH_BRCMSTB || BMIPS_GENERIC 163 default ARCH_BRCMSTB || BMIPS_GENERIC 164 select GENERIC_IRQ_CHIP 165 select IRQ_DOMAIN 166 167config BRCMSTB_L2_IRQ 168 tristate "Broadcom STB generic L2 interrupt controller driver" 169 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 170 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 171 select GENERIC_IRQ_CHIP 172 select IRQ_DOMAIN 173 174config DAVINCI_CP_INTC 175 bool 176 select GENERIC_IRQ_CHIP 177 select IRQ_DOMAIN 178 179config DW_APB_ICTL 180 bool 181 select GENERIC_IRQ_CHIP 182 select IRQ_DOMAIN_HIERARCHY 183 184config ECONET_EN751221_INTC 185 bool 186 select GENERIC_IRQ_CHIP 187 select IRQ_DOMAIN 188 189config FARADAY_FTINTC010 190 bool 191 select IRQ_DOMAIN 192 select SPARSE_IRQ 193 194config HISILICON_IRQ_MBIGEN 195 bool 196 select ARM_GIC_V3 197 select ARM_GIC_V3_ITS 198 199config IMGPDC_IRQ 200 bool 201 select GENERIC_IRQ_CHIP 202 select IRQ_DOMAIN 203 204config IXP4XX_IRQ 205 bool 206 select IRQ_DOMAIN 207 select SPARSE_IRQ 208 209config LAN966X_OIC 210 tristate "Microchip LAN966x OIC Support" 211 depends on MCHP_LAN966X_PCI || COMPILE_TEST 212 select GENERIC_IRQ_CHIP 213 select IRQ_DOMAIN 214 help 215 Enable support for the LAN966x Outbound Interrupt Controller. 216 This controller is present on the Microchip LAN966x PCI device and 217 maps the internal interrupts sources to PCIe interrupt. 218 219 To compile this driver as a module, choose M here: the module 220 will be called irq-lan966x-oic. 221 222config MADERA_IRQ 223 tristate 224 225config IRQ_MIPS_CPU 226 bool 227 select GENERIC_IRQ_CHIP 228 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 229 select IRQ_DOMAIN 230 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 231 232config CLPS711X_IRQCHIP 233 bool 234 depends on ARCH_CLPS711X 235 select IRQ_DOMAIN 236 select SPARSE_IRQ 237 default y 238 239config OMPIC 240 bool 241 242config OR1K_PIC 243 bool 244 select IRQ_DOMAIN 245 246config OMAP_IRQCHIP 247 bool 248 select GENERIC_IRQ_CHIP 249 select IRQ_DOMAIN 250 251config ORION_IRQCHIP 252 bool 253 select IRQ_DOMAIN 254 255config PIC32_EVIC 256 bool 257 select GENERIC_IRQ_CHIP 258 select IRQ_DOMAIN 259 260config JCORE_AIC 261 bool "J-Core integrated AIC" if COMPILE_TEST 262 depends on OF 263 select IRQ_DOMAIN 264 help 265 Support for the J-Core integrated AIC. 266 267config RDA_INTC 268 bool 269 select IRQ_DOMAIN 270 271config RENESAS_INTC_IRQPIN 272 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 273 select IRQ_DOMAIN 274 help 275 Enable support for the Renesas Interrupt Controller for external 276 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 277 278config RENESAS_IRQC 279 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 280 select GENERIC_IRQ_CHIP 281 select IRQ_DOMAIN 282 help 283 Enable support for the Renesas Interrupt Controller for external 284 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 285 286config RENESAS_RZA1_IRQC 287 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 288 select IRQ_DOMAIN_HIERARCHY 289 help 290 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 291 to 8 external interrupts with configurable sense select. 292 293config RENESAS_RZG2L_IRQC 294 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 295 select GENERIC_IRQ_CHIP 296 select IRQ_DOMAIN_HIERARCHY 297 help 298 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 299 for external devices. 300 301config RENESAS_RZV2H_ICU 302 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 303 select GENERIC_IRQ_CHIP 304 select IRQ_DOMAIN_HIERARCHY 305 help 306 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 307 308config SL28CPLD_INTC 309 bool "Kontron sl28cpld IRQ controller" 310 depends on MFD_SL28CPLD=y || COMPILE_TEST 311 select REGMAP_IRQ 312 help 313 Interrupt controller driver for the board management controller 314 found on the Kontron sl28 CPLD. 315 316config ST_IRQCHIP 317 bool 318 select REGMAP 319 select MFD_SYSCON 320 help 321 Enables SysCfg Controlled IRQs on STi based platforms. 322 323config SUN4I_INTC 324 bool 325 326config SUN6I_R_INTC 327 bool 328 select IRQ_DOMAIN_HIERARCHY 329 select IRQ_FASTEOI_HIERARCHY_HANDLERS 330 331config SUNXI_NMI_INTC 332 bool 333 select GENERIC_IRQ_CHIP 334 335config TB10X_IRQC 336 bool 337 select IRQ_DOMAIN 338 select GENERIC_IRQ_CHIP 339 340config TS4800_IRQ 341 tristate "TS-4800 IRQ controller" 342 select IRQ_DOMAIN 343 depends on HAS_IOMEM 344 depends on SOC_IMX51 || COMPILE_TEST 345 help 346 Support for the TS-4800 FPGA IRQ controller 347 348config VERSATILE_FPGA_IRQ 349 bool 350 select IRQ_DOMAIN 351 352config VERSATILE_FPGA_IRQ_NR 353 int 354 default 4 355 depends on VERSATILE_FPGA_IRQ 356 357config XTENSA_MX 358 bool 359 select IRQ_DOMAIN 360 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 361 362config XILINX_INTC 363 bool "Xilinx Interrupt Controller IP" 364 depends on OF_ADDRESS 365 select IRQ_DOMAIN 366 help 367 Support for the Xilinx Interrupt Controller IP core. 368 This is used as a primary controller with MicroBlaze and can also 369 be used as a secondary chained controller on other platforms. 370 371config IRQ_CROSSBAR 372 bool 373 help 374 Support for a CROSSBAR ip that precedes the main interrupt controller. 375 The primary irqchip invokes the crossbar's callback which inturn allocates 376 a free irq and configures the IP. Thus the peripheral interrupts are 377 routed to one of the free irqchip interrupt lines. 378 379config KEYSTONE_IRQ 380 tristate "Keystone 2 IRQ controller IP" 381 depends on ARCH_KEYSTONE 382 help 383 Support for Texas Instruments Keystone 2 IRQ controller IP which 384 is part of the Keystone 2 IPC mechanism 385 386config MIPS_GIC 387 bool 388 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 389 select GENERIC_IRQ_IPI if SMP 390 select IRQ_DOMAIN_HIERARCHY 391 select MIPS_CM 392 393config INGENIC_IRQ 394 bool 395 depends on MACH_INGENIC 396 default y 397 398config INGENIC_TCU_IRQ 399 bool "Ingenic JZ47xx TCU interrupt controller" 400 default MACH_INGENIC 401 depends on MIPS || COMPILE_TEST 402 select MFD_SYSCON 403 select GENERIC_IRQ_CHIP 404 help 405 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 406 JZ47xx SoCs. 407 408 If unsure, say N. 409 410config IMX_GPCV2 411 bool 412 select IRQ_DOMAIN 413 help 414 Enables the wakeup IRQs for IMX platforms with GPCv2 block 415 416config IRQ_MXS 417 def_bool y if MACH_ASM9260 || ARCH_MXS 418 select IRQ_DOMAIN 419 select STMP_DEVICE 420 421config MSCC_OCELOT_IRQ 422 bool 423 select IRQ_DOMAIN 424 select GENERIC_IRQ_CHIP 425 426config MVEBU_GICP 427 select IRQ_MSI_LIB 428 bool 429 430config MVEBU_ICU 431 bool 432 433config MVEBU_ODMI 434 bool 435 select IRQ_MSI_LIB 436 select GENERIC_MSI_IRQ 437 438config MVEBU_PIC 439 bool 440 441config MVEBU_SEI 442 bool 443 444config LS_EXTIRQ 445 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 446 select MFD_SYSCON 447 448config LS_SCFG_MSI 449 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 450 select IRQ_MSI_IOMMU 451 depends on PCI_MSI 452 select IRQ_MSI_LIB 453 454config PARTITION_PERCPU 455 bool 456 457config STM32MP_EXTI 458 tristate "STM32MP extended interrupts and event controller" 459 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 460 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 461 select IRQ_DOMAIN_HIERARCHY 462 select GENERIC_IRQ_CHIP 463 help 464 Support STM32MP EXTI (extended interrupts and event) controller. 465 466config STM32_EXTI 467 bool 468 select IRQ_DOMAIN 469 select GENERIC_IRQ_CHIP 470 471config QCOM_IRQ_COMBINER 472 bool "QCOM IRQ combiner support" 473 depends on ARCH_QCOM && ACPI 474 select IRQ_DOMAIN_HIERARCHY 475 help 476 Say yes here to add support for the IRQ combiner devices embedded 477 in Qualcomm Technologies chips. 478 479config IRQ_UNIPHIER_AIDET 480 bool "UniPhier AIDET support" if COMPILE_TEST 481 depends on ARCH_UNIPHIER || COMPILE_TEST 482 default ARCH_UNIPHIER 483 select IRQ_DOMAIN_HIERARCHY 484 help 485 Support for the UniPhier AIDET (ARM Interrupt Detector). 486 487config MESON_IRQ_GPIO 488 tristate "Meson GPIO Interrupt Multiplexer" 489 depends on ARCH_MESON || COMPILE_TEST 490 default ARCH_MESON 491 select IRQ_DOMAIN_HIERARCHY 492 help 493 Support Meson SoC Family GPIO Interrupt Multiplexer 494 495config GOLDFISH_PIC 496 bool "Goldfish programmable interrupt controller" 497 depends on MIPS && (GOLDFISH || COMPILE_TEST) 498 select GENERIC_IRQ_CHIP 499 select IRQ_DOMAIN 500 help 501 Say yes here to enable Goldfish interrupt controller driver used 502 for Goldfish based virtual platforms. 503 504config QCOM_PDC 505 tristate "QCOM PDC" 506 depends on ARCH_QCOM 507 select IRQ_DOMAIN_HIERARCHY 508 help 509 Power Domain Controller driver to manage and configure wakeup 510 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 511 512config QCOM_MPM 513 tristate "QCOM MPM" 514 depends on ARCH_QCOM 515 depends on MAILBOX 516 select IRQ_DOMAIN_HIERARCHY 517 help 518 MSM Power Manager driver to manage and configure wakeup 519 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 520 521config CSKY_MPINTC 522 bool 523 depends on CSKY 524 help 525 Say yes here to enable C-SKY SMP interrupt controller driver used 526 for C-SKY SMP system. 527 In fact it's not mmio map in hardware and it uses ld/st to visit the 528 controller's register inside CPU. 529 530config CSKY_APB_INTC 531 bool "C-SKY APB Interrupt Controller" 532 depends on CSKY 533 help 534 Say yes here to enable C-SKY APB interrupt controller driver used 535 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 536 the controller's register. 537 538config IMX_IRQSTEER 539 bool "i.MX IRQSTEER support" 540 depends on ARCH_MXC || COMPILE_TEST 541 default ARCH_MXC 542 select IRQ_DOMAIN 543 help 544 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 545 546config IMX_INTMUX 547 bool "i.MX INTMUX support" if COMPILE_TEST 548 default y if ARCH_MXC 549 select IRQ_DOMAIN 550 help 551 Support for the i.MX INTMUX interrupt multiplexer. 552 553config IMX_MU_MSI 554 tristate "i.MX MU used as MSI controller" 555 depends on OF && HAS_IOMEM 556 depends on ARCH_MXC || COMPILE_TEST 557 default m if ARCH_MXC 558 select IRQ_DOMAIN 559 select IRQ_DOMAIN_HIERARCHY 560 select GENERIC_MSI_IRQ 561 select IRQ_MSI_LIB 562 help 563 Provide a driver for the i.MX Messaging Unit block used as a 564 CPU-to-CPU MSI controller. This requires a specially crafted DT 565 to make use of this driver. 566 567 If unsure, say N 568 569config LS1X_IRQ 570 bool "Loongson-1 Interrupt Controller" 571 depends on MACH_LOONGSON32 572 default y 573 select IRQ_DOMAIN 574 select GENERIC_IRQ_CHIP 575 help 576 Support for the Loongson-1 platform Interrupt Controller. 577 578config TI_SCI_INTR_IRQCHIP 579 tristate "TI SCI INTR Interrupt Controller" 580 depends on TI_SCI_PROTOCOL 581 depends on ARCH_K3 || COMPILE_TEST 582 select IRQ_DOMAIN_HIERARCHY 583 help 584 This enables the irqchip driver support for K3 Interrupt router 585 over TI System Control Interface available on some new TI's SoCs. 586 If you wish to use interrupt router irq resources managed by the 587 TI System Controller, say Y here. Otherwise, say N. 588 589config TI_SCI_INTA_IRQCHIP 590 tristate "TI SCI INTA Interrupt Controller" 591 depends on TI_SCI_PROTOCOL 592 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 593 select IRQ_DOMAIN_HIERARCHY 594 select TI_SCI_INTA_MSI_DOMAIN 595 help 596 This enables the irqchip driver support for K3 Interrupt aggregator 597 over TI System Control Interface available on some new TI's SoCs. 598 If you wish to use interrupt aggregator irq resources managed by the 599 TI System Controller, say Y here. Otherwise, say N. 600 601config TI_PRUSS_INTC 602 tristate 603 depends on TI_PRUSS 604 default TI_PRUSS 605 select IRQ_DOMAIN 606 help 607 This enables support for the PRU-ICSS Local Interrupt Controller 608 present within a PRU-ICSS subsystem present on various TI SoCs. 609 The PRUSS INTC enables various interrupts to be routed to multiple 610 different processors within the SoC. 611 612config RISCV_INTC 613 bool 614 depends on RISCV 615 select IRQ_DOMAIN_HIERARCHY 616 617config RISCV_APLIC 618 bool 619 depends on RISCV 620 select IRQ_DOMAIN_HIERARCHY 621 622config RISCV_APLIC_MSI 623 bool 624 depends on RISCV_APLIC 625 select GENERIC_MSI_IRQ 626 default RISCV_APLIC 627 628config RISCV_IMSIC 629 bool 630 depends on RISCV 631 select IRQ_DOMAIN_HIERARCHY 632 select GENERIC_IRQ_MATRIX_ALLOCATOR 633 select GENERIC_MSI_IRQ 634 select IRQ_MSI_LIB 635 636config SIFIVE_PLIC 637 bool 638 depends on RISCV 639 select IRQ_DOMAIN_HIERARCHY 640 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 641 642config STARFIVE_JH8100_INTC 643 bool "StarFive JH8100 External Interrupt Controller" 644 depends on ARCH_STARFIVE || COMPILE_TEST 645 default ARCH_STARFIVE 646 select IRQ_DOMAIN_HIERARCHY 647 help 648 This enables support for the INTC chip found in StarFive JH8100 649 SoC. 650 651 If you don't know what to do here, say Y. 652 653config ACLINT_SSWI 654 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 655 depends on RISCV 656 depends on SMP 657 select IRQ_DOMAIN_HIERARCHY 658 select GENERIC_IRQ_IPI_MUX 659 help 660 This enables support for variants of the RISC-V ACLINT-SSWI device. 661 Supported variants are: 662 - T-HEAD, with compatible "thead,c900-aclint-sswi" 663 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 664 665 If you don't know what to do here, say Y. 666 667# Backwards compatibility so oldconfig does not drop it. 668config THEAD_C900_ACLINT_SSWI 669 bool 670 select ACLINT_SSWI 671 672config EXYNOS_IRQ_COMBINER 673 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 674 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 675 help 676 Say yes here to add support for the IRQ combiner devices embedded 677 in Samsung Exynos chips. 678 679config IRQ_LOONGARCH_CPU 680 bool 681 select GENERIC_IRQ_CHIP 682 select IRQ_DOMAIN 683 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 684 select LOONGSON_HTVEC 685 select LOONGSON_LIOINTC 686 select LOONGSON_EIOINTC 687 select LOONGSON_PCH_PIC 688 select LOONGSON_PCH_MSI 689 select LOONGSON_PCH_LPC 690 help 691 Support for the LoongArch CPU Interrupt Controller. For details of 692 irq chip hierarchy on LoongArch platforms please read the document 693 Documentation/arch/loongarch/irq-chip-model.rst. 694 695config LOONGSON_LIOINTC 696 bool "Loongson Local I/O Interrupt Controller" 697 depends on MACH_LOONGSON64 698 default y 699 select IRQ_DOMAIN 700 select GENERIC_IRQ_CHIP 701 help 702 Support for the Loongson Local I/O Interrupt Controller. 703 704config LOONGSON_EIOINTC 705 bool "Loongson Extend I/O Interrupt Controller" 706 depends on LOONGARCH 707 depends on MACH_LOONGSON64 708 default MACH_LOONGSON64 709 select IRQ_DOMAIN_HIERARCHY 710 select GENERIC_IRQ_CHIP 711 help 712 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 713 714config LOONGSON_HTPIC 715 bool "Loongson3 HyperTransport PIC Controller" 716 depends on MACH_LOONGSON64 && MIPS 717 default y 718 select IRQ_DOMAIN 719 select GENERIC_IRQ_CHIP 720 help 721 Support for the Loongson-3 HyperTransport PIC Controller. 722 723config LOONGSON_HTVEC 724 bool "Loongson HyperTransport Interrupt Vector Controller" 725 depends on MACH_LOONGSON64 726 default MACH_LOONGSON64 727 select IRQ_DOMAIN_HIERARCHY 728 help 729 Support for the Loongson HyperTransport Interrupt Vector Controller. 730 731config LOONGSON_PCH_PIC 732 bool "Loongson PCH PIC Controller" 733 depends on MACH_LOONGSON64 734 default MACH_LOONGSON64 735 select IRQ_DOMAIN_HIERARCHY 736 select IRQ_FASTEOI_HIERARCHY_HANDLERS 737 help 738 Support for the Loongson PCH PIC Controller. 739 740config LOONGSON_PCH_MSI 741 bool "Loongson PCH MSI Controller" 742 depends on MACH_LOONGSON64 743 depends on PCI 744 default MACH_LOONGSON64 745 select IRQ_DOMAIN_HIERARCHY 746 select IRQ_MSI_LIB 747 select PCI_MSI 748 help 749 Support for the Loongson PCH MSI Controller. 750 751config LOONGSON_PCH_LPC 752 bool "Loongson PCH LPC Controller" 753 depends on LOONGARCH 754 depends on MACH_LOONGSON64 755 default MACH_LOONGSON64 756 select IRQ_DOMAIN_HIERARCHY 757 help 758 Support for the Loongson PCH LPC Controller. 759 760config MST_IRQ 761 bool "MStar Interrupt Controller" 762 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 763 default ARCH_MEDIATEK 764 select IRQ_DOMAIN 765 select IRQ_DOMAIN_HIERARCHY 766 help 767 Support MStar Interrupt Controller. 768 769config WPCM450_AIC 770 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 771 depends on ARCH_WPCM450 772 help 773 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 774 775config IRQ_IDT3243X 776 bool 777 select GENERIC_IRQ_CHIP 778 select IRQ_DOMAIN 779 780config APPLE_AIC 781 bool "Apple Interrupt Controller (AIC)" 782 depends on ARM64 783 depends on ARCH_APPLE || COMPILE_TEST 784 select GENERIC_IRQ_IPI_MUX 785 help 786 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 787 such as the M1. 788 789config MCHP_EIC 790 bool "Microchip External Interrupt Controller" 791 depends on ARCH_AT91 || COMPILE_TEST 792 select IRQ_DOMAIN 793 select IRQ_DOMAIN_HIERARCHY 794 help 795 Support for Microchip External Interrupt Controller. 796 797config SOPHGO_SG2042_MSI 798 bool "Sophgo SG2042 MSI Controller" 799 depends on ARCH_SOPHGO || COMPILE_TEST 800 depends on PCI 801 select IRQ_DOMAIN_HIERARCHY 802 select IRQ_MSI_LIB 803 select PCI_MSI 804 help 805 Support for the Sophgo SG2042 MSI Controller. 806 This on-chip interrupt controller enables MSI sources to be 807 routed to the primary PLIC controller on SoC. 808 809config SUNPLUS_SP7021_INTC 810 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 811 default SOC_SP7021 812 help 813 Support for the Sunplus SP7021 Interrupt Controller IP core. 814 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 815 chained controller, routing all interrupt source in P-Chip to 816 the primary controller on C-Chip. 817 818endmenu 819