1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _TEGRA124_CAR_ 28 #define _TEGRA124_CAR_ 29 30 #include "clkdev_if.h" 31 32 #define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val) 33 #define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val) 34 #define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set) 35 #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 36 #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 37 38 #define RST_DEVICES_L 0x004 39 #define RST_DEVICES_H 0x008 40 #define RST_DEVICES_U 0x00C 41 #define CLK_OUT_ENB_L 0x010 42 #define CLK_OUT_ENB_H 0x014 43 #define CLK_OUT_ENB_U 0x018 44 #define CCLK_BURST_POLICY 0x020 45 #define SUPER_CCLK_DIVIDER 0x024 46 #define SCLK_BURST_POLICY 0x028 47 #define SUPER_SCLK_DIVIDER 0x02c 48 #define CLK_SYSTEM_RATE 0x030 49 50 #define OSC_CTRL 0x050 51 #define OSC_CTRL_OSC_FREQ_SHIFT 28 52 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26 53 54 #define PLLE_SS_CNTL 0x068 55 #define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24) 56 #define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24) 57 #define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16) 58 #define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16) 59 #define PLLE_SS_CNTL_SSCINVERT (1 << 15) 60 #define PLLE_SS_CNTL_SSCCENTER (1 << 14) 61 #define PLLE_SS_CNTL_SSCBYP (1 << 12) 62 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11) 63 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10) 64 #define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff 65 #define PLLE_SS_CNTL_SSCMAX_VAL 0x25 66 #define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \ 67 PLLE_SS_CNTL_INTERP_RESET | \ 68 PLLE_SS_CNTL_SSCBYP) 69 #define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \ 70 PLLE_SS_CNTL_SSCINC_MASK | \ 71 PLLE_SS_CNTL_SSCINCINTRV_MASK) 72 #define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \ 73 PLLE_SS_CNTL_SSCINC_VAL | \ 74 PLLE_SS_CNTL_SSCINCINTRV_VAL) 75 76 #define PLLC_BASE 0x080 77 #define PLLC_OUT 0x084 78 #define PLLC_MISC2 0x088 79 #define PLLC_MISC 0x08c 80 #define PLLM_BASE 0x090 81 #define PLLM_OUT 0x094 82 #define PLLM_MISC 0x09c 83 #define PLLP_BASE 0x0a0 84 #define PLLP_MISC 0x0ac 85 #define PLLP_OUTA 0x0a4 86 #define PLLP_OUTB 0x0a8 87 #define PLLA_BASE 0x0b0 88 #define PLLA_OUT 0x0b4 89 #define PLLA_MISC 0x0bc 90 #define PLLU_BASE 0x0c0 91 #define PLLU_MISC 0x0cc 92 #define PLLD_BASE 0x0d0 93 #define PLLD_MISC 0x0dc 94 #define PLLX_BASE 0x0e0 95 #define PLLX_MISC 0x0e4 96 #define PLLE_BASE 0x0e8 97 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29) 98 #define PLLE_BASE_DIVCML_SHIFT 24 99 #define PLLE_BASE_DIVCML_MASK 0xf 100 101 #define PLLE_MISC 0x0ec 102 #define PLLE_MISC_SETUP_BASE_SHIFT 16 103 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 104 #define PLLE_MISC_READY (1 << 15) 105 #define PLLE_MISC_IDDQ_SWCTL (1 << 14) 106 #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) 107 #define PLLE_MISC_LOCK (1 << 11) 108 #define PLLE_MISC_REF_ENABLE (1 << 10) 109 #define PLLE_MISC_LOCK_ENABLE (1 << 9) 110 #define PLLE_MISC_PTS (1 << 8) 111 #define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 112 #define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 113 #define PLLE_MISC_VREG_CTRL_SHIFT 2 114 #define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 115 116 #define CLK_SOURCE_I2S1 0x100 117 #define CLK_SOURCE_I2S2 0x104 118 #define CLK_SOURCE_SPDIF_OUT 0x108 119 #define CLK_SOURCE_SPDIF_IN 0x10c 120 #define CLK_SOURCE_PWM 0x110 121 #define CLK_SOURCE_SPI2 0x118 122 #define CLK_SOURCE_SPI3 0x11c 123 #define CLK_SOURCE_I2C1 0x124 124 #define CLK_SOURCE_I2C5 0x128 125 #define CLK_SOURCE_SPI1 0x134 126 #define CLK_SOURCE_DISP1 0x138 127 #define CLK_SOURCE_DISP2 0x13c 128 #define CLK_SOURCE_ISP 0x144 129 #define CLK_SOURCE_VI 0x148 130 #define CLK_SOURCE_SDMMC1 0x150 131 #define CLK_SOURCE_SDMMC2 0x154 132 #define CLK_SOURCE_SDMMC4 0x164 133 #define CLK_SOURCE_VFIR 0x168 134 #define CLK_SOURCE_HSI 0x174 135 #define CLK_SOURCE_UARTA 0x178 136 #define CLK_SOURCE_UARTB 0x17c 137 #define CLK_SOURCE_HOST1X 0x180 138 #define CLK_SOURCE_HDMI 0x18c 139 #define CLK_SOURCE_I2C2 0x198 140 #define CLK_SOURCE_EMC 0x19c 141 #define CLK_SOURCE_UARTC 0x1a0 142 #define CLK_SOURCE_VI_SENSOR 0x1a8 143 #define CLK_SOURCE_SPI4 0x1b4 144 #define CLK_SOURCE_I2C3 0x1b8 145 #define CLK_SOURCE_SDMMC3 0x1bc 146 #define CLK_SOURCE_UARTD 0x1c0 147 #define CLK_SOURCE_VDE 0x1c8 148 #define CLK_SOURCE_OWR 0x1cc 149 #define CLK_SOURCE_NOR 0x1d0 150 #define CLK_SOURCE_CSITE 0x1d4 151 #define CLK_SOURCE_I2S0 0x1d8 152 #define CLK_SOURCE_DTV 0x1dc 153 #define CLK_SOURCE_MSENC 0x1f0 154 #define CLK_SOURCE_TSEC 0x1f4 155 #define CLK_SOURCE_SPARE2 0x1f8 156 157 #define CLK_OUT_ENB_X 0x280 158 #define RST_DEVICES_X 0x28C 159 160 #define RST_DEVICES_V 0x358 161 #define RST_DEVICES_W 0x35C 162 #define CLK_OUT_ENB_V 0x360 163 #define CLK_OUT_ENB_W 0x364 164 #define CCLKG_BURST_POLICY 0x368 165 #define SUPER_CCLKG_DIVIDER 0x36C 166 #define CCLKLP_BURST_POLICY 0x370 167 #define SUPER_CCLKLP_DIVIDER 0x374 168 169 #define CLK_SOURCE_MSELECT 0x3b4 170 #define CLK_SOURCE_TSENSOR 0x3b8 171 #define CLK_SOURCE_I2S3 0x3bc 172 #define CLK_SOURCE_I2S4 0x3c0 173 #define CLK_SOURCE_I2C4 0x3c4 174 #define CLK_SOURCE_SPI5 0x3c8 175 #define CLK_SOURCE_SPI6 0x3cc 176 #define CLK_SOURCE_AUDIO 0x3d0 177 #define CLK_SOURCE_DAM0 0x3d8 178 #define CLK_SOURCE_DAM1 0x3dc 179 #define CLK_SOURCE_DAM2 0x3e0 180 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4 181 #define CLK_SOURCE_ACTMON 0x3e8 182 #define CLK_SOURCE_EXTPERIPH1 0x3ec 183 #define CLK_SOURCE_EXTPERIPH2 0x3f0 184 #define CLK_SOURCE_EXTPERIPH3 0x3f4 185 #define CLK_SOURCE_I2C_SLOW 0x3fc 186 187 #define CLK_SOURCE_SYS 0x400 188 #define CLK_SOURCE_SOR0 0x414 189 #define CLK_SOURCE_SATA_OOB 0x420 190 #define CLK_SOURCE_SATA 0x424 191 #define CLK_SOURCE_HDA 0x428 192 #define UTMIP_PLL_CFG0 0x480 193 #define UTMIP_PLL_CFG1 0x484 194 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17) 195 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) 196 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15) 197 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) 198 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) 199 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 200 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 201 202 #define UTMIP_PLL_CFG2 0x488 203 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 205 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) 206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) 207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) 208 209 #define PLLE_AUX 0x48c 210 #define PLLE_AUX_PLLRE_SEL (1 << 28) 211 #define PLLE_AUX_SEQ_START_STATE (1 << 25) 212 #define PLLE_AUX_SEQ_ENABLE (1 << 24) 213 #define PLLE_AUX_SS_SWCTL (1 << 6) 214 #define PLLE_AUX_ENABLE_SWCTL (1 << 4) 215 #define PLLE_AUX_USE_LOCKDET (1 << 3) 216 #define PLLE_AUX_PLLP_SEL (1 << 2) 217 218 #define SATA_PLL_CFG0 0x490 219 #define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25) 220 #define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24) 221 #define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7) 222 #define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6) 223 #define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 224 #define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4) 225 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2) 226 #define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1) 227 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 228 229 #define SATA_PLL_CFG1 0x494 230 #define PCIE_PLL_CFG0 0x498 231 #define PCIE_PLL_CFG0_SEQ_START_STATE (1 << 25) 232 #define PCIE_PLL_CFG0_SEQ_ENABLE (1 << 24) 233 234 #define PLLD2_BASE 0x4b8 235 #define PLLD2_MISC 0x4bc 236 #define UTMIP_PLL_CFG3 0x4c0 237 #define PLLRE_BASE 0x4c4 238 #define PLLRE_MISC 0x4c8 239 #define PLLC2_BASE 0x4e8 240 #define PLLC2_MISC 0x4ec 241 #define PLLC3_BASE 0x4fc 242 243 #define PLLC3_MISC 0x500 244 #define PLLX_MISC2 0x514 245 #define PLLX_MISC2 0x514 246 #define PLLX_MISC3 0x518 247 #define PLLX_MISC3_DYNRAMP_STEPB_MASK 0xFF 248 #define PLLX_MISC3_DYNRAMP_STEPB_SHIFT 24 249 #define PLLX_MISC3_DYNRAMP_STEPA_MASK 0xFF 250 #define PLLX_MISC3_DYNRAMP_STEPA_SHIFT 16 251 #define PLLX_MISC3_NDIV_NEW_MASK 0xFF 252 #define PLLX_MISC3_NDIV_NEW_SHIFT 8 253 #define PLLX_MISC3_EN_FSTLCK (1 << 5) 254 #define PLLX_MISC3_LOCK_OVERRIDE (1 << 4) 255 #define PLLX_MISC3_PLL_FREQLOCK (1 << 3) 256 #define PLLX_MISC3_DYNRAMP_DONE (1 << 2) 257 #define PLLX_MISC3_CLAMP_NDIV (1 << 1) 258 #define PLLX_MISC3_EN_DYNRAMP (1 << 0) 259 #define XUSBIO_PLL_CFG0 0x51c 260 #define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25) 261 #define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24) 262 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6) 263 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) 264 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0) 265 266 #define PLLP_RESHIFT 0x528 267 #define UTMIPLL_HW_PWRDN_CFG0 0x52c 268 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25) 269 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24) 270 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6) 271 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5) 272 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4) 273 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2) 274 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1) 275 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0) 276 277 #define PLLDP_BASE 0x590 278 #define PLLDP_MISC 0x594 279 #define PLLC4_BASE 0x5a4 280 #define PLLC4_MISC 0x5a8 281 282 #define CLK_SOURCE_XUSB_CORE_HOST 0x600 283 #define CLK_SOURCE_XUSB_FALCON 0x604 284 #define CLK_SOURCE_XUSB_FS 0x608 285 #define CLK_SOURCE_XUSB_CORE_DEV 0x60c 286 #define CLK_SOURCE_XUSB_SS 0x610 287 #define CLK_SOURCE_CILAB 0x614 288 #define CLK_SOURCE_CILCD 0x618 289 #define CLK_SOURCE_CILE 0x61c 290 #define CLK_SOURCE_DSIA_LP 0x620 291 #define CLK_SOURCE_DSIB_LP 0x624 292 #define CLK_SOURCE_ENTROPY 0x628 293 #define CLK_SOURCE_DVFS_REF 0x62c 294 #define CLK_SOURCE_DVFS_SOC 0x630 295 #define CLK_SOURCE_TRACECLKIN 0x634 296 #define CLK_SOURCE_ADX 0x638 297 #define CLK_SOURCE_AMX 0x63c 298 #define CLK_SOURCE_EMC_LATENCY 0x640 299 #define CLK_SOURCE_SOC_THERM 0x644 300 #define CLK_SOURCE_VI_SENSOR2 0x658 301 #define CLK_SOURCE_I2C6 0x65c 302 #define CLK_SOURCE_EMC_DLL 0x664 303 #define CLK_SOURCE_HDMI_AUDIO 0x668 304 #define CLK_SOURCE_CLK72MHZ 0x66c 305 #define CLK_SOURCE_ADX1 0x670 306 #define CLK_SOURCE_AMX1 0x674 307 #define CLK_SOURCE_VIC 0x678 308 #define PLLP_OUTC 0x67c 309 #define PLLP_MISC1 0x680 310 311 struct tegra124_car_softc { 312 device_t dev; 313 struct resource * mem_res; 314 struct mtx mtx; 315 struct clkdom *clkdom; 316 int type; 317 }; 318 319 struct tegra124_init_item { 320 char *name; 321 char *parent; 322 uint64_t frequency; 323 int enable; 324 }; 325 326 void tegra124_init_plls(struct tegra124_car_softc *sc); 327 328 void tegra124_periph_clock(struct tegra124_car_softc *sc); 329 void tegra124_super_mux_clock(struct tegra124_car_softc *sc); 330 331 int tegra124_hwreset_by_idx(struct tegra124_car_softc *sc, intptr_t idx, 332 bool reset); 333 334 #endif /*_TEGRA124_CAR_*/ 335