xref: /linux/drivers/clk/renesas/r9a07g044-cpg.c (revision 619b92b9c8fe5369503ae948ad4e0a9c195c2c4a)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * RZ/G2L CPG driver
4  *
5  * Copyright (C) 2021 Renesas Electronics Corp.
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/device.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 
13 #include <dt-bindings/clock/r9a07g044-cpg.h>
14 #include <dt-bindings/clock/r9a07g054-cpg.h>
15 
16 #include "rzg2l-cpg.h"
17 
18 /* Specific registers. */
19 #define CPG_PL2SDHI_DSEL	(0x218)
20 
21 /* Clock select configuration. */
22 #define SEL_SDHI0		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2)
23 #define SEL_SDHI1		SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2)
24 
25 /* Clock status configuration. */
26 #define SEL_SDHI0_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1)
27 #define SEL_SDHI1_STS		SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1)
28 
29 enum clk_ids {
30 	/* Core Clock Outputs exported to DT */
31 	LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A,
32 
33 	/* External Input Clocks */
34 	CLK_EXTAL,
35 
36 	/* Internal Core Clocks */
37 	CLK_OSC_DIV1000,
38 	CLK_PLL1,
39 	CLK_PLL2,
40 	CLK_PLL2_DIV2,
41 	CLK_PLL2_DIV2_8,
42 	CLK_PLL2_DIV2_10,
43 	CLK_PLL3,
44 	CLK_PLL3_400,
45 	CLK_PLL3_533,
46 	CLK_M2_DIV2,
47 	CLK_PLL3_DIV2,
48 	CLK_PLL3_DIV2_2,
49 	CLK_PLL3_DIV2_4,
50 	CLK_PLL3_DIV2_4_2,
51 	CLK_SEL_PLL3_3,
52 	CLK_DIV_PLL3_C,
53 	CLK_PLL4,
54 	CLK_PLL5,
55 	CLK_PLL5_FOUTPOSTDIV,
56 	CLK_PLL5_FOUT1PH0,
57 	CLK_PLL5_FOUT3,
58 	CLK_PLL5_250,
59 	CLK_PLL6,
60 	CLK_PLL6_250,
61 	CLK_P1_DIV2,
62 	CLK_PLL2_800,
63 	CLK_PLL2_SDHI_533,
64 	CLK_PLL2_SDHI_400,
65 	CLK_PLL2_SDHI_266,
66 	CLK_SD0_DIV4,
67 	CLK_SD1_DIV4,
68 	CLK_SEL_GPU2,
69 	CLK_SEL_PLL5_4,
70 	CLK_DSI_DIV,
71 	CLK_PLL2_533,
72 	CLK_PLL2_533_DIV2,
73 	CLK_DIV_DSI_LPCLK,
74 
75 	/* Module Clocks */
76 	MOD_CLK_BASE,
77 };
78 
79 /* Divider tables */
80 static const struct clk_div_table dtable_1_8[] = {
81 	{0, 1},
82 	{1, 2},
83 	{2, 4},
84 	{3, 8},
85 	{0, 0},
86 };
87 
88 static const struct clk_div_table dtable_1_32[] = {
89 	{0, 1},
90 	{1, 2},
91 	{2, 4},
92 	{3, 8},
93 	{4, 32},
94 	{0, 0},
95 };
96 
97 static const struct clk_div_table dtable_16_128[] = {
98 	{0, 16},
99 	{1, 32},
100 	{2, 64},
101 	{3, 128},
102 	{0, 0},
103 };
104 
105 /* Mux clock tables */
106 static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
107 static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
108 static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };
109 static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };
110 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
111 
112 static const u32 mtable_sdhi[] = { 1, 2, 3 };
113 
114 static const struct {
115 	struct cpg_core_clk common[56];
116 #ifdef CONFIG_CLK_R9A07G054
117 	struct cpg_core_clk drp[0];
118 #endif
119 } core_clks __initconst = {
120 	.common = {
121 		/* External Clock Inputs */
122 		DEF_INPUT("extal", CLK_EXTAL),
123 
124 		/* Internal Core Clocks */
125 		DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
126 		DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
127 		DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
128 		DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
129 		DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
130 		DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
131 		DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
132 		DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
133 
134 		DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
135 		DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
136 
137 		DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
138 
139 		DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
140 		DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
141 		DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3),
142 		DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2),
143 		DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2),
144 
145 		DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
146 		DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
147 
148 		DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2),
149 
150 		DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
151 		DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
152 		DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
153 		DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
154 		DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
155 		DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
156 
157 		DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
158 		DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
159 		DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2),
160 		DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
161 		DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
162 		DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
163 		DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
164 			DIVDSILPCLK, dtable_16_128),
165 
166 		/* Core output clk */
167 		DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
168 		DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
169 		DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
170 		DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
171 		DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
172 		DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
173 		DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
174 		DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
175 		DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
176 		DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
177 		DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
178 		DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
179 		DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,
180 			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
181 		DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi,
182 			   mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier),
183 		DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
184 		DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
185 		DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
186 		DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
187 		DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
188 		DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
189 		DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
190 		DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
191 		DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1),
192 	},
193 #ifdef CONFIG_CLK_R9A07G054
194 	.drp = {
195 	},
196 #endif
197 };
198 
199 static const struct {
200 	struct rzg2l_mod_clk common[79];
201 #ifdef CONFIG_CLK_R9A07G054
202 	struct rzg2l_mod_clk drp[0];
203 #endif
204 } mod_clks = {
205 	.common = {
206 		DEF_MOD("gic",		R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
207 					0x514, 0),
208 		DEF_MOD("ia55_pclk",	R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
209 					0x518, 0),
210 		DEF_MOD("ia55_clk",	R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
211 					0x518, 1),
212 		DEF_MOD("dmac_aclk",	R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
213 					0x52c, 0),
214 		DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
215 					0x52c, 1),
216 		DEF_MOD("ostm0_pclk",	R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
217 					0x534, 0),
218 		DEF_MOD("ostm1_pclk",	R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
219 					0x534, 1),
220 		DEF_MOD("ostm2_pclk",	R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
221 					0x534, 2),
222 		DEF_MOD("mtu_x_mck",	R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
223 					0x538, 0),
224 		DEF_MOD("gpt_pclk",	R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
225 					0x540, 0),
226 		DEF_MOD("poeg_a_clkp",	R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
227 					0x544, 0),
228 		DEF_MOD("poeg_b_clkp",	R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
229 					0x544, 1),
230 		DEF_MOD("poeg_c_clkp",	R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
231 					0x544, 2),
232 		DEF_MOD("poeg_d_clkp",	R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
233 					0x544, 3),
234 		DEF_MOD("wdt0_pclk",	R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
235 					0x548, 0),
236 		DEF_MOD("wdt0_clk",	R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
237 					0x548, 1),
238 		DEF_MOD("wdt1_pclk",	R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0,
239 					0x548, 2),
240 		DEF_MOD("wdt1_clk",	R9A07G044_WDT1_CLK, R9A07G044_OSCCLK,
241 					0x548, 3),
242 		DEF_MOD("spi_clk2",	R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1,
243 					0x550, 0),
244 		DEF_MOD("spi_clk",	R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0,
245 					0x550, 1),
246 		DEF_MOD("sdhi0_imclk",	R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4,
247 					0x554, 0),
248 		DEF_MOD("sdhi0_imclk2",	R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4,
249 					0x554, 1),
250 		DEF_MOD("sdhi0_clk_hs",	R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0,
251 					0x554, 2),
252 		DEF_MOD("sdhi0_aclk",	R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1,
253 					0x554, 3),
254 		DEF_MOD("sdhi1_imclk",	R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4,
255 					0x554, 4),
256 		DEF_MOD("sdhi1_imclk2",	R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4,
257 					0x554, 5),
258 		DEF_MOD("sdhi1_clk_hs",	R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1,
259 					0x554, 6),
260 		DEF_MOD("sdhi1_aclk",	R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1,
261 					0x554, 7),
262 		DEF_MOD("gpu_clk",	R9A07G044_GPU_CLK, R9A07G044_CLK_G,
263 					0x558, 0),
264 		DEF_MOD("gpu_axi_clk",	R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1,
265 					0x558, 1),
266 		DEF_MOD("gpu_ace_clk",	R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
267 					0x558, 2),
268 		DEF_MOD("cru_sysclk",   R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
269 					0x564, 0),
270 		DEF_MOD("cru_vclk",     R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
271 					0x564, 1),
272 		DEF_MOD("cru_pclk",     R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
273 					0x564, 2),
274 		DEF_MOD("cru_aclk",     R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
275 					0x564, 3),
276 		DEF_MOD("dsi_pll_clk",	R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
277 					0x568, 0),
278 		DEF_MOD("dsi_sys_clk",	R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
279 					0x568, 1),
280 		DEF_MOD("dsi_aclk",	R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
281 					0x568, 2),
282 		DEF_MOD("dsi_pclk",	R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
283 					0x568, 3),
284 		DEF_MOD("dsi_vclk",	R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
285 					0x568, 4),
286 		DEF_MOD("dsi_lpclk",	R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
287 					0x568, 5),
288 		DEF_COUPLED("lcdc_a",	R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
289 					0x56c, 0),
290 		DEF_COUPLED("lcdc_p",	R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
291 					0x56c, 0),
292 		DEF_MOD("lcdc_clk_d",	R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
293 					0x56c, 1),
294 		DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
295 					0x570, 0),
296 		DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
297 					0x570, 1),
298 		DEF_MOD("ssi1_pclk",	R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
299 					0x570, 2),
300 		DEF_MOD("ssi1_sfr",	R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
301 					0x570, 3),
302 		DEF_MOD("ssi2_pclk",	R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
303 					0x570, 4),
304 		DEF_MOD("ssi2_sfr",	R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
305 					0x570, 5),
306 		DEF_MOD("ssi3_pclk",	R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
307 					0x570, 6),
308 		DEF_MOD("ssi3_sfr",	R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
309 					0x570, 7),
310 		DEF_MOD("usb0_host",	R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
311 					0x578, 0),
312 		DEF_MOD("usb1_host",	R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
313 					0x578, 1),
314 		DEF_MOD("usb0_func",	R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
315 					0x578, 2),
316 		DEF_MOD("usb_pclk",	R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
317 					0x578, 3),
318 		DEF_COUPLED("eth0_axi",	R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0,
319 					0x57c, 0),
320 		DEF_COUPLED("eth0_chi",	R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT,
321 					0x57c, 0),
322 		DEF_COUPLED("eth1_axi",	R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0,
323 					0x57c, 1),
324 		DEF_COUPLED("eth1_chi",	R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT,
325 					0x57c, 1),
326 		DEF_MOD("i2c0",		R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
327 					0x580, 0),
328 		DEF_MOD("i2c1",		R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
329 					0x580, 1),
330 		DEF_MOD("i2c2",		R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
331 					0x580, 2),
332 		DEF_MOD("i2c3",		R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
333 					0x580, 3),
334 		DEF_MOD("scif0",	R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
335 					0x584, 0),
336 		DEF_MOD("scif1",	R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
337 					0x584, 1),
338 		DEF_MOD("scif2",	R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
339 					0x584, 2),
340 		DEF_MOD("scif3",	R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
341 					0x584, 3),
342 		DEF_MOD("scif4",	R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
343 					0x584, 4),
344 		DEF_MOD("sci0",		R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
345 					0x588, 0),
346 		DEF_MOD("sci1",		R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0,
347 					0x588, 1),
348 		DEF_MOD("rspi0",	R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0,
349 					0x590, 0),
350 		DEF_MOD("rspi1",	R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0,
351 					0x590, 1),
352 		DEF_MOD("rspi2",	R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0,
353 					0x590, 2),
354 		DEF_MOD("canfd",	R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
355 					0x594, 0),
356 		DEF_MOD("gpio",		R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
357 					0x598, 0),
358 		DEF_MOD("adc_adclk",	R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
359 					0x5a8, 0),
360 		DEF_MOD("adc_pclk",	R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
361 					0x5a8, 1),
362 		DEF_MOD("tsu_pclk",	R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU,
363 					0x5ac, 0),
364 	},
365 #ifdef CONFIG_CLK_R9A07G054
366 	.drp = {
367 	},
368 #endif
369 };
370 
371 static const struct rzg2l_reset r9a07g044_resets[] = {
372 	DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
373 	DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
374 	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
375 	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
376 	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
377 	DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
378 	DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
379 	DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
380 	DEF_RST(R9A07G044_MTU_X_PRESET_MTU3, 0x838, 0),
381 	DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
382 	DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
383 	DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
384 	DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
385 	DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
386 	DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
387 	DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
388 	DEF_RST(R9A07G044_SPI_RST, 0x850, 0),
389 	DEF_RST(R9A07G044_SDHI0_IXRST, 0x854, 0),
390 	DEF_RST(R9A07G044_SDHI1_IXRST, 0x854, 1),
391 	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
392 	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
393 	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
394 	DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
395 	DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
396 	DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
397 	DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
398 	DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
399 	DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
400 	DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
401 	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
402 	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
403 	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
404 	DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
405 	DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
406 	DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
407 	DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
408 	DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
409 	DEF_RST(R9A07G044_ETH0_RST_HW_N, 0x87c, 0),
410 	DEF_RST(R9A07G044_ETH1_RST_HW_N, 0x87c, 1),
411 	DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
412 	DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
413 	DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
414 	DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
415 	DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
416 	DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
417 	DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
418 	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
419 	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
420 	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
421 	DEF_RST(R9A07G044_SCI1_RST, 0x888, 1),
422 	DEF_RST(R9A07G044_RSPI0_RST, 0x890, 0),
423 	DEF_RST(R9A07G044_RSPI1_RST, 0x890, 1),
424 	DEF_RST(R9A07G044_RSPI2_RST, 0x890, 2),
425 	DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
426 	DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
427 	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
428 	DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
429 	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
430 	DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
431 	DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
432 	DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),
433 };
434 
435 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
436 	MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
437 	MOD_CLK_BASE + R9A07G044_IA55_CLK,
438 	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
439 };
440 
441 static const unsigned int r9a07g044_no_pm_mod_clks[] = {
442 	MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
443 	MOD_CLK_BASE + R9A07G044_CRU_VCLK,
444 };
445 
446 #ifdef CONFIG_CLK_R9A07G044
447 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
448 	/* Core Clocks */
449 	.core_clks = core_clks.common,
450 	.num_core_clks = ARRAY_SIZE(core_clks.common),
451 	.last_dt_core_clk = LAST_DT_CORE_CLK,
452 	.num_total_core_clks = MOD_CLK_BASE,
453 
454 	/* Critical Module Clocks */
455 	.crit_mod_clks = r9a07g044_crit_mod_clks,
456 	.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
457 
458 	/* Module Clocks */
459 	.mod_clks = mod_clks.common,
460 	.num_mod_clks = ARRAY_SIZE(mod_clks.common),
461 	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
462 
463 	/* No PM Module Clocks */
464 	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
465 	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
466 
467 	/* Resets */
468 	.resets = r9a07g044_resets,
469 	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
470 
471 	.has_clk_mon_regs = true,
472 };
473 #endif
474 
475 #ifdef CONFIG_CLK_R9A07G054
476 const struct rzg2l_cpg_info r9a07g054_cpg_info = {
477 	/* Core Clocks */
478 	.core_clks = core_clks.common,
479 	.num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp),
480 	.last_dt_core_clk = LAST_DT_CORE_CLK,
481 	.num_total_core_clks = MOD_CLK_BASE,
482 
483 	/* Critical Module Clocks */
484 	.crit_mod_clks = r9a07g044_crit_mod_clks,
485 	.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
486 
487 	/* Module Clocks */
488 	.mod_clks = mod_clks.common,
489 	.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
490 	.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
491 
492 	/* No PM Module Clocks */
493 	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
494 	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
495 
496 	/* Resets */
497 	.resets = r9a07g044_resets,
498 	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
499 
500 	.has_clk_mon_regs = true,
501 };
502 #endif
503