1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
5 *
6 * Based on clock drivers for S3C64xx and Exynos4 SoCs.
7 *
8 * Common Clock Framework support for all S5PC110/S5PV210 SoCs.
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14
15 #include "clk.h"
16 #include "clk-pll.h"
17
18 #include <dt-bindings/clock/s5pv210.h>
19
20 /* S5PC110/S5PV210 clock controller register offsets */
21 #define APLL_LOCK 0x0000
22 #define MPLL_LOCK 0x0008
23 #define EPLL_LOCK 0x0010
24 #define VPLL_LOCK 0x0020
25 #define APLL_CON0 0x0100
26 #define APLL_CON1 0x0104
27 #define MPLL_CON 0x0108
28 #define EPLL_CON0 0x0110
29 #define EPLL_CON1 0x0114
30 #define VPLL_CON 0x0120
31 #define CLK_SRC0 0x0200
32 #define CLK_SRC1 0x0204
33 #define CLK_SRC2 0x0208
34 #define CLK_SRC3 0x020c
35 #define CLK_SRC4 0x0210
36 #define CLK_SRC5 0x0214
37 #define CLK_SRC6 0x0218
38 #define CLK_SRC_MASK0 0x0280
39 #define CLK_SRC_MASK1 0x0284
40 #define CLK_DIV0 0x0300
41 #define CLK_DIV1 0x0304
42 #define CLK_DIV2 0x0308
43 #define CLK_DIV3 0x030c
44 #define CLK_DIV4 0x0310
45 #define CLK_DIV5 0x0314
46 #define CLK_DIV6 0x0318
47 #define CLK_DIV7 0x031c
48 #define CLK_GATE_MAIN0 0x0400
49 #define CLK_GATE_MAIN1 0x0404
50 #define CLK_GATE_MAIN2 0x0408
51 #define CLK_GATE_PERI0 0x0420
52 #define CLK_GATE_PERI1 0x0424
53 #define CLK_GATE_SCLK0 0x0440
54 #define CLK_GATE_SCLK1 0x0444
55 #define CLK_GATE_IP0 0x0460
56 #define CLK_GATE_IP1 0x0464
57 #define CLK_GATE_IP2 0x0468
58 #define CLK_GATE_IP3 0x046c
59 #define CLK_GATE_IP4 0x0470
60 #define CLK_GATE_BLOCK 0x0480
61 #define CLK_GATE_IP5 0x0484
62 #define CLK_OUT 0x0500
63 #define MISC 0xe000
64 #define OM_STAT 0xe100
65
66 /* IDs of PLLs available on S5PV210/S5P6442 SoCs */
67 enum {
68 apll,
69 mpll,
70 epll,
71 vpll,
72 };
73
74 /* IDs of external clocks (used for legacy boards) */
75 enum {
76 xxti,
77 xusbxti,
78 };
79
80 static void __iomem *reg_base;
81
82 /* List of registers that need to be preserved across suspend/resume. */
83 static unsigned long s5pv210_clk_regs[] __initdata = {
84 CLK_SRC0,
85 CLK_SRC1,
86 CLK_SRC2,
87 CLK_SRC3,
88 CLK_SRC4,
89 CLK_SRC5,
90 CLK_SRC6,
91 CLK_SRC_MASK0,
92 CLK_SRC_MASK1,
93 CLK_DIV0,
94 CLK_DIV1,
95 CLK_DIV2,
96 CLK_DIV3,
97 CLK_DIV4,
98 CLK_DIV5,
99 CLK_DIV6,
100 CLK_DIV7,
101 CLK_GATE_MAIN0,
102 CLK_GATE_MAIN1,
103 CLK_GATE_MAIN2,
104 CLK_GATE_PERI0,
105 CLK_GATE_PERI1,
106 CLK_GATE_SCLK0,
107 CLK_GATE_SCLK1,
108 CLK_GATE_IP0,
109 CLK_GATE_IP1,
110 CLK_GATE_IP2,
111 CLK_GATE_IP3,
112 CLK_GATE_IP4,
113 CLK_GATE_IP5,
114 CLK_GATE_BLOCK,
115 APLL_LOCK,
116 MPLL_LOCK,
117 EPLL_LOCK,
118 VPLL_LOCK,
119 APLL_CON0,
120 APLL_CON1,
121 MPLL_CON,
122 EPLL_CON0,
123 EPLL_CON1,
124 VPLL_CON,
125 CLK_OUT,
126 };
127
128 /* Mux parent lists. */
129 static const char *const fin_pll_p[] __initconst = {
130 "xxti",
131 "xusbxti"
132 };
133
134 static const char *const mout_apll_p[] __initconst = {
135 "fin_pll",
136 "fout_apll"
137 };
138
139 static const char *const mout_mpll_p[] __initconst = {
140 "fin_pll",
141 "fout_mpll"
142 };
143
144 static const char *const mout_epll_p[] __initconst = {
145 "fin_pll",
146 "fout_epll"
147 };
148
149 static const char *const mout_vpllsrc_p[] __initconst = {
150 "fin_pll",
151 "sclk_hdmi27m"
152 };
153
154 static const char *const mout_vpll_p[] __initconst = {
155 "mout_vpllsrc",
156 "fout_vpll"
157 };
158
159 static const char *const mout_group1_p[] __initconst = {
160 "dout_a2m",
161 "mout_mpll",
162 "mout_epll",
163 "mout_vpll"
164 };
165
166 static const char *const mout_group2_p[] __initconst = {
167 "xxti",
168 "xusbxti",
169 "sclk_hdmi27m",
170 "sclk_usbphy0",
171 "sclk_usbphy1",
172 "sclk_hdmiphy",
173 "mout_mpll",
174 "mout_epll",
175 "mout_vpll",
176 };
177
178 static const char *const mout_audio0_p[] __initconst = {
179 "xxti",
180 "pcmcdclk0",
181 "sclk_hdmi27m",
182 "sclk_usbphy0",
183 "sclk_usbphy1",
184 "sclk_hdmiphy",
185 "mout_mpll",
186 "mout_epll",
187 "mout_vpll",
188 };
189
190 static const char *const mout_audio1_p[] __initconst = {
191 "i2scdclk1",
192 "pcmcdclk1",
193 "sclk_hdmi27m",
194 "sclk_usbphy0",
195 "sclk_usbphy1",
196 "sclk_hdmiphy",
197 "mout_mpll",
198 "mout_epll",
199 "mout_vpll",
200 };
201
202 static const char *const mout_audio2_p[] __initconst = {
203 "i2scdclk2",
204 "pcmcdclk2",
205 "sclk_hdmi27m",
206 "sclk_usbphy0",
207 "sclk_usbphy1",
208 "sclk_hdmiphy",
209 "mout_mpll",
210 "mout_epll",
211 "mout_vpll",
212 };
213
214 static const char *const mout_spdif_p[] __initconst = {
215 "dout_audio0",
216 "dout_audio1",
217 "dout_audio3",
218 };
219
220 static const char *const mout_group3_p[] __initconst = {
221 "mout_apll",
222 "mout_mpll"
223 };
224
225 static const char *const mout_group4_p[] __initconst = {
226 "mout_mpll",
227 "dout_a2m"
228 };
229
230 static const char *const mout_flash_p[] __initconst = {
231 "dout_hclkd",
232 "dout_hclkp"
233 };
234
235 static const char *const mout_dac_p[] __initconst = {
236 "mout_vpll",
237 "sclk_hdmiphy"
238 };
239
240 static const char *const mout_hdmi_p[] __initconst = {
241 "sclk_hdmiphy",
242 "dout_tblk"
243 };
244
245 static const char *const mout_mixer_p[] __initconst = {
246 "mout_dac",
247 "mout_hdmi"
248 };
249
250 static const char *const mout_vpll_6442_p[] __initconst = {
251 "fin_pll",
252 "fout_vpll"
253 };
254
255 static const char *const mout_mixer_6442_p[] __initconst = {
256 "mout_vpll",
257 "dout_mixer"
258 };
259
260 static const char *const mout_d0sync_6442_p[] __initconst = {
261 "mout_dsys",
262 "div_apll"
263 };
264
265 static const char *const mout_d1sync_6442_p[] __initconst = {
266 "mout_psys",
267 "div_apll"
268 };
269
270 static const char *const mout_group2_6442_p[] __initconst = {
271 "fin_pll",
272 "none",
273 "none",
274 "sclk_usbphy0",
275 "none",
276 "none",
277 "mout_mpll",
278 "mout_epll",
279 "mout_vpll",
280 };
281
282 static const char *const mout_audio0_6442_p[] __initconst = {
283 "fin_pll",
284 "pcmcdclk0",
285 "none",
286 "sclk_usbphy0",
287 "none",
288 "none",
289 "mout_mpll",
290 "mout_epll",
291 "mout_vpll",
292 };
293
294 static const char *const mout_audio1_6442_p[] __initconst = {
295 "i2scdclk1",
296 "pcmcdclk1",
297 "none",
298 "sclk_usbphy0",
299 "none",
300 "none",
301 "mout_mpll",
302 "mout_epll",
303 "mout_vpll",
304 "fin_pll",
305 };
306
307 static const char *const mout_clksel_p[] __initconst = {
308 "fout_apll_clkout",
309 "fout_mpll_clkout",
310 "fout_epll",
311 "fout_vpll",
312 "sclk_usbphy0",
313 "sclk_usbphy1",
314 "sclk_hdmiphy",
315 "rtc",
316 "rtc_tick",
317 "dout_hclkm",
318 "dout_pclkm",
319 "dout_hclkd",
320 "dout_pclkd",
321 "dout_hclkp",
322 "dout_pclkp",
323 "dout_apll_clkout",
324 "dout_hpm",
325 "xxti",
326 "xusbxti",
327 "div_dclk"
328 };
329
330 static const char *const mout_clksel_6442_p[] __initconst = {
331 "fout_apll_clkout",
332 "fout_mpll_clkout",
333 "fout_epll",
334 "fout_vpll",
335 "sclk_usbphy0",
336 "none",
337 "none",
338 "rtc",
339 "rtc_tick",
340 "none",
341 "none",
342 "dout_hclkd",
343 "dout_pclkd",
344 "dout_hclkp",
345 "dout_pclkp",
346 "dout_apll_clkout",
347 "none",
348 "fin_pll",
349 "none",
350 "div_dclk"
351 };
352
353 static const char *const mout_clkout_p[] __initconst = {
354 "dout_clkout",
355 "none",
356 "xxti",
357 "xusbxti"
358 };
359
360 /* Common fixed factor clocks. */
361 static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = {
362 FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0),
363 FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0),
364 FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0),
365 };
366
367 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
368 static const struct samsung_mux_clock early_mux_clks[] __initconst = {
369 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1,
370 CLK_MUX_READ_ONLY, 0),
371 };
372
373 /* Common clock muxes. */
374 static const struct samsung_mux_clock mux_clks[] __initconst = {
375 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
376 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
377 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
378 MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
379 MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
380 MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
381 MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
382
383 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
384 };
385
386 /* S5PV210-specific clock muxes. */
387 static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = {
388 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
389
390 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
391 MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4),
392 MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4),
393 MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4),
394 MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4),
395 MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1),
396 MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1),
397 MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1),
398
399 MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2),
400 MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2),
401 MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2),
402
403 MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4),
404 MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4),
405 MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4),
406
407 MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4),
408 MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4),
409 MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4),
410 MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4),
411 MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4),
412 MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4),
413 MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4),
414 MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4),
415
416 MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4),
417 MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4),
418 MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4),
419
420 MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2),
421 MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4),
422 MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1),
423 MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2),
424 MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4),
425 MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4),
426 MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4),
427
428 MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5),
429 };
430
431 /* S5P6442-specific clock muxes. */
432 static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = {
433 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1),
434
435 MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4),
436 MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4),
437 MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4),
438 MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1),
439
440 MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1),
441 MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1),
442
443 MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4),
444 MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4),
445 MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4),
446
447 MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4),
448 MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4),
449 MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4),
450 MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4),
451 MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4),
452 MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4),
453
454 MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4),
455 MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4),
456
457 MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4),
458 MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4),
459
460 MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5),
461 };
462
463 /* S5PV210-specific fixed rate clocks generated inside the SoC. */
464 static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = {
465 FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000),
466 FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000),
467 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000),
468 FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000),
469 };
470
471 /* S5P6442-specific fixed rate clocks generated inside the SoC. */
472 static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = {
473 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000),
474 };
475
476 /* Common clock dividers. */
477 static const struct samsung_div_clock div_clks[] __initconst = {
478 DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3),
479 DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3),
480 DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
481 DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3),
482
483 DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4),
484 DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4),
485 DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4),
486
487 DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4),
488 DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4),
489 DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4),
490
491 DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4),
492 DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4),
493 DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4),
494 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4),
495 DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4),
496 DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4),
497
498 DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4),
499 DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4),
500
501 DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3),
502 DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4),
503 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4),
504
505 DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4),
506 };
507
508 /* S5PV210-specific clock dividers. */
509 static const struct samsung_div_clock s5pv210_div_clks[] __initconst = {
510 DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4),
511 DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4),
512 DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3),
513 DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3),
514
515 DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4),
516 DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4),
517
518 DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4),
519 DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4),
520 DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4),
521
522 DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4),
523 DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4),
524
525 DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4),
526
527 DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4),
528 DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4),
529 DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3),
530 DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3),
531 DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4),
532
533 DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7),
534 DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7),
535 };
536
537 /* S5P6442-specific clock dividers. */
538 static const struct samsung_div_clock s5p6442_div_clks[] __initconst = {
539 DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4),
540 DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4),
541
542 DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4),
543 };
544
545 /* Common clock gates. */
546 static const struct samsung_gate_clock gate_clks[] __initconst = {
547 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
548 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
549 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
550 GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
551 GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
552 GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
553
554 GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
555 GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
556 GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
557 GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
558 GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0),
559 GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
560 GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0),
561
562 GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0),
563 GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0),
564 GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0),
565 GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0),
566 GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0),
567
568 GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0),
569 GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0),
570 GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0),
571 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
572 GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0),
573 GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0),
574 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0),
575 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0),
576 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0),
577 GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0),
578 GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
579 GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0),
580 GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0),
581 GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0),
582 GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0),
583 GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0),
584
585 GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0),
586 GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0),
587
588 GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25,
589 CLK_SET_RATE_PARENT, 0),
590 GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24,
591 CLK_SET_RATE_PARENT, 0),
592 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
593 CLK_SET_RATE_PARENT, 0),
594 GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
595 CLK_SET_RATE_PARENT, 0),
596 GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
597 CLK_SET_RATE_PARENT, 0),
598 GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
599 CLK_SET_RATE_PARENT, 0),
600 GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
601 CLK_SET_RATE_PARENT, 0),
602 GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10,
603 CLK_SET_RATE_PARENT, 0),
604 GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
605 CLK_SET_RATE_PARENT, 0),
606 GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8,
607 CLK_SET_RATE_PARENT, 0),
608 GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5,
609 CLK_SET_RATE_PARENT, 0),
610 GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4,
611 CLK_SET_RATE_PARENT, 0),
612 GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3,
613 CLK_SET_RATE_PARENT, 0),
614 GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1,
615 CLK_SET_RATE_PARENT, 0),
616
617 GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4,
618 CLK_SET_RATE_PARENT, 0),
619 GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3,
620 CLK_SET_RATE_PARENT, 0),
621 GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2,
622 CLK_SET_RATE_PARENT, 0),
623 };
624
625 /* S5PV210-specific clock gates. */
626 static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = {
627 GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0),
628 GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0),
629 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
630 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
631 GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0),
632 GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0),
633
634 GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0),
635 GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0),
636 GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0),
637 GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0),
638 GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
639
640 GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0),
641 GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0),
642 GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0),
643 GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0),
644 GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0),
645 GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0),
646 GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0),
647 GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0),
648 GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
649
650 GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0),
651 GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0),
652 GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0),
653 GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
654 CLK_GATE_IP3, 11, 0, 0),
655 GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0),
656 GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0),
657 GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0),
658 GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0),
659
660 GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0),
661 GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0),
662 GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0),
663 GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0),
664 GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0),
665 GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0),
666
667 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0),
668
669 GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27,
670 CLK_SET_RATE_PARENT, 0),
671 GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26,
672 CLK_SET_RATE_PARENT, 0),
673 GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17,
674 CLK_SET_RATE_PARENT, 0),
675 GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
676 CLK_SET_RATE_PARENT, 0),
677 GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11,
678 CLK_SET_RATE_PARENT, 0),
679 GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6,
680 CLK_SET_RATE_PARENT, 0),
681 GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
682 CLK_SET_RATE_PARENT, 0),
683 GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0,
684 CLK_SET_RATE_PARENT, 0),
685 };
686
687 /* S5P6442-specific clock gates. */
688 static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = {
689 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0),
690 GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0),
691 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0),
692 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
693 GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0),
694
695 GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0),
696 GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0),
697
698 GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0),
699
700 GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2,
701 CLK_SET_RATE_PARENT, 0),
702 };
703
704 /*
705 * Clock aliases for legacy clkdev look-up.
706 * NOTE: Needed only to support legacy board files.
707 */
708 static const struct samsung_clock_alias s5pv210_aliases[] __initconst = {
709 ALIAS(DOUT_APLL, NULL, "armclk"),
710 ALIAS(DOUT_HCLKM, NULL, "hclk_msys"),
711 ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"),
712 };
713
714 /* S5PV210-specific PLLs. */
715 static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = {
716 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
717 APLL_LOCK, APLL_CON0, NULL),
718 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
719 MPLL_LOCK, MPLL_CON, NULL),
720 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
721 EPLL_LOCK, EPLL_CON0, NULL),
722 [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
723 VPLL_LOCK, VPLL_CON, NULL),
724 };
725
726 /* S5P6442-specific PLLs. */
727 static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = {
728 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
729 APLL_LOCK, APLL_CON0, NULL),
730 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
731 MPLL_LOCK, MPLL_CON, NULL),
732 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
733 EPLL_LOCK, EPLL_CON0, NULL),
734 [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
735 VPLL_LOCK, VPLL_CON, NULL),
736 };
737
__s5pv210_clk_init(struct device_node * np,unsigned long xxti_f,unsigned long xusbxti_f,bool is_s5p6442)738 static void __init __s5pv210_clk_init(struct device_node *np,
739 unsigned long xxti_f,
740 unsigned long xusbxti_f,
741 bool is_s5p6442)
742 {
743 struct samsung_clk_provider *ctx;
744 struct clk_hw **hws;
745
746 ctx = samsung_clk_init(NULL, reg_base, NR_CLKS);
747 hws = ctx->clk_data.hws;
748
749 samsung_clk_register_mux(ctx, early_mux_clks,
750 ARRAY_SIZE(early_mux_clks));
751
752 if (is_s5p6442) {
753 samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
754 ARRAY_SIZE(s5p6442_frate_clks));
755 samsung_clk_register_pll(ctx, s5p6442_pll_clks,
756 ARRAY_SIZE(s5p6442_pll_clks));
757 samsung_clk_register_mux(ctx, s5p6442_mux_clks,
758 ARRAY_SIZE(s5p6442_mux_clks));
759 samsung_clk_register_div(ctx, s5p6442_div_clks,
760 ARRAY_SIZE(s5p6442_div_clks));
761 samsung_clk_register_gate(ctx, s5p6442_gate_clks,
762 ARRAY_SIZE(s5p6442_gate_clks));
763 } else {
764 samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
765 ARRAY_SIZE(s5pv210_frate_clks));
766 samsung_clk_register_pll(ctx, s5pv210_pll_clks,
767 ARRAY_SIZE(s5pv210_pll_clks));
768 samsung_clk_register_mux(ctx, s5pv210_mux_clks,
769 ARRAY_SIZE(s5pv210_mux_clks));
770 samsung_clk_register_div(ctx, s5pv210_div_clks,
771 ARRAY_SIZE(s5pv210_div_clks));
772 samsung_clk_register_gate(ctx, s5pv210_gate_clks,
773 ARRAY_SIZE(s5pv210_gate_clks));
774 }
775
776 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
777 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
778 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
779
780 samsung_clk_register_fixed_factor(ctx, ffactor_clks,
781 ARRAY_SIZE(ffactor_clks));
782
783 samsung_clk_register_alias(ctx, s5pv210_aliases,
784 ARRAY_SIZE(s5pv210_aliases));
785
786 samsung_clk_sleep_init(reg_base, s5pv210_clk_regs,
787 ARRAY_SIZE(s5pv210_clk_regs));
788
789 samsung_clk_of_add_provider(np, ctx);
790
791 pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n"
792 "\tmout_epll = %ld, mout_vpll = %ld\n",
793 is_s5p6442 ? "S5P6442" : "S5PV210",
794 clk_hw_get_rate(hws[MOUT_APLL]),
795 clk_hw_get_rate(hws[MOUT_MPLL]),
796 clk_hw_get_rate(hws[MOUT_EPLL]),
797 clk_hw_get_rate(hws[MOUT_VPLL]));
798 }
799
s5pv210_clk_dt_init(struct device_node * np)800 static void __init s5pv210_clk_dt_init(struct device_node *np)
801 {
802 reg_base = of_iomap(np, 0);
803 if (!reg_base)
804 panic("%s: failed to map registers\n", __func__);
805
806 __s5pv210_clk_init(np, 0, 0, false);
807 }
808 CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init);
809
s5p6442_clk_dt_init(struct device_node * np)810 static void __init s5p6442_clk_dt_init(struct device_node *np)
811 {
812 reg_base = of_iomap(np, 0);
813 if (!reg_base)
814 panic("%s: failed to map registers\n", __func__);
815
816 __s5pv210_clk_init(np, 0, 0, true);
817 }
818 CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init);
819