1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
4 *
5 * Common Clock Framework support for Exynos990.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <dt-bindings/clock/samsung,exynos990.h>
14
15 #include "clk.h"
16 #include "clk-exynos-arm64.h"
17 #include "clk-pll.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1)
21 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK + 1)
22 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PCLK + 1)
23 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_XIU_P_ACLK + 1)
24 #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
25
26 /* ---- CMU_TOP ------------------------------------------------------------- */
27
28 /* Register Offset definitions for CMU_TOP (0x1a330000) */
29 #define PLL_LOCKTIME_PLL_G3D 0x0000
30 #define PLL_LOCKTIME_PLL_MMC 0x0004
31 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
32 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
33 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
34 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
35 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
36 #define PLL_CON0_PLL_G3D 0x0100
37 #define PLL_CON3_PLL_G3D 0x010c
38 #define PLL_CON0_PLL_MMC 0x0140
39 #define PLL_CON3_PLL_MMC 0x014c
40 #define PLL_CON0_PLL_SHARED0 0x0180
41 #define PLL_CON3_PLL_SHARED0 0x018c
42 #define PLL_CON0_PLL_SHARED1 0x01c0
43 #define PLL_CON3_PLL_SHARED1 0x01cc
44 #define PLL_CON0_PLL_SHARED2 0x0200
45 #define PLL_CON3_PLL_SHARED2 0x020c
46 #define PLL_CON0_PLL_SHARED3 0x0240
47 #define PLL_CON3_PLL_SHARED3 0x024c
48 #define PLL_CON0_PLL_SHARED4 0x0280
49 #define PLL_CON3_PLL_SHARED4 0x028c
50 #define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000
51 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
52 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
53 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
54 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1010
55 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS 0x1014
56 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1018
57 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x101c
58 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1020
59 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1024
60 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1028
61 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x102c
62 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
63 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1034
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS 0x1038
65 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x103c
66 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1040
67 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP 0x1044
68 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
69 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
70 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU 0x1050
71 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUS 0x1054
72 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM 0x1058
73 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x105c
74 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1060
75 #define CLK_CON_MUX_MUX_CLKCMU_DPU_ALT 0x1064
76 #define CLK_CON_MUX_MUX_CLKCMU_DSP_BUS 0x1068
77 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x106c
78 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1070
79 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1074
80 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1078
81 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x107c
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1080
83 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG 0x1084
84 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1088
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x108c
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x1090
87 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD 0x1094
88 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD 0x1098
89 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x109c
90 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a0
91 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10a4
92 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10a8
93 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS 0x10ac
94 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC 0x10b0
95 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU 0x10b4
96 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0 0x10b8
97 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD 0x10bc
98 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c0
99 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c4
100 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10c8
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10cc
102 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10d0
103 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10d4
104 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d8
105 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10dc
106 #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
107 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
108 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
109 #define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0
110 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
111 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
112 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
113 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
114 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x180c
115 #define CLK_CON_DIV_CLKCMU_BUS1_SSS 0x1810
116 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1814
117 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1818
118 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x181c
119 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1820
120 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1824
121 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1828
122 #define CLK_CON_DIV_CLKCMU_CMU_BOOST 0x182c
123 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
124 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS 0x1834
125 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
126 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
127 #define CLK_CON_DIV_CLKCMU_CPUCL2_BUSP 0x1840
128 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1844
129 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1848
130 #define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU 0x184c
131 #define CLK_CON_DIV_CLKCMU_DNC_BUS 0x1850
132 #define CLK_CON_DIV_CLKCMU_DNC_BUSM 0x1854
133 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x1858
134 #define CLK_CON_DIV_CLKCMU_DSP_BUS 0x185c
135 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1860
136 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1864
137 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
138 #define CLK_CON_DIV_CLKCMU_HPM 0x186c
139 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1870
140 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1874
141 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1878
142 #define CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG 0x187c
143 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1880
144 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x1884
145 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1888
146 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD 0x188c
147 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD 0x1890
148 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1894
149 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x1898
150 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x189c
151 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18a0
152 #define CLK_CON_DIV_CLKCMU_MCSC_BUS 0x18a4
153 #define CLK_CON_DIV_CLKCMU_MCSC_GDC 0x18a8
154 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x18ac
155 #define CLK_CON_DIV_CLKCMU_MFC0_MFC0 0x18b0
156 #define CLK_CON_DIV_CLKCMU_MFC0_WFD 0x18b4
157 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18b8
158 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x18bc
159 #define CLK_CON_DIV_CLKCMU_OTP 0x18c0
160 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18c4
161 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c8
162 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18cc
163 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18d0
164 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18d4
165 #define CLK_CON_DIV_CLKCMU_SSP_BUS 0x18d8
166 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18dc
167 #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
168 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
169 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
170 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0
171 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
172 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
173 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
174 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1900
175 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1904
176 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1908
177 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x190c
178 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x1910
179 #define CLK_CON_DIV_PLL_SHARED4_DIV3 0x1914
180 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x1918
181 #define CLK_CON_GAT_CLKCMU_G3D_BUS 0x2000
182 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2004
183 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
184 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x200c
185 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2010
186 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x2014
187 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS 0x2018
188 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x201c
189 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2020
190 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2024
191 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2028
192 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x202c
193 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2030
194 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2034
195 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x2038
196 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x203c
197 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2040
198 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP 0x2044
199 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2048
200 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x204c
201 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU 0x2050
202 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUS 0x2054
203 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM 0x2058
204 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x205c
205 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x2060
206 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2064
207 #define CLK_CON_GAT_GATE_CLKCMU_DSP_BUS 0x2068
208 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x206c
209 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2070
210 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2074
211 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x2078
212 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x207c
213 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x2080
214 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x2084
215 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG 0x2088
216 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x208c
217 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD 0x2090
218 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x2094
219 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD 0x2098
220 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD 0x209c
221 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20a0
222 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20a4
223 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20a8
224 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20ac
225 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS 0x20b0
226 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC 0x20b4
227 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0 0x20bc
228 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD 0x20c0
229 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c4
230 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c8
231 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20cc
232 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20d0
233 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d4
234 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d8
235 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20dc
236 #define CLK_CON_GAT_GATE_CLKCMU_SSP_BUS 0x20e0
237 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x20e4
238 #define CLK_CON_GAT_GATE_CLKCMU_VRA_BUS 0x20e8
239
240 static const unsigned long top_clk_regs[] __initconst = {
241 PLL_LOCKTIME_PLL_G3D,
242 PLL_LOCKTIME_PLL_MMC,
243 PLL_LOCKTIME_PLL_SHARED0,
244 PLL_LOCKTIME_PLL_SHARED1,
245 PLL_LOCKTIME_PLL_SHARED2,
246 PLL_LOCKTIME_PLL_SHARED3,
247 PLL_LOCKTIME_PLL_SHARED4,
248 PLL_CON0_PLL_G3D,
249 PLL_CON3_PLL_G3D,
250 PLL_CON0_PLL_MMC,
251 PLL_CON3_PLL_MMC,
252 PLL_CON0_PLL_SHARED0,
253 PLL_CON3_PLL_SHARED0,
254 PLL_CON0_PLL_SHARED1,
255 PLL_CON3_PLL_SHARED1,
256 PLL_CON0_PLL_SHARED2,
257 PLL_CON3_PLL_SHARED2,
258 PLL_CON0_PLL_SHARED3,
259 PLL_CON3_PLL_SHARED3,
260 PLL_CON0_PLL_SHARED4,
261 PLL_CON3_PLL_SHARED4,
262 CLK_CON_MUX_CLKCMU_DPU_BUS,
263 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
264 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
265 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
266 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
267 CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS,
268 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
269 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
270 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
271 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
272 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
273 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
274 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
275 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
276 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
277 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
278 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
279 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP,
280 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
281 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
282 CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
283 CLK_CON_MUX_MUX_CLKCMU_DNC_BUS,
284 CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM,
285 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
286 CLK_CON_MUX_MUX_CLKCMU_DPU,
287 CLK_CON_MUX_MUX_CLKCMU_DPU_ALT,
288 CLK_CON_MUX_MUX_CLKCMU_DSP_BUS,
289 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
290 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
291 CLK_CON_MUX_MUX_CLKCMU_HPM,
292 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
293 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
294 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
295 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG,
296 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
297 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
298 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
299 CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD,
300 CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
301 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
302 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
303 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
304 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
305 CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS,
306 CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC,
307 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
308 CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
309 CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
310 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
311 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
312 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
313 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
314 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
315 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
316 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
317 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
318 CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
319 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
320 CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
321 CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
322 CLK_CON_MUX_MUX_CMU_CMUREF,
323 CLK_CON_DIV_CLKCMU_APM_BUS,
324 CLK_CON_DIV_CLKCMU_AUD_CPU,
325 CLK_CON_DIV_CLKCMU_BUS0_BUS,
326 CLK_CON_DIV_CLKCMU_BUS1_BUS,
327 CLK_CON_DIV_CLKCMU_BUS1_SSS,
328 CLK_CON_DIV_CLKCMU_CIS_CLK0,
329 CLK_CON_DIV_CLKCMU_CIS_CLK1,
330 CLK_CON_DIV_CLKCMU_CIS_CLK2,
331 CLK_CON_DIV_CLKCMU_CIS_CLK3,
332 CLK_CON_DIV_CLKCMU_CIS_CLK4,
333 CLK_CON_DIV_CLKCMU_CIS_CLK5,
334 CLK_CON_DIV_CLKCMU_CMU_BOOST,
335 CLK_CON_DIV_CLKCMU_CORE_BUS,
336 CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
337 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
338 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
339 CLK_CON_DIV_CLKCMU_CPUCL2_BUSP,
340 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
341 CLK_CON_DIV_CLKCMU_CSIS_BUS,
342 CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
343 CLK_CON_DIV_CLKCMU_DNC_BUS,
344 CLK_CON_DIV_CLKCMU_DNC_BUSM,
345 CLK_CON_DIV_CLKCMU_DNS_BUS,
346 CLK_CON_DIV_CLKCMU_DSP_BUS,
347 CLK_CON_DIV_CLKCMU_G2D_G2D,
348 CLK_CON_DIV_CLKCMU_G2D_MSCL,
349 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
350 CLK_CON_DIV_CLKCMU_HPM,
351 CLK_CON_DIV_CLKCMU_HSI0_BUS,
352 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
353 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
354 CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
355 CLK_CON_DIV_CLKCMU_HSI1_BUS,
356 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
357 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
358 CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
359 CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
360 CLK_CON_DIV_CLKCMU_HSI2_BUS,
361 CLK_CON_DIV_CLKCMU_HSI2_PCIE,
362 CLK_CON_DIV_CLKCMU_IPP_BUS,
363 CLK_CON_DIV_CLKCMU_ITP_BUS,
364 CLK_CON_DIV_CLKCMU_MCSC_BUS,
365 CLK_CON_DIV_CLKCMU_MCSC_GDC,
366 CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
367 CLK_CON_DIV_CLKCMU_MFC0_MFC0,
368 CLK_CON_DIV_CLKCMU_MFC0_WFD,
369 CLK_CON_DIV_CLKCMU_MIF_BUSP,
370 CLK_CON_DIV_CLKCMU_NPU_BUS,
371 CLK_CON_DIV_CLKCMU_OTP,
372 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
373 CLK_CON_DIV_CLKCMU_PERIC0_IP,
374 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
375 CLK_CON_DIV_CLKCMU_PERIC1_IP,
376 CLK_CON_DIV_CLKCMU_PERIS_BUS,
377 CLK_CON_DIV_CLKCMU_SSP_BUS,
378 CLK_CON_DIV_CLKCMU_TNR_BUS,
379 CLK_CON_DIV_CLKCMU_VRA_BUS,
380 CLK_CON_DIV_DIV_CLKCMU_DPU,
381 CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
382 CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
383 CLK_CON_DIV_PLL_SHARED0_DIV2,
384 CLK_CON_DIV_PLL_SHARED0_DIV3,
385 CLK_CON_DIV_PLL_SHARED0_DIV4,
386 CLK_CON_DIV_PLL_SHARED1_DIV2,
387 CLK_CON_DIV_PLL_SHARED1_DIV3,
388 CLK_CON_DIV_PLL_SHARED1_DIV4,
389 CLK_CON_DIV_PLL_SHARED2_DIV2,
390 CLK_CON_DIV_PLL_SHARED4_DIV2,
391 CLK_CON_DIV_PLL_SHARED4_DIV3,
392 CLK_CON_DIV_PLL_SHARED4_DIV4,
393 CLK_CON_GAT_CLKCMU_G3D_BUS,
394 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
395 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
396 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
397 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
398 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
399 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS,
400 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
401 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
402 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
403 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
404 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
405 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
406 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
407 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
408 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
409 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
410 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP,
411 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
412 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
413 CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
414 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS,
415 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM,
416 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
417 CLK_CON_GAT_GATE_CLKCMU_DPU,
418 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
419 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS,
420 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
421 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
422 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
423 CLK_CON_GAT_GATE_CLKCMU_HPM,
424 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
425 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
426 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
427 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG,
428 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
429 CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
430 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
431 CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD,
432 CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
433 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
434 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
435 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
436 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
437 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS,
438 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC,
439 CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
440 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
441 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
442 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
443 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
444 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
445 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
446 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
447 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
448 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS,
449 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
450 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS,
451 };
452
453 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
454 PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
455 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
456 PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
457 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
458 PLL(pll_0718x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
459 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
460 PLL(pll_0718x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
461 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
462 PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
463 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
464 PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
465 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
466 PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
467 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
468 };
469
470 /* Parent clock list for CMU_TOP muxes */
471 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
472 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
473 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
474 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
475 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
476 PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
477 PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
478 PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
479 "dout_cmu_dpu_alt" };
480 PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
481 "dout_cmu_shared2_div2" };
482 PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
483 "fout_shared2_pll",
484 "dout_cmu_shared4_div2",
485 "dout_cmu_shared0_div4" };
486 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4",
487 "dout_cmu_shared1_div4",
488 "dout_cmu_shared2_div2",
489 "oscclk" };
490 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div4",
491 "dout_cmu_shared1_div4",
492 "dout_cmu_shared2_div2",
493 "oscclk" };
494 PNAME(mout_cmu_bus1_sss_p) = { "dout_cmu_shared0_div4",
495 "dout_cmu_shared1_div4",
496 "dout_cmu_shared2_div2",
497 "oscclk" };
498 PNAME(mout_cmu_cis_clk0_p) = { "oscclk",
499 "dout_cmu_shared2_div2" };
500 PNAME(mout_cmu_cis_clk1_p) = { "oscclk",
501 "dout_cmu_shared2_div2" };
502 PNAME(mout_cmu_cis_clk2_p) = { "oscclk",
503 "dout_cmu_shared2_div2" };
504 PNAME(mout_cmu_cis_clk3_p) = { "oscclk",
505 "dout_cmu_shared2_div2" };
506 PNAME(mout_cmu_cis_clk4_p) = { "oscclk",
507 "dout_cmu_shared2_div2" };
508 PNAME(mout_cmu_cis_clk5_p) = { "oscclk",
509 "dout_cmu_shared2_div2" };
510 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4",
511 "dout_cmu_shared1_div4",
512 "dout_cmu_shared2_div2",
513 "oscclk" };
514 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2",
515 "dout_cmu_shared1_div2",
516 "fout_shared2_pll",
517 "dout_cmu_shared0_div3",
518 "dout_cmu_shared1_div3",
519 "dout_cmu_shared0_div4",
520 "fout_shared3_pll", "oscclk" };
521 PNAME(mout_cmu_cpucl0_dbg_bus_p) = { "fout_shared2_pll",
522 "dout_cmu_shared0_div3",
523 "dout_cmu_shared0_div4",
524 "oscclk" };
525 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
526 "dout_cmu_shared0_div2",
527 "fout_shared2_pll",
528 "dout_cmu_shared0_div4" };
529 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
530 "dout_cmu_shared0_div2",
531 "fout_shared2_pll",
532 "dout_cmu_shared0_div4" };
533 PNAME(mout_cmu_cpucl2_busp_p) = { "dout_cmu_shared0_div4",
534 "dout_cmu_shared2_div2" };
535 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared4_pll",
536 "dout_cmu_shared0_div2",
537 "fout_shared2_pll",
538 "dout_cmu_shared0_div4" };
539 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3",
540 "dout_cmu_shared4_div2",
541 "dout_cmu_shared0_div4",
542 "dout_cmu_shared4_div3" };
543 PNAME(mout_cmu_csis_ois_mcu_p) = { "dout_cmu_shared0_div4",
544 "dout_cmu_shared2_div2" };
545 PNAME(mout_cmu_dnc_bus_p) = { "dout_cmu_shared1_div2",
546 "fout_shared2_pll",
547 "dout_cmu_shared4_div2",
548 "dout_cmu_shared0_div4" };
549 PNAME(mout_cmu_dnc_busm_p) = { "dout_cmu_shared0_div4",
550 "dout_cmu_shared1_div4",
551 "dout_cmu_shared2_div2",
552 "dout_cmu_shared4_div4" };
553 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3",
554 "dout_cmu_shared4_div2",
555 "dout_cmu_shared0_div4",
556 "dout_cmu_shared1_div4",
557 "dout_cmu_shared4_div3",
558 "dout_cmu_shared2_div2",
559 "oscclk", "oscclk" };
560 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3",
561 "dout_cmu_shared0_div4" };
562 PNAME(mout_cmu_dpu_alt_p) = { "dout_cmu_shared4_div2",
563 "dout_cmu_shared4_div3",
564 "dout_cmu_shared2_div2",
565 "oscclk" };
566 PNAME(mout_cmu_dsp_bus_p) = { "dout_cmu_shared0_div2",
567 "dout_cmu_shared1_div2",
568 "fout_shared2_pll",
569 "dout_cmu_shared4_div2",
570 "fout_shared3_pll", "oscclk",
571 "oscclk", "oscclk" };
572 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3",
573 "dout_cmu_shared4_div2",
574 "dout_cmu_shared0_div4",
575 "dout_cmu_shared2_div2" };
576 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4",
577 "dout_cmu_shared2_div2",
578 "dout_cmu_shared4_div4",
579 "oscclk" };
580 PNAME(mout_cmu_hpm_p) = { "oscclk",
581 "dout_cmu_shared0_div4",
582 "dout_cmu_shared2_div2",
583 "oscclk" };
584 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4",
585 "dout_cmu_shared2_div2" };
586 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
587 "dout_cmu_shared2_div2",
588 "oscclk" };
589 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared0_div4",
590 "dout_cmu_shared2_div2",
591 "oscclk" };
592 PNAME(mout_cmu_hsi0_usbdp_debug_p) = { "oscclk", "fout_shared2_pll" };
593 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
594 "dout_cmu_shared0_div4",
595 "dout_cmu_shared1_div4",
596 "dout_cmu_shared4_div3",
597 "dout_cmu_shared2_div2",
598 "fout_mmc_pll", "oscclk", "oscclk" };
599 PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
600 "fout_mmc_pll",
601 "dout_cmu_shared0_div4" };
602 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
603 PNAME(mout_cmu_hsi1_ufs_card_p) = { "oscclk", "dout_cmu_shared0_div4",
604 "dout_cmu_shared2_div2",
605 "oscclk" };
606 PNAME(mout_cmu_hsi1_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
607 "dout_cmu_shared2_div2",
608 "oscclk" };
609 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div3",
610 "dout_cmu_shared2_div2" };
611 PNAME(mout_cmu_hsi2_pcie_p) = { "oscclk", "fout_shared2_pll" };
612 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3",
613 "dout_cmu_shared4_div2",
614 "dout_cmu_shared0_div4",
615 "dout_cmu_shared1_div4",
616 "dout_cmu_shared4_div3",
617 "oscclk", "oscclk", "oscclk" };
618 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3",
619 "dout_cmu_shared4_div2",
620 "dout_cmu_shared0_div4",
621 "dout_cmu_shared1_div4",
622 "dout_cmu_shared4_div3",
623 "dout_cmu_shared2_div2",
624 "oscclk", "oscclk" };
625 PNAME(mout_cmu_mcsc_bus_p) = { "dout_cmu_shared0_div3",
626 "dout_cmu_shared4_div2",
627 "dout_cmu_shared0_div4",
628 "dout_cmu_shared1_div4",
629 "dout_cmu_shared4_div3",
630 "dout_cmu_shared2_div2",
631 "oscclk", "oscclk" };
632 PNAME(mout_cmu_mcsc_gdc_p) = { "dout_cmu_shared0_div3",
633 "dout_cmu_shared4_div2",
634 "dout_cmu_shared0_div4",
635 "dout_cmu_shared1_div4",
636 "dout_cmu_shared4_div3",
637 "dout_cmu_shared2_div2",
638 "oscclk", "oscclk" };
639 PNAME(mout_cmu_cmu_boost_cpu_p) = { "dout_cmu_shared0_div4",
640 "dout_cmu_shared1_div4",
641 "dout_cmu_shared2_div2",
642 "oscclk" };
643 PNAME(mout_cmu_mfc0_mfc0_p) = { "dout_cmu_shared4_div2",
644 "dout_cmu_shared0_div4",
645 "dout_cmu_shared4_div3",
646 "dout_cmu_shared2_div2" };
647 PNAME(mout_cmu_mfc0_wfd_p) = { "dout_cmu_shared4_div2",
648 "dout_cmu_shared0_div4",
649 "dout_cmu_shared4_div3",
650 "dout_cmu_shared2_div2" };
651 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4",
652 "dout_cmu_shared1_div4",
653 "dout_cmu_shared2_div2",
654 "oscclk" };
655 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll",
656 "fout_shared1_pll",
657 "dout_cmu_shared0_div2",
658 "dout_cmu_shared1_div2",
659 "fout_shared2_pll",
660 "dout_cmu_shared0_div4",
661 "dout_cmu_shared2_div2",
662 "oscclk" };
663 PNAME(mout_cmu_npu_bus_p) = { "dout_cmu_shared0_div2",
664 "dout_cmu_shared1_div2",
665 "fout_shared2_pll",
666 "dout_cmu_shared4_div2",
667 "fout_shared3_pll", "oscclk",
668 "oscclk", "oscclk" };
669 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
670 "dout_cmu_shared2_div2" };
671 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4",
672 "dout_cmu_shared2_div2" };
673 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
674 "dout_cmu_shared2_div2" };
675 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4",
676 "dout_cmu_shared2_div2" };
677 PNAME(mout_cmu_peris_bus_p) = { "dout_cmu_shared0_div4",
678 "dout_cmu_shared2_div2" };
679 PNAME(mout_cmu_ssp_bus_p) = { "dout_cmu_shared4_div2",
680 "dout_cmu_shared0_div4",
681 "dout_cmu_shared4_div3",
682 "dout_cmu_shared2_div2" };
683 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3",
684 "dout_cmu_shared4_div2",
685 "dout_cmu_shared0_div4",
686 "dout_cmu_shared1_div4",
687 "dout_cmu_shared4_div3",
688 "dout_cmu_shared2_div2",
689 "oscclk", "oscclk" };
690 PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
691 "dout_cmu_shared4_div2",
692 "dout_cmu_shared0_div4",
693 "dout_cmu_shared4_div3" };
694 PNAME(mout_cmu_cmuref_p) = { "oscclk",
695 "dout_cmu_clk_cmuref" };
696 PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4",
697 "dout_cmu_shared1_div4",
698 "dout_cmu_shared2_div2",
699 "oscclk" };
700
701 /*
702 * Register name to clock name mangling strategy used in this file
703 *
704 * Replace PLL_CON{0,3}_PLL with CLK_MOUT_PLL and mout_pll
705 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
706 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
707 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
708 * Replace CLK_CON_DIV_PLL_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
709 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
710 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
711 *
712 * For gates remove _UID _BLK _IPCLKPORT, _I and _RSTNSYNC
713 */
714
715 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
716 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
717 PLL_CON0_PLL_SHARED0, 4, 1),
718 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
719 PLL_CON0_PLL_SHARED1, 4, 1),
720 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
721 PLL_CON0_PLL_SHARED2, 4, 1),
722 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
723 PLL_CON0_PLL_SHARED3, 4, 1),
724 MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
725 PLL_CON0_PLL_SHARED4, 4, 1),
726 MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
727 PLL_CON0_PLL_MMC, 4, 1),
728 MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
729 PLL_CON0_PLL_G3D, 4, 1),
730 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
731 mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
732 MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
733 mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
734 MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
735 mout_cmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 2),
736 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus",
737 mout_cmu_bus0_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
738 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus",
739 mout_cmu_bus1_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
740 MUX(CLK_MOUT_CMU_BUS1_SSS, "mout_cmu_bus1_sss",
741 mout_cmu_bus1_sss_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS, 0, 2),
742 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0",
743 mout_cmu_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
744 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1",
745 mout_cmu_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
746 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2",
747 mout_cmu_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
748 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3",
749 mout_cmu_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
750 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4",
751 mout_cmu_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1),
752 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5",
753 mout_cmu_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1),
754 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost",
755 mout_cmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
756 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus",
757 mout_cmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
758 MUX(CLK_MOUT_CMU_CPUCL0_DBG_BUS, "mout_cmu_cpucl0_dbg_bus",
759 mout_cmu_cpucl0_dbg_bus_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
760 0, 2),
761 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
762 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
763 0, 2),
764 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
765 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
766 0, 2),
767 MUX(CLK_MOUT_CMU_CPUCL2_BUSP, "mout_cmu_cpucl2_busp",
768 mout_cmu_cpucl2_busp_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP,
769 0, 1),
770 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
771 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
772 0, 2),
773 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus",
774 mout_cmu_csis_bus_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
775 MUX(CLK_MOUT_CMU_CSIS_OIS_MCU, "mout_cmu_csis_ois_mcu",
776 mout_cmu_csis_ois_mcu_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
777 0, 1),
778 MUX(CLK_MOUT_CMU_DNC_BUS, "mout_cmu_dnc_bus",
779 mout_cmu_dnc_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUS, 0, 2),
780 MUX(CLK_MOUT_CMU_DNC_BUSM, "mout_cmu_dnc_busm",
781 mout_cmu_dnc_busm_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM, 0, 2),
782 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus",
783 mout_cmu_dns_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
784 MUX(CLK_MOUT_CMU_DPU, "mout_cmu_dpu",
785 mout_cmu_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 1),
786 MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt",
787 mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
788 MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus",
789 mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3),
790 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d",
791 mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
792 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl",
793 mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
794 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm",
795 mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
796 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus",
797 mout_cmu_hsi0_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 1),
798 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",
799 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
800 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",
801 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
802 0, 2),
803 MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug",
804 mout_cmu_hsi0_usbdp_debug_p,
805 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1),
806 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus",
807 mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
808 MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card",
809 mout_cmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
810 0, 2),
811 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie",
812 mout_cmu_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
813 MUX(CLK_MOUT_CMU_HSI1_UFS_CARD, "mout_cmu_hsi1_ufs_card",
814 mout_cmu_hsi1_ufs_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD,
815 0, 2),
816 MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd",
817 mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
818 0, 2),
819 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus",
820 mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
821 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie",
822 mout_cmu_hsi2_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
823 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus",
824 mout_cmu_ipp_bus_p, CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
825 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus",
826 mout_cmu_itp_bus_p, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
827 MUX(CLK_MOUT_CMU_MCSC_BUS, "mout_cmu_mcsc_bus",
828 mout_cmu_mcsc_bus_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, 0, 3),
829 MUX(CLK_MOUT_CMU_MCSC_GDC, "mout_cmu_mcsc_gdc",
830 mout_cmu_mcsc_gdc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, 0, 3),
831 MUX(CLK_MOUT_CMU_CMU_BOOST_CPU, "mout_cmu_cmu_boost_cpu",
832 mout_cmu_cmu_boost_cpu_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
833 0, 2),
834 MUX(CLK_MOUT_CMU_MFC0_MFC0, "mout_cmu_mfc0_mfc0",
835 mout_cmu_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 2),
836 MUX(CLK_MOUT_CMU_MFC0_WFD, "mout_cmu_mfc0_wfd",
837 mout_cmu_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 2),
838 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp",
839 mout_cmu_mif_busp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
840 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
841 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
842 MUX(CLK_MOUT_CMU_NPU_BUS, "mout_cmu_npu_bus",
843 mout_cmu_npu_bus_p, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
844 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
845 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
846 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip",
847 mout_cmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
848 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
849 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
850 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip",
851 mout_cmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
852 MUX(CLK_MOUT_CMU_PERIS_BUS, "mout_cmu_peris_bus",
853 mout_cmu_peris_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
854 MUX(CLK_MOUT_CMU_SSP_BUS, "mout_cmu_ssp_bus",
855 mout_cmu_ssp_bus_p, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, 0, 2),
856 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus",
857 mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
858 MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
859 mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
860 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
861 mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
862 MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
863 mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
864 };
865
866 static const struct samsung_div_clock top_div_clks[] __initconst = {
867 /* SHARED0 region*/
868 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
869 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
870 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
871 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
872 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
873 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
874
875 /* SHARED1 region*/
876 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
877 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
878 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
879 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
880 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
881 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
882
883 /* SHARED2 region */
884 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
885 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
886
887 /* SHARED4 region*/
888 DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
889 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
890 DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
891 CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
892 DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
893 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
894
895 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
896 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
897 DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
898 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
899 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
900 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
901 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
902 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
903 DIV(CLK_DOUT_CMU_BUS1_SSS, "dout_cmu_bus1_sss", "gout_cmu_bus1_sss",
904 CLK_CON_DIV_CLKCMU_BUS1_SSS, 0, 4),
905 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
906 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
907 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
908 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
909 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
910 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
911 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
912 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
913 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",
914 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
915 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",
916 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
917 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "mout_cmu_cmu_boost",
918 CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
919 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
920 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
921 DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus",
922 "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
923 0, 4),
924 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
925 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
926 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
927 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
928 DIV(CLK_DOUT_CMU_CPUCL2_BUSP, "dout_cmu_cpucl2_busp",
929 "gout_cmu_cpucl2_busp", CLK_CON_DIV_CLKCMU_CPUCL2_BUSP, 0, 4),
930 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
931 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
932 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
933 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
934 DIV(CLK_DOUT_CMU_CSIS_OIS_MCU, "dout_cmu_csis_ois_mcu",
935 "gout_cmu_csis_ois_mcu", CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, 0, 4),
936 DIV(CLK_DOUT_CMU_DNC_BUS, "dout_cmu_dnc_bus", "gout_cmu_dnc_bus",
937 CLK_CON_DIV_CLKCMU_DNC_BUS, 0, 4),
938 DIV(CLK_DOUT_CMU_DNC_BUSM, "dout_cmu_dnc_busm", "gout_cmu_dnc_busm",
939 CLK_CON_DIV_CLKCMU_DNC_BUSM, 0, 4),
940 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
941 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
942 DIV(CLK_DOUT_CMU_DSP_BUS, "dout_cmu_dsp_bus", "gout_cmu_dsp_bus",
943 CLK_CON_DIV_CLKCMU_DSP_BUS, 0, 4),
944 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
945 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
946 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
947 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
948 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
949 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
950 DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
951 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
952 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
953 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
954 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
955 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
956 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
957 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
958 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
959 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
960 DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card",
961 "gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
962 0, 9),
963 DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card",
964 "gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
965 0, 3),
966 DIV(CLK_DOUT_CMU_HSI1_UFS_EMBD, "dout_cmu_hsi1_ufs_embd",
967 "gout_cmu_hsi1_ufs_embd", CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
968 0, 3),
969 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
970 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
971 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
972 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
973 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
974 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
975 DIV(CLK_DOUT_CMU_MCSC_BUS, "dout_cmu_mcsc_bus", "gout_cmu_mcsc_bus",
976 CLK_CON_DIV_CLKCMU_MCSC_BUS, 0, 4),
977 DIV(CLK_DOUT_CMU_MCSC_GDC, "dout_cmu_mcsc_gdc", "gout_cmu_mcsc_gdc",
978 CLK_CON_DIV_CLKCMU_MCSC_GDC, 0, 4),
979 DIV(CLK_DOUT_CMU_CMU_BOOST_CPU, "dout_cmu_cmu_boost_cpu",
980 "mout_cmu_cmu_boost_cpu", CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
981 0, 2),
982 DIV(CLK_DOUT_CMU_MFC0_MFC0, "dout_cmu_mfc0_mfc0", "gout_cmu_mfc0_mfc0",
983 CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0, 4),
984 DIV(CLK_DOUT_CMU_MFC0_WFD, "dout_cmu_mfc0_wfd", "gout_cmu_mfc0_wfd",
985 CLK_CON_DIV_CLKCMU_MFC0_WFD, 0, 4),
986 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
987 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
988 DIV(CLK_DOUT_CMU_NPU_BUS, "dout_cmu_npu_bus", "gout_cmu_npu_bus",
989 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
990 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
991 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
992 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
993 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
994 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
995 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
996 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
997 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
998 DIV(CLK_DOUT_CMU_PERIS_BUS, "dout_cmu_peris_bus", "gout_cmu_peris_bus",
999 CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
1000 DIV(CLK_DOUT_CMU_SSP_BUS, "dout_cmu_ssp_bus", "gout_cmu_ssp_bus",
1001 CLK_CON_DIV_CLKCMU_SSP_BUS, 0, 4),
1002 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
1003 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1004 DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
1005 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
1006 DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
1007 CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
1008 DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
1009 CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
1010 DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
1011 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
1012 };
1013
1014 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
1015 FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie",
1016 "gout_cmu_hsi1_pcie", 1, 8, 0),
1017 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
1018 FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
1019 "gout_cmu_hsi0_usbdp_debug", 1, 8, 0),
1020 FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie",
1021 "gout_cmu_hsi2_pcie", 1, 8, 0),
1022 };
1023
1024 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
1025 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
1026 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
1027 GATE(CLK_GOUT_CMU_AUD_CPU, "gout_cmu_aud_cpu", "mout_cmu_aud_cpu",
1028 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
1029 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1030 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, CLK_IGNORE_UNUSED, 0),
1031 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1032 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, CLK_IGNORE_UNUSED, 0),
1033 GATE(CLK_GOUT_CMU_BUS1_SSS, "gout_cmu_bus1_sss", "mout_cmu_bus1_sss",
1034 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS, 21, CLK_IGNORE_UNUSED, 0),
1035 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1036 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1037 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1038 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1039 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1040 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1041 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1042 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1043 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1044 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1045 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1046 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1047 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1048 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IGNORE_UNUSED, 0),
1049 GATE(CLK_GOUT_CMU_CPUCL0_DBG_BUS, "gout_cmu_cpucl0_dbg_bus",
1050 "mout_cmu_cpucl0_dbg_bus", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1051 21, 0, 0),
1052 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1053 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1054 21, CLK_IGNORE_UNUSED, 0),
1055 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1056 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1057 21, CLK_IGNORE_UNUSED, 0),
1058 GATE(CLK_GOUT_CMU_CPUCL2_BUSP, "gout_cmu_cpucl2_busp",
1059 "mout_cmu_cpucl2_busp", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP,
1060 21, CLK_IGNORE_UNUSED, 0),
1061 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1062 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
1063 21, CLK_IGNORE_UNUSED, 0),
1064 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1065 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1066 GATE(CLK_GOUT_CMU_CSIS_OIS_MCU, "gout_cmu_csis_ois_mcu",
1067 "mout_cmu_csis_ois_mcu", CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
1068 21, 0, 0),
1069 GATE(CLK_GOUT_CMU_DNC_BUS, "gout_cmu_dnc_bus", "mout_cmu_dnc_bus",
1070 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS, 21, 0, 0),
1071 GATE(CLK_GOUT_CMU_DNC_BUSM, "gout_cmu_dnc_busm", "mout_cmu_dnc_busm",
1072 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM, 21, 0, 0),
1073 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1074 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1075 GATE(CLK_GOUT_CMU_DPU, "gout_cmu_dpu", "mout_cmu_dpu",
1076 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
1077 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_alt",
1078 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, CLK_IGNORE_UNUSED, 0),
1079 GATE(CLK_GOUT_CMU_DSP_BUS, "gout_cmu_dsp_bus", "mout_cmu_dsp_bus",
1080 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 21, 0, 0),
1081 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1082 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1083 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1084 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1085 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1086 "fout_shared2_pll", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1087 21, 0, 0),
1088 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1089 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1090 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus",
1091 "mout_cmu_hsi0_bus", CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1092 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1093 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1094 21, 0, 0),
1095 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1096 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
1097 21, 0, 0),
1098 GATE(CLK_GOUT_CMU_HSI0_USBDP_DEBUG, "gout_cmu_hsi0_usbdp_debug",
1099 "mout_cmu_hsi0_usbdp_debug", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG,
1100 21, 0, 0),
1101 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1102 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1103 GATE(CLK_GOUT_CMU_HSI1_MMC_CARD, "gout_cmu_hsi1_mmc_card",
1104 "mout_cmu_hsi1_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
1105 21, 0, 0),
1106 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie",
1107 "mout_cmu_hsi1_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
1108 21, 0, 0),
1109 GATE(CLK_GOUT_CMU_HSI1_UFS_CARD, "gout_cmu_hsi1_ufs_card",
1110 "mout_cmu_hsi1_ufs_card", CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD,
1111 21, 0, 0),
1112 GATE(CLK_GOUT_CMU_HSI1_UFS_EMBD, "gout_cmu_hsi1_ufs_embd",
1113 "mout_cmu_hsi1_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
1114 21, 0, 0),
1115 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1116 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1117 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie",
1118 "mout_cmu_hsi2_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
1119 21, 0, 0),
1120 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1121 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1122 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1123 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1124 GATE(CLK_GOUT_CMU_MCSC_BUS, "gout_cmu_mcsc_bus", "mout_cmu_mcsc_bus",
1125 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, 21, 0, 0),
1126 GATE(CLK_GOUT_CMU_MCSC_GDC, "gout_cmu_mcsc_gdc", "mout_cmu_mcsc_gdc",
1127 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, 21, 0, 0),
1128 GATE(CLK_GOUT_CMU_MFC0_MFC0, "gout_cmu_mfc0_mfc0",
1129 "mout_cmu_mfc0_mfc0", CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
1130 21, 0, 0),
1131 GATE(CLK_GOUT_CMU_MFC0_WFD, "gout_cmu_mfc0_wfd", "mout_cmu_mfc0_wfd",
1132 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, 21, 0, 0),
1133 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1134 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1135 GATE(CLK_GOUT_CMU_NPU_BUS, "gout_cmu_npu_bus", "mout_cmu_npu_bus",
1136 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
1137 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1138 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1139 21, 0, 0),
1140 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip",
1141 "mout_cmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
1142 21, 0, 0),
1143 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1144 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1145 21, 0, 0),
1146 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip",
1147 "mout_cmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
1148 21, 0, 0),
1149 GATE(CLK_GOUT_CMU_PERIS_BUS, "gout_cmu_peris_bus",
1150 "mout_cmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
1151 21, CLK_IGNORE_UNUSED, 0),
1152 GATE(CLK_GOUT_CMU_SSP_BUS, "gout_cmu_ssp_bus", "mout_cmu_ssp_bus",
1153 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS, 21, 0, 0),
1154 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1155 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1156 GATE(CLK_GOUT_CMU_VRA_BUS, "gout_cmu_vra_bus", "mout_cmu_vra_bus",
1157 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS, 21, 0, 0),
1158 };
1159
1160 static const struct samsung_cmu_info top_cmu_info __initconst = {
1161 .pll_clks = top_pll_clks,
1162 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1163 .mux_clks = top_mux_clks,
1164 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1165 .div_clks = top_div_clks,
1166 .nr_div_clks = ARRAY_SIZE(top_div_clks),
1167 .fixed_factor_clks = cmu_top_ffactor,
1168 .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
1169 .gate_clks = top_gate_clks,
1170 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1171 .nr_clk_ids = CLKS_NR_TOP,
1172 .clk_regs = top_clk_regs,
1173 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1174 };
1175
exynos990_cmu_top_init(struct device_node * np)1176 static void __init exynos990_cmu_top_init(struct device_node *np)
1177 {
1178 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1179 }
1180
1181 /* Register CMU_TOP early, as it's a dependency for other early domains */
1182 CLK_OF_DECLARE(exynos990_cmu_top, "samsung,exynos990-cmu-top",
1183 exynos990_cmu_top_init);
1184
1185 /* ---- CMU_HSI0 ------------------------------------------------------------ */
1186
1187 /* Register Offset definitions for CMU_HSI0 (0x10a00000) */
1188 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0600
1189 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0620
1190 #define PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER 0x0630
1191 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0610
1192 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x2004
1193 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK 0x2018
1194 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2014
1195 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2020
1196 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK 0x2044
1197 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2008
1198 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x200c
1199 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x2010
1200 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK 0x201c
1201 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2024
1202 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2028
1203 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x202c
1204 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2034
1205 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x203c
1206 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2040
1207 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2030
1208 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1209 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK 0x2048
1210 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x2038
1211
1212 static const unsigned long hsi0_clk_regs[] __initconst = {
1213 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
1214 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
1215 PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
1216 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
1217 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
1218 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1219 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
1220 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
1221 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
1222 CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
1223 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
1224 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
1225 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
1226 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1227 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1228 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1229 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
1230 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
1231 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1232 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1233 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
1234 CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
1235 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1236 };
1237
1238 /* Parent clock list for CMU_HSI0 muxes */
1239 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
1240 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", "dout_cmu_hsi0_usb31drd" };
1241 PNAME(mout_hsi0_usbdp_debug_user_p) = { "oscclk",
1242 "dout_cmu_hsi0_usbdp_debug" };
1243 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
1244
1245 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1246 MUX(CLK_MOUT_HSI0_BUS_USER, "mout_hsi0_bus_user",
1247 mout_hsi0_bus_user_p, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
1248 4, 1),
1249 MUX(CLK_MOUT_HSI0_USB31DRD_USER, "mout_hsi0_usb31drd_user",
1250 mout_hsi0_usb31drd_user_p, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
1251 4, 1),
1252 MUX(CLK_MOUT_HSI0_USBDP_DEBUG_USER, "mout_hsi0_usbdp_debug_user",
1253 mout_hsi0_usbdp_debug_user_p,
1254 PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
1255 4, 1),
1256 MUX(CLK_MOUT_HSI0_DPGTC_USER, "mout_hsi0_dpgtc_user",
1257 mout_hsi0_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
1258 4, 1),
1259 };
1260
1261 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
1262 GATE(CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK,
1263 "gout_hsi0_dp_link_dp_gtc_clk", "mout_hsi0_dpgtc_user",
1264 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
1265 21, 0, 0),
1266 GATE(CLK_GOUT_HSI0_DP_LINK_PCLK,
1267 "gout_hsi0_dp_link_pclk", "mout_hsi0_bus_user",
1268 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1269 21, 0, 0),
1270 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
1271 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus_user",
1272 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
1273 21, 0, 0),
1274 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK,
1275 "gout_hsi0_lhm_axi_p_hsi0_clk", "mout_hsi0_bus_user",
1276 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
1277 21, CLK_IS_CRITICAL, 0),
1278 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK,
1279 "gout_hsi0_ppmu_hsi0_bus1_aclk", "mout_hsi0_bus_user",
1280 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
1281 21, 0, 0),
1282 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK,
1283 "gout_hsi0_ppmu_hsi0_bus1_pclk", "mout_hsi0_bus_user",
1284 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
1285 21, 0, 0),
1286 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
1287 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus_user",
1288 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
1289 21, 0, 0),
1290 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
1291 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus_user",
1292 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1293 21, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
1295 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus_user",
1296 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1297 21, 0, 0),
1298 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
1299 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus_user",
1300 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1301 21, 0, 0),
1302 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
1303 "gout_hsi0_usb31drd_bus_clk_early",
1304 "mout_hsi0_bus_user",
1305 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
1306 21, 0, 0),
1307 GATE(CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40,
1308 "gout_hsi0_usb31drd_usb31drd_ref_clk_40",
1309 "mout_hsi0_usb31drd_user",
1310 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
1311 21, 0, 0),
1312 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL,
1313 "gout_hsi0_usb31drd_usbdpphy_ref_soc_pll",
1314 "mout_hsi0_usbdp_debug_user",
1315 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
1316 21, 0, 0),
1317 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB,
1318 "gout_hsi0_usb31drd_ipclkport_i_usbdpphy_scl_apb_pclk",
1319 "mout_hsi0_bus_user",
1320 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1321 21, 0, 0),
1322 GATE(CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK,
1323 "gout_hsi0_usb31drd_usbpcs_apb_clk",
1324 "mout_hsi0_bus_user",
1325 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1326 21, 0, 0),
1327 GATE(CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK,
1328 "gout_hsi0_vgen_lite_ipclkport_clk", "mout_hsi0_bus_user",
1329 CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
1330 21, 0, 0),
1331 GATE(CLK_GOUT_HSI0_CMU_HSI0_PCLK,
1332 "gout_hsi0_cmu_hsi0_pclk", "mout_hsi0_bus_user",
1333 CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
1334 21, CLK_IGNORE_UNUSED, 0),
1335 GATE(CLK_GOUT_HSI0_XIU_D_HSI0_ACLK,
1336 "gout_hsi0_xiu_d_hsi0_aclk", "mout_hsi0_bus_user",
1337 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1338 21, CLK_IGNORE_UNUSED, 0),
1339 GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK,
1340 "gout_hsi0_lhs_acel_d_hsi0_clk", "mout_hsi0_bus_user",
1341 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
1342 21, CLK_IS_CRITICAL, 0),
1343 };
1344
1345 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1346 .mux_clks = hsi0_mux_clks,
1347 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1348 .gate_clks = hsi0_gate_clks,
1349 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
1350 .nr_clk_ids = CLKS_NR_HSI0,
1351 .clk_regs = hsi0_clk_regs,
1352 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1353 .clk_name = "bus",
1354 };
1355
1356 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1357
1358 /* Register Offset definitions for CMU_PERIC0 (0x10400000) */
1359 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1360 #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
1361 #define PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG 0x0610
1362 #define PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG 0x0614
1363 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0620
1364 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER 0x0624
1365 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0630
1366 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER 0x0634
1367 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0640
1368 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER 0x0644
1369 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0650
1370 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER 0x0654
1371 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0660
1372 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER 0x0664
1373 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0670
1374 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER 0x0674
1375 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0680
1376 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER 0x0684
1377 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0690
1378 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0694
1379 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a0
1380 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER 0x06a4
1381 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b0
1382 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER 0x06b4
1383 #define CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG 0x1800
1384 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1385 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1386 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1387 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1388 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1389 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1390 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI 0x181c
1391 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x1820
1392 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI 0x1824
1393 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1394 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
1395 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
1396 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
1397 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2010
1398 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2014
1399 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2018
1400 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x201c
1401 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x2020
1402 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2024
1403 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2028
1404 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x202c
1405 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2030
1406 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2034
1407 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2038
1408 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x203c
1409 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2040
1410 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2044
1411 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2048
1412 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x204c
1413 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x2050
1414 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2054
1415 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2058
1416 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x205c
1417 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1418 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1419 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1420 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1421 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1422 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1423 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x2078
1424 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3 0x207c
1425 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4 0x2080
1426 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5 0x2084
1427 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6 0x2088
1428 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7 0x208c
1429 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8 0x2090
1430 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x2094
1431 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15 0x2098
1432 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3 0x209c
1433 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4 0x20a0
1434 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5 0x20a4
1435 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6 0x20a8
1436 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7 0x20ac
1437 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8 0x20b0
1438 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
1439 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK 0x20b8
1440 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK 0x20bc
1441 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK 0x20c0
1442 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK 0x20c4
1443 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK 0x20c8
1444 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK 0x20cc
1445 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK 0x20d0
1446 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK 0x20d4
1447 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20d8
1448 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK 0x20dc
1449 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK 0x20e0
1450 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e4
1451
1452 static const unsigned long peric0_clk_regs[] __initconst = {
1453 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1454 PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
1455 PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
1456 PLL_CON1_MUX_CLKCMU_PERIC0_UART_DBG,
1457 PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
1458 PLL_CON1_MUX_CLKCMU_PERIC0_USI00_USI_USER,
1459 PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
1460 PLL_CON1_MUX_CLKCMU_PERIC0_USI01_USI_USER,
1461 PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
1462 PLL_CON1_MUX_CLKCMU_PERIC0_USI02_USI_USER,
1463 PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
1464 PLL_CON1_MUX_CLKCMU_PERIC0_USI03_USI_USER,
1465 PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
1466 PLL_CON1_MUX_CLKCMU_PERIC0_USI04_USI_USER,
1467 PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
1468 PLL_CON1_MUX_CLKCMU_PERIC0_USI05_USI_USER,
1469 PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
1470 PLL_CON1_MUX_CLKCMU_PERIC0_USI13_USI_USER,
1471 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
1472 PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
1473 PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
1474 PLL_CON1_MUX_CLKCMU_PERIC0_USI15_USI_USER,
1475 PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
1476 PLL_CON1_MUX_CLKCMU_PERIC0_USI_I2C_USER,
1477 CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
1478 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1479 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1480 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1481 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1482 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1483 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1484 CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
1485 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
1486 CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
1487 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1488 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
1489 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
1490 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
1491 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
1492 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
1493 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1494 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1495 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
1496 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
1497 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
1498 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
1499 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1500 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1501 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1502 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1503 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1504 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1505 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1506 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1507 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
1508 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
1509 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
1510 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
1511 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1512 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1513 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1514 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1515 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1516 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1517 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
1518 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3,
1519 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4,
1520 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5,
1521 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6,
1522 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7,
1523 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8,
1524 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
1525 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15,
1526 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3,
1527 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4,
1528 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5,
1529 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6,
1530 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7,
1531 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8,
1532 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
1533 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
1534 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
1535 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
1536 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
1537 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
1538 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
1539 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
1540 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
1541 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
1542 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
1543 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
1544 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
1545 };
1546
1547 /* Parent clock list for CMU_PERIC0 muxes */
1548 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
1549 PNAME(mout_peric0_uart_dbg_p) = { "oscclk", "dout_cmu_peric0_ip" };
1550 PNAME(mout_peric0_usi00_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1551 PNAME(mout_peric0_usi01_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1552 PNAME(mout_peric0_usi02_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1553 PNAME(mout_peric0_usi03_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1554 PNAME(mout_peric0_usi04_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1555 PNAME(mout_peric0_usi05_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1556 PNAME(mout_peric0_usi13_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1557 PNAME(mout_peric0_usi14_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1558 PNAME(mout_peric0_usi15_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1559 PNAME(mout_peric0_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
1560
1561 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1562 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
1563 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
1564 4, 1),
1565 MUX(CLK_MOUT_PERIC0_UART_DBG, "mout_peric0_uart_dbg",
1566 mout_peric0_uart_dbg_p, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG,
1567 4, 1),
1568 MUX(CLK_MOUT_PERIC0_USI00_USI_USER, "mout_peric0_usi00_usi_user",
1569 mout_peric0_usi00_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USI_USER,
1570 4, 1),
1571 MUX(CLK_MOUT_PERIC0_USI01_USI_USER, "mout_peric0_usi01_usi_user",
1572 mout_peric0_usi01_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USI_USER,
1573 4, 1),
1574 MUX(CLK_MOUT_PERIC0_USI02_USI_USER, "mout_peric0_usi02_usi_user",
1575 mout_peric0_usi02_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USI_USER,
1576 4, 1),
1577 MUX(CLK_MOUT_PERIC0_USI03_USI_USER, "mout_peric0_usi03_usi_user",
1578 mout_peric0_usi03_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USI_USER,
1579 4, 1),
1580 MUX(CLK_MOUT_PERIC0_USI04_USI_USER, "mout_peric0_usi04_usi_user",
1581 mout_peric0_usi04_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI04_USI_USER,
1582 4, 1),
1583 MUX(CLK_MOUT_PERIC0_USI05_USI_USER, "mout_peric0_usi05_usi_user",
1584 mout_peric0_usi05_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI05_USI_USER,
1585 4, 1),
1586 MUX(CLK_MOUT_PERIC0_USI13_USI_USER, "mout_peric0_usi13_usi_user",
1587 mout_peric0_usi13_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI13_USI_USER,
1588 4, 1),
1589 MUX(CLK_MOUT_PERIC0_USI14_USI_USER, "mout_peric0_usi14_usi_user",
1590 mout_peric0_usi14_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
1591 4, 1),
1592 MUX(CLK_MOUT_PERIC0_USI15_USI_USER, "mout_peric0_usi15_usi_user",
1593 mout_peric0_usi15_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI15_USI_USER,
1594 4, 1),
1595 MUX(CLK_MOUT_PERIC0_USI_I2C_USER, "mout_peric0_usi_i2c_user",
1596 mout_peric0_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_USI_I2C_USER,
1597 4, 1),
1598 };
1599
1600 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1601 DIV(CLK_DOUT_PERIC0_UART_DBG, "dout_peric0_uart_dbg",
1602 "mout_peric0_uart_dbg",
1603 CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG,
1604 0, 4),
1605 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1606 "mout_peric0_usi00_usi_user",
1607 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1608 0, 4),
1609 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1610 "mout_peric0_usi01_usi_user",
1611 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1612 0, 4),
1613 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1614 "mout_peric0_usi02_usi_user",
1615 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1616 0, 4),
1617 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1618 "mout_peric0_usi03_usi_user",
1619 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1620 0, 4),
1621 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1622 "mout_peric0_usi04_usi_user",
1623 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1624 0, 4),
1625 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1626 "mout_peric0_usi05_usi_user",
1627 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1628 0, 4),
1629 DIV(CLK_DOUT_PERIC0_USI13_USI, "dout_peric0_usi13_usi",
1630 "mout_peric0_usi13_usi_user",
1631 CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI,
1632 0, 4),
1633 DIV(CLK_DOUT_PERIC0_USI14_USI, "dout_peric0_usi14_usi",
1634 "mout_peric0_usi14_usi_user",
1635 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
1636 0, 4),
1637 DIV(CLK_DOUT_PERIC0_USI15_USI, "dout_peric0_usi15_usi",
1638 "mout_peric0_usi15_usi_user",
1639 CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI,
1640 0, 4),
1641 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1642 "mout_peric0_usi_i2c_user",
1643 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1644 0, 4),
1645 };
1646
1647 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
1648 GATE(CLK_GOUT_PERIC0_CMU_PCLK, "gout_peric0_cmu_pclk",
1649 "mout_peric0_bus_user",
1650 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
1651 21, CLK_IS_CRITICAL, 0),
1652 GATE(CLK_GOUT_PERIC0_OSCCLK_CLK, "gout_peric0_oscclk_clk",
1653 "oscclk",
1654 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
1655 21, 0, 0),
1656 GATE(CLK_GOUT_PERIC0_D_TZPC_PCLK, "gout_peric0_d_tpzc_pclk",
1657 "mout_peric0_bus_user",
1658 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
1659 21, 0, 0),
1660 GATE(CLK_GOUT_PERIC0_GPIO_PCLK, "gout_peric0_gpio_pclk",
1661 "mout_peric0_bus_user",
1662 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
1663 21, CLK_IGNORE_UNUSED, 0),
1664 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_CLK, "gout_peric0_lhm_axi_p_clk",
1665 "mout_peric0_bus_user",
1666 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
1667 21, CLK_IS_CRITICAL, 0),
1668 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_10, "gout_peric0_top0_ipclk_10",
1669 "dout_peric0_usi_i2c",
1670 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
1671 21, 0, 0),
1672 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_11, "gout_peric0_top0_ipclk_11",
1673 "dout_peric0_usi03_usi",
1674 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
1675 21, 0, 0),
1676 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_12, "gout_peric0_top0_ipclk_12",
1677 "dout_peric0_usi_i2c",
1678 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
1679 21, 0, 0),
1680 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_13, "gout_peric0_top0_ipclk_13",
1681 "dout_peric0_usi04_usi",
1682 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
1683 21, 0, 0),
1684 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_14, "gout_peric0_top0_ipclk_14",
1685 "dout_peric0_usi_i2c",
1686 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
1687 21, 0, 0),
1688 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_15, "gout_peric0_top0_ipclk_15",
1689 "dout_peric0_usi05_usi",
1690 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
1691 21, 0, 0),
1692 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_4, "gout_peric0_top0_ipclk_4",
1693 "dout_peric0_uart_dbg",
1694 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
1695 21, 0, 0),
1696 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_5, "gout_peric0_top0_ipclk_5",
1697 "dout_peric0_usi00_usi",
1698 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
1699 21, 0, 0),
1700 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_6, "gout_peric0_top0_ipclk_6",
1701 "dout_peric0_usi_i2c",
1702 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
1703 21, 0, 0),
1704 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_7, "gout_peric0_top0_ipclk_7",
1705 "dout_peric0_usi01_usi",
1706 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
1707 21, 0, 0),
1708 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_8, "gout_peric0_top0_ipclk_8",
1709 "dout_peric0_usi_i2c",
1710 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
1711 21, 0, 0),
1712 GATE(CLK_GOUT_PERIC0_TOP0_IPCLK_9, "gout_peric0_top0_ipclk_9",
1713 "dout_peric0_usi02_usi",
1714 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
1715 21, 0, 0),
1716 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_10, "gout_peric0_top0_pclk_10",
1717 "mout_peric0_bus_user",
1718 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
1719 21, 0, 0),
1720 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_11, "gout_peric0_top0_pclk_11",
1721 "mout_peric0_bus_user",
1722 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
1723 21, 0, 0),
1724 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_12, "gout_peric0_top0_pclk_12",
1725 "mout_peric0_bus_user",
1726 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
1727 21, 0, 0),
1728 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_13, "gout_peric0_top0_pclk_13",
1729 "mout_peric0_bus_user",
1730 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
1731 21, 0, 0),
1732 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_14, "gout_peric0_top0_pclk_14",
1733 "mout_peric0_bus_user",
1734 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
1735 21, 0, 0),
1736 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_15, "gout_peric0_top0_pclk_15",
1737 "mout_peric0_bus_user",
1738 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
1739 21, 0, 0),
1740 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_4, "gout_peric0_top0_pclk_4",
1741 "mout_peric0_bus_user",
1742 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
1743 21, 0, 0),
1744 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_5, "gout_peric0_top0_pclk_5",
1745 "mout_peric0_bus_user",
1746 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
1747 21, 0, 0),
1748 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_6, "gout_peric0_top0_pclk_6",
1749 "mout_peric0_bus_user",
1750 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
1751 21, 0, 0),
1752 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_7, "gout_peric0_top0_pclk_7",
1753 "mout_peric0_bus_user",
1754 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
1755 21, 0, 0),
1756 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_8, "gout_peric0_top0_pclk_8",
1757 "mout_peric0_bus_user",
1758 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
1759 21, 0, 0),
1760 GATE(CLK_GOUT_PERIC0_TOP0_PCLK_9, "gout_peric0_top0_pclk_9",
1761 "mout_peric0_bus_user",
1762 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
1763 21, 0, 0),
1764 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_0, "gout_peric0_top1_ipclk_0",
1765 "dout_peric0_usi_i2c",
1766 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
1767 21, 0, 0),
1768 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_3, "gout_peric0_top1_ipclk_3",
1769 "dout_peric0_usi13_usi",
1770 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3,
1771 21, 0, 0),
1772 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_4, "gout_peric0_top1_ipclk_4",
1773 "dout_peric0_usi_i2c",
1774 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4,
1775 21, 0, 0),
1776 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_5, "gout_peric0_top1_ipclk_5",
1777 "dout_peric0_usi14_usi",
1778 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5,
1779 21, 0, 0),
1780 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_6, "gout_peric0_top1_ipclk_6",
1781 "dout_peric0_usi_i2c",
1782 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6,
1783 21, 0, 0),
1784 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_7, "gout_peric0_top1_ipclk_7",
1785 "dout_peric0_usi15_usi",
1786 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7,
1787 21, 0, 0),
1788 GATE(CLK_GOUT_PERIC0_TOP1_IPCLK_8, "gout_peric0_top1_ipclk_8",
1789 "dout_peric0_usi_i2c",
1790 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8,
1791 21, 0, 0),
1792 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_0, "gout_peric0_top1_pclk_0",
1793 "mout_peric0_bus_user",
1794 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
1795 21, 0, 0),
1796 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_15, "gout_peric0_top1_pclk_15",
1797 "mout_peric0_bus_user",
1798 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15,
1799 21, 0, 0),
1800 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_3, "gout_peric0_top1_pclk_3",
1801 "mout_peric0_bus_user",
1802 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3,
1803 21, 0, 0),
1804 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_4, "gout_peric0_top1_pclk_4",
1805 "mout_peric0_bus_user",
1806 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4,
1807 21, 0, 0),
1808 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_5, "gout_peric0_top1_pclk_5",
1809 "mout_peric0_bus_user",
1810 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5,
1811 21, 0, 0),
1812 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_6, "gout_peric0_top1_pclk_6",
1813 "mout_peric0_bus_user",
1814 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6,
1815 21, 0, 0),
1816 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_7, "gout_peric0_top1_pclk_7",
1817 "mout_peric0_bus_user",
1818 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7,
1819 21, 0, 0),
1820 GATE(CLK_GOUT_PERIC0_TOP1_PCLK_8, "gout_peric0_top1_pclk_8",
1821 "mout_peric0_bus_user",
1822 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8,
1823 21, 0, 0),
1824 GATE(CLK_GOUT_PERIC0_BUSP_CLK, "gout_peric0_busp_clk",
1825 "mout_peric0_bus_user",
1826 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
1827 21, 0, 0),
1828 GATE(CLK_GOUT_PERIC0_UART_DBG_CLK, "gout_peric0_uart_dbg_clk",
1829 "dout_peric0_uart_dbg",
1830 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
1831 21, 0, 0),
1832 GATE(CLK_GOUT_PERIC0_USI00_USI_CLK, "gout_peric0_usi00_usi_clk",
1833 "dout_peric0_usi00_usi",
1834 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
1835 21, 0, 0),
1836 GATE(CLK_GOUT_PERIC0_USI01_USI_CLK, "gout_peric0_usi01_usi_clk",
1837 "dout_peric0_usi01_usi",
1838 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
1839 21, 0, 0),
1840 GATE(CLK_GOUT_PERIC0_USI02_USI_CLK, "gout_peric0_usi02_usi_clk",
1841 "dout_peric0_usi02_usi",
1842 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
1843 21, 0, 0),
1844 GATE(CLK_GOUT_PERIC0_USI03_USI_CLK, "gout_peric0_usi03_usi_clk",
1845 "dout_peric0_usi03_usi",
1846 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
1847 21, 0, 0),
1848 GATE(CLK_GOUT_PERIC0_USI04_USI_CLK, "gout_peric0_usi04_usi_clk",
1849 "dout_peric0_usi04_usi",
1850 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
1851 21, 0, 0),
1852 GATE(CLK_GOUT_PERIC0_USI05_USI_CLK, "gout_peric0_usi05_usi_clk",
1853 "dout_peric0_usi05_usi",
1854 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
1855 21, 0, 0),
1856 GATE(CLK_GOUT_PERIC0_USI13_USI_CLK, "gout_peric0_usi13_usi_clk",
1857 "dout_peric0_usi13_usi",
1858 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
1859 21, 0, 0),
1860 GATE(CLK_GOUT_PERIC0_USI14_USI_CLK, "gout_peric0_usi14_usi_clk",
1861 "dout_peric0_usi14_usi",
1862 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
1863 21, 0, 0),
1864 GATE(CLK_GOUT_PERIC0_USI15_USI_CLK, "gout_peric0_usi15_usi_clk",
1865 "dout_peric0_usi15_usi",
1866 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
1867 21, 0, 0),
1868 GATE(CLK_GOUT_PERIC0_USI_I2C_CLK, "gout_peric0_usi_i2c_clk",
1869 "dout_peric0_usi_i2c",
1870 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
1871 21, 0, 0),
1872 GATE(CLK_GOUT_PERIC0_SYSREG_PCLK, "gout_peric0_sysreg_pclk",
1873 "mout_peric0_bus_user",
1874 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
1875 21, 0, 0)
1876 };
1877
1878 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1879 .mux_clks = peric0_mux_clks,
1880 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1881 .div_clks = peric0_div_clks,
1882 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1883 .gate_clks = peric0_gate_clks,
1884 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
1885 .nr_clk_ids = CLKS_NR_PERIC0,
1886 .clk_regs = peric0_clk_regs,
1887 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1888 .clk_name = "bus",
1889 };
1890
1891 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1892
1893 /* Register Offset definitions for CMU_PERIC1 (0x10700000) */
1894 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1895 #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
1896 #define PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0610
1897 #define PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER 0x0614
1898 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0620
1899 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER 0x0624
1900 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0630
1901 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER 0x0634
1902 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0640
1903 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER 0x0644
1904 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0650
1905 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER 0x0654
1906 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0660
1907 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0664
1908 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0670
1909 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0674
1910 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0680
1911 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0684
1912 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0690
1913 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER 0x0694
1914 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a0
1915 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER 0x06a4
1916 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b0
1917 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER 0x06b4
1918 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c0
1919 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER 0x06c4
1920 #define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1800
1921 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1804
1922 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1808
1923 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x180c
1924 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1810
1925 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1814
1926 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1818
1927 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x181c
1928 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1929 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1930 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI 0x1828
1931 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x182c
1932 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
1933 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK 0x2008
1934 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x200c
1935 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK 0x2010
1936 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2014
1937 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
1938 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK 0x201c
1939 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x2020
1940 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x2024
1941 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2028
1942 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12 0x202c
1943 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13 0x2030
1944 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14 0x2034
1945 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15 0x2038
1946 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x203c
1947 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x2040
1948 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2044
1949 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12 0x2048
1950 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13 0x204c
1951 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14 0x2050
1952 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2054
1953 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2058
1954 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0 0x205c
1955 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1 0x2060
1956 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10 0x2064
1957 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12 0x206c
1958 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13 0x2070
1959 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14 0x2074
1960 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15 0x2078
1961 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2 0x207c
1962 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3 0x2080
1963 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4 0x2084
1964 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5 0x2088
1965 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6 0x208c
1966 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7 0x2090
1967 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9 0x2098
1968 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0 0x209c
1969 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1 0x20a0
1970 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10 0x20a4
1971 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12 0x20ac
1972 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13 0x20b0
1973 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14 0x20b4
1974 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15 0x20b8
1975 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2 0x20bc
1976 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3 0x20c0
1977 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4 0x20c4
1978 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5 0x20c8
1979 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6 0x20cc
1980 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7 0x20d0
1981 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9 0x20d8
1982 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x20dc
1983 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x20e0
1984 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK 0x20e4
1985 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK 0x20e8
1986 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK 0x20ec
1987 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK 0x20f0
1988 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x20f4
1989 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x20f8
1990 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK 0x20fc
1991 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK 0x2100
1992 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK 0x2104
1993 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2108
1994 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK 0x210c
1995 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK 0x2110
1996 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK 0x2114
1997 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK 0x2118
1998 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x211c
1999
2000 static const unsigned long peric1_clk_regs[] __initconst = {
2001 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
2002 PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
2003 PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
2004 PLL_CON1_MUX_CLKCMU_PERIC1_UART_BT_USER,
2005 PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
2006 PLL_CON1_MUX_CLKCMU_PERIC1_USI06_USI_USER,
2007 PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
2008 PLL_CON1_MUX_CLKCMU_PERIC1_USI07_USI_USER,
2009 PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
2010 PLL_CON1_MUX_CLKCMU_PERIC1_USI08_USI_USER,
2011 PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
2012 PLL_CON1_MUX_CLKCMU_PERIC1_USI09_USI_USER,
2013 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
2014 PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
2015 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
2016 PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
2017 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
2018 PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
2019 PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
2020 PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER,
2021 PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
2022 PLL_CON1_MUX_CLKCMU_PERIC1_USI17_USI_USER,
2023 PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
2024 PLL_CON1_MUX_CLKCMU_PERIC1_USI18_USI_USER,
2025 PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
2026 PLL_CON1_MUX_CLKCMU_PERIC1_USI_I2C_USER,
2027 CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
2028 CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
2029 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
2030 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
2031 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
2032 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
2033 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
2034 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
2035 CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
2036 CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
2037 CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
2038 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
2039 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
2040 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
2041 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
2042 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK,
2043 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
2044 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
2045 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
2046 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
2047 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
2048 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
2049 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12,
2050 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13,
2051 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14,
2052 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15,
2053 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
2054 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
2055 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
2056 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12,
2057 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13,
2058 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14,
2059 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
2060 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
2061 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0,
2062 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1,
2063 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10,
2064 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12,
2065 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13,
2066 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14,
2067 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15,
2068 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2,
2069 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3,
2070 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4,
2071 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5,
2072 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6,
2073 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7,
2074 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9,
2075 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0,
2076 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1,
2077 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10,
2078 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12,
2079 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13,
2080 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14,
2081 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15,
2082 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2,
2083 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3,
2084 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4,
2085 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5,
2086 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6,
2087 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7,
2088 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9,
2089 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
2090 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
2091 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
2092 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
2093 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
2094 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
2095 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
2096 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
2097 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
2098 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
2099 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
2100 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
2101 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
2102 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
2103 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK,
2104 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK,
2105 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
2106 };
2107
2108 /* Parent clock list for CMU_PERIC1 muxes */
2109 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
2110 PNAME(mout_peric1_uart_bt_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2111 PNAME(mout_peric1_usi06_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2112 PNAME(mout_peric1_usi07_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2113 PNAME(mout_peric1_usi08_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2114 PNAME(mout_peric1_usi09_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2115 PNAME(mout_peric1_usi10_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2116 PNAME(mout_peric1_usi11_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2117 PNAME(mout_peric1_usi12_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2118 PNAME(mout_peric1_usi18_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2119 PNAME(mout_peric1_usi16_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2120 PNAME(mout_peric1_usi17_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2121 PNAME(mout_peric1_usi_i2c_user_p) = { "oscclk", "dout_cmu_peric1_ip" };
2122
2123 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
2124 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
2125 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
2126 4, 1),
2127 MUX(CLK_MOUT_PERIC1_UART_BT_USER, "mout_peric1_uart_bt_user",
2128 mout_peric1_uart_bt_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER,
2129 4, 1),
2130 MUX(CLK_MOUT_PERIC1_USI06_USI_USER, "mout_peric1_usi06_usi_user",
2131 mout_peric1_usi06_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USI_USER,
2132 4, 1),
2133 MUX(CLK_MOUT_PERIC1_USI07_USI_USER, "mout_peric1_usi07_usi_user",
2134 mout_peric1_usi07_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USI_USER,
2135 4, 1),
2136 MUX(CLK_MOUT_PERIC1_USI08_USI_USER, "mout_peric1_usi08_usi_user",
2137 mout_peric1_usi08_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USI_USER,
2138 4, 1),
2139 MUX(CLK_MOUT_PERIC1_USI09_USI_USER, "mout_peric1_usi09_usi_user",
2140 mout_peric1_usi09_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USI_USER,
2141 4, 1),
2142 MUX(CLK_MOUT_PERIC1_USI10_USI_USER, "mout_peric1_usi10_usi_user",
2143 mout_peric1_usi10_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
2144 4, 1),
2145 MUX(CLK_MOUT_PERIC1_USI11_USI_USER, "mout_peric1_usi11_usi_user",
2146 mout_peric1_usi11_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
2147 4, 1),
2148 MUX(CLK_MOUT_PERIC1_USI12_USI_USER, "mout_peric1_usi12_usi_user",
2149 mout_peric1_usi12_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
2150 4, 1),
2151 MUX(CLK_MOUT_PERIC1_USI18_USI_USER, "mout_peric1_usi18_usi_user",
2152 mout_peric1_usi18_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI18_USI_USER,
2153 4, 1),
2154 MUX(CLK_MOUT_PERIC1_USI16_USI_USER, "mout_peric1_usi16_usi_user",
2155 mout_peric1_usi16_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER,
2156 4, 1),
2157 MUX(CLK_MOUT_PERIC1_USI17_USI_USER, "mout_peric1_usi17_usi_user",
2158 mout_peric1_usi17_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI17_USI_USER,
2159 4, 1),
2160 MUX(CLK_MOUT_PERIC1_USI_I2C_USER, "mout_peric1_usi_i2c_user",
2161 mout_peric1_usi_i2c_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_USI_I2C_USER,
2162 4, 1),
2163 };
2164
2165 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
2166 DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt",
2167 "mout_peric1_uart_bt_user",
2168 CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT,
2169 0, 4),
2170 DIV(CLK_DOUT_PERIC1_USI06_USI, "dout_peric1_usi06_usi",
2171 "mout_peric1_usi06_usi_user",
2172 CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI,
2173 0, 4),
2174 DIV(CLK_DOUT_PERIC1_USI07_USI, "dout_peric1_usi07_usi",
2175 "mout_peric1_usi07_usi_user",
2176 CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI,
2177 0, 4),
2178 DIV(CLK_DOUT_PERIC1_USI08_USI, "dout_peric1_usi08_usi",
2179 "mout_peric1_usi08_usi_user",
2180 CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI,
2181 0, 4),
2182 DIV(CLK_DOUT_PERIC1_USI18_USI, "dout_peric1_usi18_usi",
2183 "mout_peric1_usi18_usi_user",
2184 CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI,
2185 0, 4),
2186 DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
2187 "mout_peric1_usi12_usi_user",
2188 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
2189 0, 4),
2190 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
2191 "mout_peric1_usi09_usi_user",
2192 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
2193 0, 4),
2194 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
2195 "mout_peric1_usi10_usi_user",
2196 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
2197 0, 4),
2198 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
2199 "mout_peric1_usi11_usi_user",
2200 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
2201 0, 4),
2202 DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
2203 "mout_peric1_usi16_usi_user",
2204 CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
2205 0, 4),
2206 DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
2207 "mout_peric1_usi17_usi_user",
2208 CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
2209 0, 4),
2210 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
2211 "mout_peric1_usi_i2c_user",
2212 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
2213 0, 4),
2214 };
2215
2216 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
2217 GATE(CLK_GOUT_PERIC1_CMU_PCLK, "gout_peric1_cmu_pclk",
2218 "mout_peric1_bus_user",
2219 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
2220 21, CLK_IS_CRITICAL, 0),
2221 GATE(CLK_GOUT_PERIC1_UART_BT_CLK, "gout_peric1_uart_bt_clk",
2222 "dout_peric1_uart_bt",
2223 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
2224 21, 0, 0),
2225 GATE(CLK_GOUT_PERIC1_USI12_USI_CLK, "gout_peric1_usi12_usi_clk",
2226 "dout_peric1_usi12_usi",
2227 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
2228 21, 0, 0),
2229 GATE(CLK_GOUT_PERIC1_USI18_USI_CLK, "gout_peric1_usi18_usi_clk",
2230 "dout_peric1_usi18_usi",
2231 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK,
2232 21, 0, 0),
2233 GATE(CLK_GOUT_PERIC1_D_TZPC_PCLK, "gout_peric1_d_tzpc_pclk",
2234 "dout_peric1_bus_user",
2235 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
2236 21, 0, 0),
2237 GATE(CLK_GOUT_PERIC1_GPIO_PCLK, "gout_peric1_gpio_pclk",
2238 "mout_peric1_bus_user",
2239 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
2240 21, CLK_IGNORE_UNUSED, 0),
2241 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK, "gout_peric1_lhm_axi_p_csis_clk",
2242 "mout_peric1_bus_user",
2243 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK,
2244 21, 0, 0),
2245 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_CLK, "gout_peric1_lhm_axi_p_clk",
2246 "mout_peric1_bus_user",
2247 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
2248 21, CLK_IS_CRITICAL, 0),
2249 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_10, "gout_peric1_top0_ipclk_10",
2250 "dout_peric1_usi06_usi",
2251 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10,
2252 21, 0, 0),
2253 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_11, "gout_peric1_top0_ipclk_11",
2254 "dout_peric1_usi_i2c",
2255 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11,
2256 21, 0, 0),
2257 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_12, "gout_peric1_top0_ipclk_12",
2258 "dout_peric1_usi07_usi",
2259 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_12,
2260 21, 0, 0),
2261 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_13, "gout_peric1_top0_ipclk_13",
2262 "dout_peric1_usi_i2c",
2263 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_13,
2264 21, 0, 0),
2265 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_14, "gout_peric1_top0_ipclk_14",
2266 "dout_peric1_usi08_usi",
2267 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_14,
2268 21, 0, 0),
2269 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_15, "gout_peric1_top0_ipclk_15",
2270 "dout_peric1_usi_i2c",
2271 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_15,
2272 21, 0, 0),
2273 GATE(CLK_GOUT_PERIC1_TOP0_IPCLK_4, "gout_peric1_top0_ipclk_4",
2274 "dout_peric1_uart_bt",
2275 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
2276 21, 0, 0),
2277 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_10, "gout_peric1_top0_pclk_10",
2278 "mout_peric1_bus_user",
2279 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
2280 21, 0, 0),
2281 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_11, "gout_peric1_top0_pclk_11",
2282 "mout_peric1_bus_user",
2283 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11,
2284 21, 0, 0),
2285 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_12, "gout_peric1_top0_pclk_12",
2286 "mout_peric1_bus_user",
2287 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_12,
2288 21, 0, 0),
2289 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_13, "gout_peric1_top0_pclk_13",
2290 "mout_peric1_bus_user",
2291 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_13,
2292 21, 0, 0),
2293 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_14, "gout_peric1_top0_pclk_14",
2294 "mout_peric1_bus_user",
2295 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_14,
2296 21, 0, 0),
2297 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_15, "gout_peric1_top0_pclk_15",
2298 "mout_peric1_bus_user",
2299 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
2300 21, 0, 0),
2301 GATE(CLK_GOUT_PERIC1_TOP0_PCLK_4, "gout_peric1_top0_pclk_4",
2302 "mout_peric1_bus_user",
2303 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
2304 21, 0, 0),
2305 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_0, "gout_peric1_top1_ipclk_0",
2306 "dout_peric1_usi09_usi",
2307 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_0,
2308 21, 0, 0),
2309 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_1, "gout_peric1_top1_ipclk_1",
2310 "dout_peric1_usi_i2c",
2311 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_1,
2312 21, 0, 0),
2313 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_10, "gout_peric1_top1_ipclk_10",
2314 "dout_peric1_usi_i2c",
2315 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10,
2316 21, 0, 0),
2317 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_12, "gout_peric1_top1_ipclk_12",
2318 "dout_peric1_usi12_usi",
2319 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12,
2320 21, 0, 0),
2321 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_13, "gout_peric1_top1_ipclk_13",
2322 "dout_peric1_usi_i2c",
2323 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13,
2324 21, 0, 0),
2325 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_14, "gout_peric1_top1_ipclk_14",
2326 "dout_peric1_usi18_usi",
2327 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14,
2328 21, 0, 0),
2329 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_15, "gout_peric1_top1_ipclk_15",
2330 "dout_peric1_usi_i2c",
2331 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15,
2332 21, 0, 0),
2333 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_2, "gout_peric1_top1_ipclk_2",
2334 "dout_peric1_usi10_usi",
2335 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_2,
2336 21, 0, 0),
2337 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_3, "gout_peric1_top1_ipclk_3",
2338 "dout_peric1_usi_i2c",
2339 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_3,
2340 21, 0, 0),
2341 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_4, "gout_peric1_top1_ipclk_4",
2342 "dout_peric1_usi11_usi",
2343 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4,
2344 21, 0, 0),
2345 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_5, "gout_peric1_top1_ipclk_5",
2346 "dout_peric1_usi_i2c",
2347 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5,
2348 21, 0, 0),
2349 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_6, "gout_peric1_top1_ipclk_6",
2350 "dout_peric1_usi16_usi",
2351 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6,
2352 21, 0, 0),
2353 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_7, "gout_peric1_top1_ipclk_7",
2354 "dout_peric1_usi_i2c",
2355 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7,
2356 21, 0, 0),
2357 GATE(CLK_GOUT_PERIC1_TOP1_IPCLK_9, "gout_peric1_top1_ipclk_9",
2358 "dout_peric1_usi17_usi",
2359 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9,
2360 21, 0, 0),
2361 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_0, "gout_peric1_top1_pclk_0",
2362 "mout_peric1_bus_user",
2363 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_0,
2364 21, 0, 0),
2365 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_1, "gout_peric1_top1_pclk_1",
2366 "mout_peric1_bus_user",
2367 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_1,
2368 21, 0, 0),
2369 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_10, "gout_peric1_top1_pclk_10",
2370 "dout_peric1_bus_user",
2371 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10,
2372 21, 0, 0),
2373 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_12, "gout_peric1_top1_pclk_12",
2374 "dout_peric1_bus_user",
2375 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12,
2376 21, 0, 0),
2377 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_13, "gout_peric1_top1_pclk_13",
2378 "mout_peric1_bus_user",
2379 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13,
2380 21, 0, 0),
2381 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_14, "gout_peric1_top1_pclk_14",
2382 "mout_peric1_bus_user",
2383 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14,
2384 21, 0, 0),
2385 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_15, "gout_peric1_top1_pclk_15",
2386 "mout_peric1_bus_user",
2387 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15,
2388 21, 0, 0),
2389 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_2, "gout_peric1_top1_pclk_2",
2390 "mout_peric1_bus_user",
2391 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_2,
2392 21, 0, 0),
2393 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_3, "gout_peric1_top1_pclk_3",
2394 "mout_peric1_bus_user",
2395 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_3,
2396 21, 0, 0),
2397 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_4, "gout_peric1_top1_pclk_4",
2398 "mout_peric1_bus_user",
2399 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4,
2400 21, 0, 0),
2401 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_5, "gout_peric1_top1_pclk_5",
2402 "mout_peric1_bus_user",
2403 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5,
2404 21, 0, 0),
2405 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_6, "gout_peric1_top1_pclk_6",
2406 "mout_peric1_bus_user",
2407 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6,
2408 21, 0, 0),
2409 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_7, "gout_peric1_top1_pclk_7",
2410 "mout_peric1_bus_user",
2411 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7,
2412 21, 0, 0),
2413 GATE(CLK_GOUT_PERIC1_TOP1_PCLK_9, "gout_peric1_top1_pclk_9",
2414 "dout_peric1_bus_user",
2415 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9,
2416 21, 0, 0),
2417 GATE(CLK_GOUT_PERIC1_BUSP_CLK, "gout_peric1_busp_clk",
2418 "mout_peric1_bus_user",
2419 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
2420 21, 0, 0),
2421 GATE(CLK_GOUT_PERIC1_OSCCLK_CLK, "gout_peric1_oscclk_clk",
2422 "oscclk",
2423 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
2424 21, 0, 0),
2425 GATE(CLK_GOUT_PERIC1_USI06_USI_CLK, "gout_peric1_usi06_usi_clk",
2426 "dout_peric1_usi06_usi",
2427 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
2428 21, 0, 0),
2429 GATE(CLK_GOUT_PERIC1_USI07_USI_CLK, "gout_peric1_usi07_usi_clk",
2430 "dout_peric1_usi07_usi",
2431 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
2432 21, 0, 0),
2433 GATE(CLK_GOUT_PERIC1_USI08_USI_CLK, "gout_peric1_usi08_usi_clk",
2434 "dout_peric1_usi08_usi",
2435 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
2436 21, 0, 0),
2437 GATE(CLK_GOUT_PERIC1_USI09_USI_CLK, "gout_peric1_usi09_usi_clk",
2438 "dout_peric1_usi09_usi",
2439 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
2440 21, 0, 0),
2441 GATE(CLK_GOUT_PERIC1_USI10_USI_CLK, "gout_peric1_usi10_usi_clk",
2442 "dout_peric1_usi10_usi",
2443 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
2444 21, 0, 0),
2445 GATE(CLK_GOUT_PERIC1_USI11_USI_CLK, "gout_peric1_usi11_usi_clk",
2446 "dout_peric1_usi11_usi",
2447 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
2448 21, 0, 0),
2449 GATE(CLK_GOUT_PERIC1_USI16_USI_CLK, "gout_peric1_usi16_usi_clk",
2450 "dout_peric1_usi16_usi",
2451 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
2452 21, 0, 0),
2453 GATE(CLK_GOUT_PERIC1_USI17_USI_CLK, "gout_peric1_usi17_usi_clk",
2454 "dout_peric1_usi17_usi",
2455 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
2456 21, 0, 0),
2457 GATE(CLK_GOUT_PERIC1_USI_I2C_CLK, "gout_peric1_usi_i2c_clk",
2458 "dout_peric1_usi_i2c",
2459 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
2460 21, 0, 0),
2461 GATE(CLK_GOUT_PERIC1_SYSREG_PCLK, "gout_peric1_sysreg_pclk",
2462 "mout_peric1_bus_user",
2463 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
2464 21, 0, 0),
2465 GATE(CLK_GOUT_PERIC1_USI16_I3C_PCLK, "gout_peric1_usi16_i3c_pclk",
2466 "mout_peric1_bus_user",
2467 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
2468 21, 0, 0),
2469 GATE(CLK_GOUT_PERIC1_USI16_I3C_SCLK, "gout_peric1_usi16_i3c_sclk",
2470 "dout_peric1_usi_i2c",
2471 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
2472 21, 0, 0),
2473 GATE(CLK_GOUT_PERIC1_USI17_I3C_PCLK, "gout_peric1_usi17_i3c_pclk",
2474 "dout_peric1_bus_user",
2475 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK,
2476 21, 0, 0),
2477 GATE(CLK_GOUT_PERIC1_USI17_I3C_SCLK, "gout_peric1_usi17_i3c_sclk",
2478 "dout_peric1_usi_i2c",
2479 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK,
2480 21, 0, 0),
2481 GATE(CLK_GOUT_PERIC1_XIU_P_ACLK, "gout_peric1_xiu_p_aclk",
2482 "mout_peric1_bus_user",
2483 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
2484 21, CLK_IGNORE_UNUSED, 0),
2485 };
2486
2487 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
2488 .mux_clks = peric1_mux_clks,
2489 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
2490 .div_clks = peric1_div_clks,
2491 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
2492 .gate_clks = peric1_gate_clks,
2493 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
2494 .nr_clk_ids = CLKS_NR_PERIC1,
2495 .clk_regs = peric1_clk_regs,
2496 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
2497 .clk_name = "bus",
2498 };
2499
2500 /* ---- CMU_PERIS ----------------------------------------------------------- */
2501
2502 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2503 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
2504 #define PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER 0x0604
2505 #define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000
2506 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x203c
2507 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK 0x204c
2508 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2048
2509 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x200c
2510 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x2034
2511 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK 0x2010
2512 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2038
2513 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2014
2514 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2028
2515 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x201c
2516 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2020
2517 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x2024
2518 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2030
2519 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x2018
2520 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2040
2521 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2044
2522 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2000
2523 #define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
2524 #define QCH_CON_D_TZPC_PERIS_QCH 0x3004
2525 #define QCH_CON_GIC_QCH 0x3008
2526 #define QCH_CON_LHM_AXI_P_PERIS_QCH 0x300c
2527 #define QCH_CON_MCT_QCH 0x3010
2528 #define QCH_CON_OTP_CON_BIRA_QCH 0x3014
2529 #define QCH_CON_OTP_CON_TOP_QCH 0x301c
2530 #define QCH_CON_PERIS_CMU_PERIS_QCH 0x3020
2531 #define QCH_CON_SYSREG_PERIS_QCH 0x3024
2532 #define QCH_CON_TMU_SUB_QCH 0x3028
2533 #define QCH_CON_TMU_TOP_QCH 0x302c
2534 #define QCH_CON_WDT_CLUSTER0_QCH 0x3030
2535 #define QCH_CON_WDT_CLUSTER2_QCH 0x3034
2536
2537 static const unsigned long peris_clk_regs[] __initconst = {
2538 PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
2539 PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER,
2540 CLK_CON_MUX_MUX_CLK_PERIS_GIC,
2541 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2542 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
2543 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2544 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
2545 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
2546 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
2547 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
2548 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
2549 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
2550 CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
2551 CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
2552 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
2553 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
2554 CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
2555 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
2556 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
2557 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
2558 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
2559 QCH_CON_D_TZPC_PERIS_QCH,
2560 QCH_CON_GIC_QCH,
2561 QCH_CON_LHM_AXI_P_PERIS_QCH,
2562 QCH_CON_MCT_QCH,
2563 QCH_CON_OTP_CON_BIRA_QCH,
2564 QCH_CON_OTP_CON_TOP_QCH,
2565 QCH_CON_PERIS_CMU_PERIS_QCH,
2566 QCH_CON_SYSREG_PERIS_QCH,
2567 QCH_CON_TMU_SUB_QCH,
2568 QCH_CON_TMU_TOP_QCH,
2569 QCH_CON_WDT_CLUSTER0_QCH,
2570 QCH_CON_WDT_CLUSTER2_QCH,
2571 };
2572
2573 /* Parent clock list for CMU_PERIS muxes */
2574 PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" };
2575 PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" };
2576
2577 static const struct samsung_mux_clock peris_mux_clks[] __initconst = {
2578 MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",
2579 mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,
2580 4, 1),
2581 MUX(CLK_MOUT_PERIS_CLK_PERIS_GIC, "mout_peris_clk_peris_gic",
2582 mout_peris_clk_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC,
2583 4, 1),
2584 };
2585
2586 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
2587 GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK,
2588 "gout_peris_sysreg_peris_pclk", "mout_peris_bus_user",
2589 CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
2590 21, 0, 0),
2591 GATE(CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK,
2592 "gout_peris_wdt_cluster2_pclk", "mout_peris_bus_user",
2593 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
2594 21, 0, 0),
2595 GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK,
2596 "gout_peris_wdt_cluster0_pclk", "mout_peris_bus_user",
2597 CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2598 21, 0, 0),
2599 GATE(CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK,
2600 "clk_peris_peris_cmu_peris_pclk", "mout_peris_bus_user",
2601 CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
2602 21, CLK_IGNORE_UNUSED, 0),
2603 GATE(CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK,
2604 "gout_peris_clk_peris_busp_clk", "mout_peris_bus_user",
2605 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
2606 21, 0, 0),
2607 GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK,
2608 "gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user",
2609 CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
2610 21, 0, 0),
2611 GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK,
2612 "gout_peris_clk_peris_gic_clk", "mout_peris_bus_user",
2613 CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
2614 21, 0, 0),
2615 GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM,
2616 "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user",
2617 CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
2618 21, CLK_IGNORE_UNUSED, 0),
2619 GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK,
2620 "gout_peris_otp_con_bira_pclk", "mout_peris_bus_user",
2621 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
2622 21, 0, 0),
2623 GATE(CLK_GOUT_PERIS_GIC_CLK,
2624 "gout_peris_gic_clk", "mout_peris_bus_user",
2625 CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
2626 21, CLK_IS_CRITICAL, 0),
2627 GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK,
2628 "gout_peris_lhm_axi_p_peris_clk", "oscclk",
2629 CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
2630 21, CLK_IGNORE_UNUSED, 0),
2631 GATE(CLK_GOUT_PERIS_MCT_PCLK,
2632 "gout_peris_mct_pclk", "mout_peris_clk_peris_gic",
2633 CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
2634 21, 0, 0),
2635 GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK,
2636 "gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic",
2637 CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
2638 21, 0, 0),
2639 GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK,
2640 "gout_peris_d_tzpc_peris_pclk", "mout_peris_bus_user",
2641 CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
2642 21, 0, 0),
2643 GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK,
2644 "gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic",
2645 CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
2646 21, 0, 0),
2647 GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK,
2648 "gout_peris_otp_con_bira_oscclk", "oscclk",
2649 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
2650 21, 0, 0),
2651 GATE(CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK,
2652 "gout_peris_otp_con_top_oscclk", "oscclk",
2653 CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
2654 21, 0, 0),
2655 };
2656
2657 static const struct samsung_cmu_info peris_cmu_info __initconst = {
2658 .mux_clks = peris_mux_clks,
2659 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
2660 .gate_clks = peris_gate_clks,
2661 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
2662 .nr_clk_ids = CLKS_NR_PERIS,
2663 .clk_regs = peris_clk_regs,
2664 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
2665 };
2666
exynos990_cmu_peris_init(struct device_node * np)2667 static void __init exynos990_cmu_peris_init(struct device_node *np)
2668 {
2669 exynos_arm64_register_cmu(NULL, np, &peris_cmu_info);
2670 }
2671
2672 /* Register CMU_PERIS early, as it's a dependency for the MCT. */
2673 CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris",
2674 exynos990_cmu_peris_init);
2675
2676 /* ----- platform_driver ----- */
2677
exynos990_cmu_probe(struct platform_device * pdev)2678 static int __init exynos990_cmu_probe(struct platform_device *pdev)
2679 {
2680 const struct samsung_cmu_info *info;
2681 struct device *dev = &pdev->dev;
2682
2683 info = of_device_get_match_data(dev);
2684 exynos_arm64_register_cmu(dev, dev->of_node, info);
2685
2686 return 0;
2687 }
2688
2689 static const struct of_device_id exynos990_cmu_of_match[] = {
2690 {
2691 .compatible = "samsung,exynos990-cmu-hsi0",
2692 .data = &hsi0_cmu_info,
2693 }, {
2694 .compatible = "samsung,exynos990-cmu-peric0",
2695 .data = &peric0_cmu_info,
2696 }, {
2697 .compatible = "samsung,exynos990-cmu-peric1",
2698 .data = &peric1_cmu_info,
2699 },
2700 { },
2701 };
2702
2703 static struct platform_driver exynos990_cmu_driver __refdata = {
2704 .driver = {
2705 .name = "exynos990-cmu",
2706 .of_match_table = exynos990_cmu_of_match,
2707 .suppress_bind_attrs = true,
2708 },
2709 .probe = exynos990_cmu_probe,
2710 };
2711
exynos990_cmu_init(void)2712 static int __init exynos990_cmu_init(void)
2713 {
2714 return platform_driver_register(&exynos990_cmu_driver);
2715 }
2716
2717 core_initcall(exynos990_cmu_init);
2718