1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 bool have_cap_arm_mte;
19
20 enum ftr_type {
21 FTR_EXACT, /* Use a predefined safe value */
22 FTR_LOWER_SAFE, /* Smaller value is safe */
23 FTR_HIGHER_SAFE, /* Bigger value is safe */
24 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
25 FTR_END, /* Mark the last ftr bits */
26 };
27
28 #define FTR_SIGNED true /* Value should be treated as signed */
29 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
30
31 struct reg_ftr_bits {
32 char *name;
33 bool sign;
34 enum ftr_type type;
35 uint8_t shift;
36 uint64_t mask;
37 /*
38 * For FTR_EXACT, safe_val is used as the exact safe value.
39 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
40 */
41 int64_t safe_val;
42 };
43
44 struct test_feature_reg {
45 uint32_t reg;
46 const struct reg_ftr_bits *ftr_bits;
47 };
48
49 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
50 { \
51 .name = #NAME, \
52 .sign = SIGNED, \
53 .type = TYPE, \
54 .shift = SHIFT, \
55 .mask = MASK, \
56 .safe_val = SAFE_VAL, \
57 }
58
59 #define REG_FTR_BITS(type, reg, field, safe_val) \
60 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
61 reg##_##field##_MASK, safe_val)
62
63 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
64 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
65 reg##_##field##_MASK, safe_val)
66
67 #define REG_FTR_END \
68 { \
69 .type = FTR_END, \
70 }
71
72 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
75 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
76 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
77 REG_FTR_END,
78 };
79
80 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
81 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
82 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
83 REG_FTR_END,
84 };
85
86 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
100 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
101 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
102 REG_FTR_END,
103 };
104
105 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
116 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
117 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
118 REG_FTR_END,
119 };
120
121 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
123 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
124 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
125 REG_FTR_END,
126 };
127
128 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
131 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
133 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1),
136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1),
137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1),
138 REG_FTR_END,
139 };
140
141 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
143 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
144 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
145 REG_FTR_END,
146 };
147
148 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
149 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
150 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
151 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1),
152 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1),
153 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1),
154 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
155 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
157 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
158 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
159 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
160 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
161 REG_FTR_END,
162 };
163
164 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
168 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
169 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
170 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
173 REG_FTR_END,
174 };
175
176 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
182 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
183 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
184 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
187 REG_FTR_END,
188 };
189
190 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
195 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
196 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
197 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
198 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
199 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
200 REG_FTR_END,
201 };
202
203 #define TEST_REG(id, table) \
204 { \
205 .reg = id, \
206 .ftr_bits = &((table)[0]), \
207 }
208
209 static struct test_feature_reg test_regs[] = {
210 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
211 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
212 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
213 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
214 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
215 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
216 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
217 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
218 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
219 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
220 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
221 };
222
223 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
224
guest_code(void)225 static void guest_code(void)
226 {
227 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
228 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
229 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
230 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
231 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
232 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
233 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
234 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
235 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
236 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
237 GUEST_REG_SYNC(SYS_CTR_EL0);
238 GUEST_REG_SYNC(SYS_MIDR_EL1);
239 GUEST_REG_SYNC(SYS_REVIDR_EL1);
240 GUEST_REG_SYNC(SYS_AIDR_EL1);
241
242 GUEST_DONE();
243 }
244
245 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)246 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
247 {
248 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
249
250 if (ftr_bits->sign == FTR_UNSIGNED) {
251 switch (ftr_bits->type) {
252 case FTR_EXACT:
253 ftr = ftr_bits->safe_val;
254 break;
255 case FTR_LOWER_SAFE:
256 if (ftr > ftr_bits->safe_val)
257 ftr--;
258 break;
259 case FTR_HIGHER_SAFE:
260 if (ftr < ftr_max)
261 ftr++;
262 break;
263 case FTR_HIGHER_OR_ZERO_SAFE:
264 if (ftr == ftr_max)
265 ftr = 0;
266 else if (ftr != 0)
267 ftr++;
268 break;
269 default:
270 break;
271 }
272 } else if (ftr != ftr_max) {
273 switch (ftr_bits->type) {
274 case FTR_EXACT:
275 ftr = ftr_bits->safe_val;
276 break;
277 case FTR_LOWER_SAFE:
278 if (ftr > ftr_bits->safe_val)
279 ftr--;
280 break;
281 case FTR_HIGHER_SAFE:
282 if (ftr < ftr_max - 1)
283 ftr++;
284 break;
285 case FTR_HIGHER_OR_ZERO_SAFE:
286 if (ftr != 0 && ftr != ftr_max - 1)
287 ftr++;
288 break;
289 default:
290 break;
291 }
292 }
293
294 return ftr;
295 }
296
297 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)298 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
299 {
300 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
301
302 if (ftr_bits->sign == FTR_UNSIGNED) {
303 switch (ftr_bits->type) {
304 case FTR_EXACT:
305 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
306 break;
307 case FTR_LOWER_SAFE:
308 ftr++;
309 break;
310 case FTR_HIGHER_SAFE:
311 ftr--;
312 break;
313 case FTR_HIGHER_OR_ZERO_SAFE:
314 if (ftr == 0)
315 ftr = ftr_max;
316 else
317 ftr--;
318 break;
319 default:
320 break;
321 }
322 } else if (ftr != ftr_max) {
323 switch (ftr_bits->type) {
324 case FTR_EXACT:
325 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
326 break;
327 case FTR_LOWER_SAFE:
328 ftr++;
329 break;
330 case FTR_HIGHER_SAFE:
331 ftr--;
332 break;
333 case FTR_HIGHER_OR_ZERO_SAFE:
334 if (ftr == 0)
335 ftr = ftr_max - 1;
336 else
337 ftr--;
338 break;
339 default:
340 break;
341 }
342 } else {
343 ftr = 0;
344 }
345
346 return ftr;
347 }
348
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)349 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
350 const struct reg_ftr_bits *ftr_bits)
351 {
352 uint8_t shift = ftr_bits->shift;
353 uint64_t mask = ftr_bits->mask;
354 uint64_t val, new_val, ftr;
355
356 val = vcpu_get_reg(vcpu, reg);
357 ftr = (val & mask) >> shift;
358
359 ftr = get_safe_value(ftr_bits, ftr);
360
361 ftr <<= shift;
362 val &= ~mask;
363 val |= ftr;
364
365 vcpu_set_reg(vcpu, reg, val);
366 new_val = vcpu_get_reg(vcpu, reg);
367 TEST_ASSERT_EQ(new_val, val);
368
369 return new_val;
370 }
371
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)372 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
373 const struct reg_ftr_bits *ftr_bits)
374 {
375 uint8_t shift = ftr_bits->shift;
376 uint64_t mask = ftr_bits->mask;
377 uint64_t val, old_val, ftr;
378 int r;
379
380 val = vcpu_get_reg(vcpu, reg);
381 ftr = (val & mask) >> shift;
382
383 ftr = get_invalid_value(ftr_bits, ftr);
384
385 old_val = val;
386 ftr <<= shift;
387 val &= ~mask;
388 val |= ftr;
389
390 r = __vcpu_set_reg(vcpu, reg, val);
391 TEST_ASSERT(r < 0 && errno == EINVAL,
392 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
393
394 val = vcpu_get_reg(vcpu, reg);
395 TEST_ASSERT_EQ(val, old_val);
396 }
397
398 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
399
400 #define encoding_to_range_idx(encoding) \
401 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
402 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
403 sys_reg_Op2(encoding))
404
405
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)406 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
407 {
408 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
409 struct reg_mask_range range = {
410 .addr = (__u64)masks,
411 };
412 int ret;
413
414 /* KVM should return error when reserved field is not zero */
415 range.reserved[0] = 1;
416 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
417 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
418
419 /* Get writable masks for feature ID registers */
420 memset(range.reserved, 0, sizeof(range.reserved));
421 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
422
423 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
424 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
425 uint32_t reg_id = test_regs[i].reg;
426 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
427 int idx;
428
429 /* Get the index to masks array for the idreg */
430 idx = encoding_to_range_idx(reg_id);
431
432 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
433 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
434 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
435 ksft_test_result_skip("%s on AARCH64 only system\n",
436 ftr_bits[j].name);
437 continue;
438 }
439
440 /* Make sure the feature field is writable */
441 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
442
443 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
444
445 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
446 &ftr_bits[j]);
447
448 ksft_test_result_pass("%s\n", ftr_bits[j].name);
449 }
450 }
451 }
452
453 #define MPAM_IDREG_TEST 6
test_user_set_mpam_reg(struct kvm_vcpu * vcpu)454 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
455 {
456 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
457 struct reg_mask_range range = {
458 .addr = (__u64)masks,
459 };
460 uint64_t val;
461 int idx, err;
462
463 /*
464 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero,
465 * check that if it can be set to 1, (i.e. it is supported by the
466 * hardware), that it can't be set to other values.
467 */
468
469 /* Get writable masks for feature ID registers */
470 memset(range.reserved, 0, sizeof(range.reserved));
471 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
472
473 /* Writeable? Nothing to test! */
474 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1);
475 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) {
476 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n");
477 return;
478 }
479
480 /* Get the id register value */
481 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
482
483 /* Try to set MPAM=0. This should always be possible. */
484 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
485 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0);
486 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
487 if (err)
488 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n");
489 else
490 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n");
491
492 /* Try to set MPAM=1 */
493 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
494 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1);
495 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
496 if (err)
497 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n");
498 else
499 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n");
500
501 /* Try to set MPAM=2 */
502 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
503 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2);
504 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
505 if (err)
506 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n");
507 else
508 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n");
509
510 /* And again for ID_AA64PFR1_EL1.MPAM_frac */
511 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
512 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) {
513 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n");
514 return;
515 }
516
517 /* Get the id register value */
518 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
519
520 /* Try to set MPAM_frac=0. This should always be possible. */
521 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
522 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0);
523 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
524 if (err)
525 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n");
526 else
527 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n");
528
529 /* Try to set MPAM_frac=1 */
530 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
531 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1);
532 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
533 if (err)
534 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n");
535 else
536 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n");
537
538 /* Try to set MPAM_frac=2 */
539 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
540 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2);
541 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
542 if (err)
543 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n");
544 else
545 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n");
546 }
547
548 #define MTE_IDREG_TEST 1
test_user_set_mte_reg(struct kvm_vcpu * vcpu)549 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu)
550 {
551 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
552 struct reg_mask_range range = {
553 .addr = (__u64)masks,
554 };
555 uint64_t val;
556 uint64_t mte;
557 uint64_t mte_frac;
558 int idx, err;
559
560 if (!have_cap_arm_mte) {
561 ksft_test_result_skip("MTE capability not supported, nothing to test\n");
562 return;
563 }
564
565 /* Get writable masks for feature ID registers */
566 memset(range.reserved, 0, sizeof(range.reserved));
567 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
568
569 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
570 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) {
571 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n");
572 return;
573 }
574
575 /*
576 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2)
577 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported
578 * and MTE_frac == 0 indicates it is supported.
579 *
580 * As MTE_frac was previously unconditionally read as 0, check
581 * that the set to 0 succeeds but does not change MTE_frac
582 * from unsupported (0xF) to supported (0).
583 *
584 */
585 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
586
587 mte = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), val);
588 mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val);
589 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 ||
590 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) {
591 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n");
592 return;
593 }
594
595 /* Try to set MTE_frac=0. */
596 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK;
597 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0);
598 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
599 if (err) {
600 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n");
601 return;
602 }
603
604 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
605 mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val);
606 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI)
607 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n");
608 else
609 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n");
610 }
611
test_guest_reg_read(struct kvm_vcpu * vcpu)612 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
613 {
614 bool done = false;
615 struct ucall uc;
616
617 while (!done) {
618 vcpu_run(vcpu);
619
620 switch (get_ucall(vcpu, &uc)) {
621 case UCALL_ABORT:
622 REPORT_GUEST_ASSERT(uc);
623 break;
624 case UCALL_SYNC:
625 /* Make sure the written values are seen by guest */
626 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
627 uc.args[3]);
628 break;
629 case UCALL_DONE:
630 done = true;
631 break;
632 default:
633 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
634 }
635 }
636 }
637
638 /* Politely lifted from arch/arm64/include/asm/cache.h */
639 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
640 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
641 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
642 #define CLIDR_CTYPE(clidr, level) \
643 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
644
test_clidr(struct kvm_vcpu * vcpu)645 static void test_clidr(struct kvm_vcpu *vcpu)
646 {
647 uint64_t clidr;
648 int level;
649
650 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
651
652 /* find the first empty level in the cache hierarchy */
653 for (level = 1; level < 7; level++) {
654 if (!CLIDR_CTYPE(clidr, level))
655 break;
656 }
657
658 /*
659 * If you have a mind-boggling 7 levels of cache, congratulations, you
660 * get to fix this.
661 */
662 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
663
664 /* stick in a unified cache level */
665 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
666
667 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
668 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
669 }
670
test_ctr(struct kvm_vcpu * vcpu)671 static void test_ctr(struct kvm_vcpu *vcpu)
672 {
673 u64 ctr;
674
675 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
676 ctr &= ~CTR_EL0_DIC_MASK;
677 if (ctr & CTR_EL0_IminLine_MASK)
678 ctr--;
679
680 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
681 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
682 }
683
test_id_reg(struct kvm_vcpu * vcpu,u32 id)684 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id)
685 {
686 u64 val;
687
688 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id));
689 val++;
690 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val);
691 test_reg_vals[encoding_to_range_idx(id)] = val;
692 }
693
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)694 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
695 {
696 test_clidr(vcpu);
697 test_ctr(vcpu);
698
699 test_id_reg(vcpu, SYS_MPIDR_EL1);
700 ksft_test_result_pass("%s\n", __func__);
701 }
702
test_vcpu_non_ftr_id_regs(struct kvm_vcpu * vcpu)703 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu)
704 {
705 test_id_reg(vcpu, SYS_MIDR_EL1);
706 test_id_reg(vcpu, SYS_REVIDR_EL1);
707 test_id_reg(vcpu, SYS_AIDR_EL1);
708
709 ksft_test_result_pass("%s\n", __func__);
710 }
711
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)712 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
713 {
714 size_t idx = encoding_to_range_idx(encoding);
715 uint64_t observed;
716
717 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
718 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
719 }
720
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)721 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
722 {
723 /*
724 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
725 * architectural reset of the vCPU.
726 */
727 aarch64_vcpu_setup(vcpu, NULL);
728
729 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
730 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
731
732 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
733 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
734 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
735 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1);
736 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1);
737 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1);
738
739 ksft_test_result_pass("%s\n", __func__);
740 }
741
kvm_arch_vm_post_create(struct kvm_vm * vm)742 void kvm_arch_vm_post_create(struct kvm_vm *vm)
743 {
744 if (vm_check_cap(vm, KVM_CAP_ARM_MTE)) {
745 vm_enable_cap(vm, KVM_CAP_ARM_MTE, 0);
746 have_cap_arm_mte = true;
747 }
748 }
749
main(void)750 int main(void)
751 {
752 struct kvm_vcpu *vcpu;
753 struct kvm_vm *vm;
754 bool aarch64_only;
755 uint64_t val, el0;
756 int test_cnt;
757
758 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
759 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS));
760
761 vm = vm_create(1);
762 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0);
763 vcpu = vm_vcpu_add(vm, 0, guest_code);
764
765 /* Check for AARCH64 only system */
766 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
767 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
768 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
769
770 ksft_print_header();
771
772 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
773 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
774 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
775 ARRAY_SIZE(ftr_id_aa64pfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
776 ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
777 ARRAY_SIZE(ftr_id_aa64zfr0_el1) - ARRAY_SIZE(test_regs) + 3 +
778 MPAM_IDREG_TEST + MTE_IDREG_TEST;
779
780 ksft_set_plan(test_cnt);
781
782 test_vm_ftr_id_regs(vcpu, aarch64_only);
783 test_vcpu_ftr_id_regs(vcpu);
784 test_vcpu_non_ftr_id_regs(vcpu);
785 test_user_set_mpam_reg(vcpu);
786 test_user_set_mte_reg(vcpu);
787
788 test_guest_reg_read(vcpu);
789
790 test_reset_preserves_id_regs(vcpu);
791
792 kvm_vm_free(vm);
793
794 ksft_finished();
795 }
796