1 #ifndef __ETH_CONSTANTS_H_ 2 #define __ETH_CONSTANTS_H_ 3 4 /* eth hsi version */ 5 #define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2) 6 7 8 /* Ethernet Ring parameters */ 9 #define X_ETH_LOCAL_RING_SIZE 13 10 #define FIRST_BD_IN_PKT 0 11 #define PARSE_BD_INDEX 1 12 #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) 13 #define U_ETH_NUM_OF_SGES_TO_FETCH 8 14 #define U_ETH_MAX_SGES_FOR_PACKET 3 15 16 /* Rx ring params */ 17 #define U_ETH_LOCAL_BD_RING_SIZE 8 18 #define U_ETH_LOCAL_SGE_RING_SIZE 10 19 #define U_ETH_SGL_SIZE 8 20 /* The fw will padd the buffer with this value, so the IP header will be align to 4 Byte */ 21 #define IP_HEADER_ALIGNMENT_PADDING 2 22 23 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) 24 25 #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) 26 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) 27 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) 28 29 #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) 30 #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) 31 #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) 32 33 //tpa constants 34 #define U_ETH_UNDEFINED_Q 0xFF 35 36 #define T_ETH_INDIRECTION_TABLE_SIZE 128 37 #define T_ETH_RSS_KEY 10 38 #define ETH_NUM_OF_RSS_ENGINES_E2 72 39 40 // number of filter rules 41 #define FILTER_RULES_COUNT 16 42 // number of multicast rules 43 #define MULTICAST_RULES_COUNT 16 44 // number of classify rules 45 #define CLASSIFY_RULES_COUNT 16 46 47 /*The CRC32 seed, that is used for the hash(reduction) multicast address */ 48 #define ETH_CRC32_HASH_SEED 0x00000000 49 50 #define ETH_CRC32_HASH_BIT_SIZE (8) 51 #define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1) 52 53 /* Maximal L2 clients supported */ 54 #define ETH_MAX_RX_CLIENTS_E1 18 55 #define ETH_MAX_RX_CLIENTS_E1H 28 56 #define ETH_MAX_RX_CLIENTS_E2 152 57 58 /* Maximal statistics client Ids */ 59 #define MAX_STAT_COUNTER_ID_E1 36 60 #define MAX_STAT_COUNTER_ID_E1H 56 61 #define MAX_STAT_COUNTER_ID_E2 140 62 63 #define MAX_MAC_CREDIT_E1 192 /* Per Chip */ 64 #define MAX_MAC_CREDIT_E1H 256 /* Per Chip */ 65 #define MAX_MAC_CREDIT_E2 272 /* Per Path */ 66 #define MAX_VLAN_CREDIT_E1 0 /* Per Chip */ 67 #define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */ 68 #define MAX_VLAN_CREDIT_E2 272 /* Per Path */ 69 70 71 /* Maximal aggregation queues supported */ 72 #define ETH_MAX_AGGREGATION_QUEUES_E1 32 73 #define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64 74 75 76 //number of multicast bins for approximate match 77 #define ETH_NUM_OF_MCAST_BINS 256 78 #define ETH_NUM_OF_MCAST_ENGINES_E2 72 79 80 //min CQEs 81 #define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3) 82 #define ETH_MIN_RX_CQES_WITH_TPA_E1 (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA) 83 #define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA) 84 85 #define DISABLE_STATISTIC_COUNTER_ID_VALUE 0 86 #endif /*__ETH_CONSTANTS_H_ */ 87 88