1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012-2013 Thomas Skibo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Hardware and register defines for Cadence GEM Gigabit Ethernet 31 * controller such as the one used in Zynq-7000 SoC. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16 35 * and register definitions are in appendix B.18. 36 * 37 * Additional Reference: Zynq UltraScale+ Device Register Reference 38 * (UG1087 v1.7 Feb 8,2019): 39 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html 40 */ 41 42 #ifndef _IF_CGEM_HW_H_ 43 #define _IF_CGEM_HW_H_ 44 45 /* Cadence GEM hardware register definitions. */ 46 #define CGEM_NET_CTRL 0x000 /* Network Control */ 47 #define CGEM_NET_CTRL_FLUSH_DPRAM_PKT (1 << 18) 48 #define CGEM_NET_CTRL_TX_PFC_PRI_PAUSE_FRAME (1 << 17) 49 #define CGEM_NET_CTRL_EN_PFC_PRI_PAUSE_RX (1 << 16) 50 #define CGEM_NET_CTRL_STORE_RX_TSTAMP (1 << 15) 51 #define CGEM_NET_CTRL_TX_ZEROQ_PAUSE_FRAME (1 << 12) 52 #define CGEM_NET_CTRL_TX_PAUSE_FRAME (1 << 11) 53 #define CGEM_NET_CTRL_TX_HALT (1 << 10) 54 #define CGEM_NET_CTRL_START_TX (1 << 9) 55 #define CGEM_NET_CTRL_BACK_PRESSURE (1 << 8) 56 #define CGEM_NET_CTRL_WREN_STAT_REGS (1 << 7) 57 #define CGEM_NET_CTRL_INCR_STAT_REGS (1 << 6) 58 #define CGEM_NET_CTRL_CLR_STAT_REGS (1 << 5) 59 #define CGEM_NET_CTRL_MGMT_PORT_EN (1 << 4) 60 #define CGEM_NET_CTRL_TX_EN (1 << 3) 61 #define CGEM_NET_CTRL_RX_EN (1 << 2) 62 #define CGEM_NET_CTRL_LOOP_LOCAL (1 << 1) 63 64 #define CGEM_NET_CFG 0x004 /* Network Configuration */ 65 #define CGEM_NET_CFG_UNIDIR_EN (1U << 31) 66 #define CGEM_NET_CFG_IGNORE_IPG_RX_ER (1 << 30) 67 #define CGEM_NET_CFG_RX_BAD_PREAMBLE (1 << 29) 68 #define CGEM_NET_CFG_IPG_STRETCH_EN (1 << 28) 69 #define CGEM_NET_CFG_SGMII_EN (1 << 27) 70 #define CGEM_NET_CFG_IGNORE_RX_FCS (1 << 26) 71 #define CGEM_NET_CFG_RX_HD_WHILE_TX (1 << 25) 72 #define CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN (1 << 24) 73 #define CGEM_NET_CFG_DIS_CP_PAUSE_FRAME (1 << 23) 74 #define CGEM_NET_CFG_DBUS_WIDTH_32 (0 << 21) 75 #define CGEM_NET_CFG_DBUS_WIDTH_64 (1 << 21) 76 #define CGEM_NET_CFG_DBUS_WIDTH_128 (2 << 21) 77 #define CGEM_NET_CFG_DBUS_WIDTH_MASK (3 << 21) 78 #define CGEM_NET_CFG_MDC_CLK_DIV_8 (0 << 18) 79 #define CGEM_NET_CFG_MDC_CLK_DIV_16 (1 << 18) 80 #define CGEM_NET_CFG_MDC_CLK_DIV_32 (2 << 18) 81 #define CGEM_NET_CFG_MDC_CLK_DIV_48 (3 << 18) 82 #define CGEM_NET_CFG_MDC_CLK_DIV_64 (4 << 18) 83 #define CGEM_NET_CFG_MDC_CLK_DIV_96 (5 << 18) 84 #define CGEM_NET_CFG_MDC_CLK_DIV_128 (6 << 18) 85 #define CGEM_NET_CFG_MDC_CLK_DIV_224 (7 << 18) 86 #define CGEM_NET_CFG_MDC_CLK_DIV_MASK (7 << 18) 87 #define CGEM_NET_CFG_FCS_REMOVE (1 << 17) 88 #define CGEM_NET_CFG_LEN_ERR_FRAME_DISC (1 << 16) 89 #define CGEM_NET_CFG_RX_BUF_OFFSET_SHFT 14 90 #define CGEM_NET_CFG_RX_BUF_OFFSET_MASK (3 << 14) 91 #define CGEM_NET_CFG_RX_BUF_OFFSET(n) ((n) << 14) 92 #define CGEM_NET_CFG_PAUSE_EN (1 << 13) 93 #define CGEM_NET_CFG_RETRY_TEST (1 << 12) 94 #define CGEM_NET_CFG_PCS_SEL (1 << 11) 95 #define CGEM_NET_CFG_GIGE_EN (1 << 10) 96 #define CGEM_NET_CFG_EXT_ADDR_MATCH_EN (1 << 9) 97 #define CGEM_NET_CFG_1536RXEN (1 << 8) 98 #define CGEM_NET_CFG_UNI_HASH_EN (1 << 7) 99 #define CGEM_NET_CFG_MULTI_HASH_EN (1 << 6) 100 #define CGEM_NET_CFG_NO_BCAST (1 << 5) 101 #define CGEM_NET_CFG_COPY_ALL (1 << 4) 102 #define CGEM_NET_CFG_DISC_NON_VLAN (1 << 2) 103 #define CGEM_NET_CFG_FULL_DUPLEX (1 << 1) 104 #define CGEM_NET_CFG_SPEED100 (1 << 0) 105 106 #define CGEM_NET_STAT 0x008 /* Network Status */ 107 #define CGEM_NET_STAT_PFC_PRI_PAUSE_NEG (1 << 6) 108 #define CGEM_NET_STAT_PCS_AUTONEG_PAUSE_TX_RES (1 << 5) 109 #define CGEM_NET_STAT_PCS_AUTONEG_PAUSE_RX_RES (1 << 4) 110 #define CGEM_NET_STAT_PCS_AUTONEG_DUP_RES (1 << 3) 111 #define CGEM_NET_STAT_PHY_MGMT_IDLE (1 << 2) 112 #define CGEM_NET_STAT_MDIO_IN_PIN_STATUS (1 << 1) 113 #define CGEM_NET_STAT_PCS_LINK_STATE (1 << 0) 114 115 #define CGEM_USER_IO 0x00C /* User I/O */ 116 117 #define CGEM_DMA_CFG 0x010 /* DMA Config */ 118 #define CGEM_DMA_CFG_ADDR_BUS_64 (1 << 30) 119 #define CGEM_DMA_CFG_DISC_WHEN_NO_AHB (1 << 24) 120 #define CGEM_DMA_CFG_RX_BUF_SIZE_SHIFT 16 121 #define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff << 16) 122 #define CGEM_DMA_CFG_RX_BUF_SIZE(sz) ((((sz) + 63) / 64) << 16) 123 #define CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN (1 << 11) 124 #define CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL (1 << 10) 125 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_1K (0 << 8) 126 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_2K (1 << 8) 127 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_4K (2 << 8) 128 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K (3 << 8) 129 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_MASK (3 << 8) 130 #define CGEM_DMA_CFG_AHB_ENDIAN_SWAP_PKT_EN (1 << 7) 131 #define CGEM_DMA_CFG_AHB_ENDIAN_SWAP_MGMT_EN (1 << 6) 132 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_1 (1 << 0) 133 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_4 (4 << 0) 134 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_8 (8 << 0) 135 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 (16 << 0) 136 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_MASK (0x1f << 0) 137 138 #define CGEM_TX_STAT 0x014 /* Transmit Status */ 139 #define CGEM_TX_STAT_HRESP_NOT_OK (1 << 8) 140 #define CGEM_TX_STAT_LATE_COLL (1 << 7) 141 #define CGEM_TX_STAT_UNDERRUN (1 << 6) 142 #define CGEM_TX_STAT_COMPLETE (1 << 5) 143 #define CGEM_TX_STAT_CORRUPT_AHB_ERR (1 << 4) 144 #define CGEM_TX_STAT_GO (1 << 3) 145 #define CGEM_TX_STAT_RETRY_LIMIT_EXC (1 << 2) 146 #define CGEM_TX_STAT_COLLISION (1 << 1) 147 #define CGEM_TX_STAT_USED_BIT_READ (1 << 0) 148 #define CGEM_TX_STAT_ALL 0x1ff 149 150 #define CGEM_RX_QBAR 0x018 /* Receive Buf Q Base Addr */ 151 #define CGEM_TX_QBAR 0x01C /* Transmit Buf Q Base Addr */ 152 153 #define CGEM_RX_STAT 0x020 /* Receive Status */ 154 #define CGEM_RX_STAT_HRESP_NOT_OK (1 << 3) 155 #define CGEM_RX_STAT_OVERRUN (1 << 2) 156 #define CGEM_RX_STAT_FRAME_RECD (1 << 1) 157 #define CGEM_RX_STAT_BUF_NOT_AVAIL (1 << 0) 158 #define CGEM_RX_STAT_ALL 0xf 159 160 #define CGEM_INTR_STAT 0x024 /* Interrupt Status */ 161 #define CGEM_INTR_EN 0x028 /* Interrupt Enable */ 162 #define CGEM_INTR_DIS 0x02C /* Interrupt Disable */ 163 #define CGEM_INTR_MASK 0x030 /* Interrupt Mask */ 164 #define CGEM_INTR_TSU_SEC_INCR (1 << 26) 165 #define CGEM_INTR_PDELAY_RESP_TX (1 << 25) 166 #define CGEM_INTR_PDELAY_REQ_TX (1 << 24) 167 #define CGEM_INTR_PDELAY_RESP_RX (1 << 23) 168 #define CGEM_INTR_PDELAY_REQ_RX (1 << 22) 169 #define CGEM_INTR_SYNX_TX (1 << 21) 170 #define CGEM_INTR_DELAY_REQ_TX (1 << 20) 171 #define CGEM_INTR_SYNC_RX (1 << 19) 172 #define CGEM_INTR_DELAY_REQ_RX (1 << 18) 173 #define CGEM_INTR_PARTNER_PG_RX (1 << 17) 174 #define CGEM_INTR_AUTONEG_COMPL (1 << 16) 175 #define CGEM_INTR_EXT_INTR (1 << 15) 176 #define CGEM_INTR_PAUSE_TX (1 << 14) 177 #define CGEM_INTR_PAUSE_ZERO (1 << 13) 178 #define CGEM_INTR_PAUSE_NONZEROQ_RX (1 << 12) 179 #define CGEM_INTR_HRESP_NOT_OK (1 << 11) 180 #define CGEM_INTR_RX_OVERRUN (1 << 10) 181 #define CGEM_INTR_LINK_CHNG (1 << 9) 182 #define CGEM_INTR_TX_COMPLETE (1 << 7) 183 #define CGEM_INTR_TX_CORRUPT_AHB_ERR (1 << 6) 184 #define CGEM_INTR_RETRY_EX_LATE_COLLISION (1 << 5) 185 #define CGEM_INTR_TX_USED_READ (1 << 3) 186 #define CGEM_INTR_RX_USED_READ (1 << 2) 187 #define CGEM_INTR_RX_COMPLETE (1 << 1) 188 #define CGEM_INTR_MGMT_SENT (1 << 0) 189 #define CGEM_INTR_ALL 0x7FFFEFF 190 191 #define CGEM_PHY_MAINT 0x034 /* PHY Maintenenace */ 192 #define CGEM_PHY_MAINT_CLAUSE_22 (1 << 30) 193 #define CGEM_PHY_MAINT_OP_SHIFT 28 194 #define CGEM_PHY_MAINT_OP_MASK (3 << 28) 195 #define CGEM_PHY_MAINT_OP_READ (2 << 28) 196 #define CGEM_PHY_MAINT_OP_WRITE (1 << 28) 197 #define CGEM_PHY_MAINT_PHY_ADDR_SHIFT 23 198 #define CGEM_PHY_MAINT_PHY_ADDR_MASK (0x1f << 23) 199 #define CGEM_PHY_MAINT_REG_ADDR_SHIFT 18 200 #define CGEM_PHY_MAINT_REG_ADDR_MASK (0x1f << 18) 201 #define CGEM_PHY_MAINT_MUST_10 (2 << 16) 202 #define CGEM_PHY_MAINT_DATA_MASK 0xffff 203 204 #define CGEM_RX_PAUSEQ 0x038 /* Received Pause Quantum */ 205 #define CGEM_TX_PAUSEQ 0x03C /* Transmit Puase Quantum */ 206 207 #define CGEM_HASH_BOT 0x080 /* Hash Reg Bottom [31:0] */ 208 #define CGEM_HASH_TOP 0x084 /* Hash Reg Top [63:32] */ 209 #define CGEM_SPEC_ADDR_LOW(n) (0x088 + (n) * 8) 210 #define CGEM_SPEC_ADDR_HI(n) (0x08C + (n) * 8) 211 212 #define CGEM_TYPE_ID_MATCH1 0x0A8 /* Type ID Match 1 */ 213 #define CGEM_TYPE_ID_MATCH_COPY_EN (1U << 31) 214 #define CGEM_TYPE_ID_MATCH2 0x0AC /* Type ID Match 2 */ 215 #define CGEM_TYPE_ID_MATCH3 0x0B0 /* Type ID Match 3 */ 216 #define CGEM_TYPE_ID_MATCH4 0x0B4 /* Type ID Match 4 */ 217 218 #define CGEM_WAKE_ON_LAN 0x0B8 /* Wake on LAN Register */ 219 #define CGEM_WOL_MULTI_HASH_EN (1 << 19) 220 #define CGEM_WOL_SPEC_ADDR1_EN (1 << 18) 221 #define CGEM_WOL_ARP_REQ_EN (1 << 17) 222 #define CGEM_WOL_MAGIC_PKT_EN (1 << 16) 223 #define CGEM_WOL_ARP_REQ_IP_ADDR_MASK 0xffff 224 225 #define CGEM_IPG_STRETCH /* IPG Stretch Register */ 226 227 #define CGEM_STACKED_VLAN 0x0C0 /* Stacked VLAN Register */ 228 #define CGEM_STACKED_VLAN_EN (1U << 31) 229 230 #define CGEM_TX_PFC_PAUSE 0x0C4 /* Transmit PFC Pause Reg */ 231 #define CGEM_TX_PFC_PAUSEQ_SEL_SHIFT 8 232 #define CGEM_TX_PFC_PAUSEQ_SEL_MASK (0xff << 8) 233 #define CGEM_TX_PFC_PAUSE_PRI_EN_VEC_VAL_MASK 0xff 234 235 #define CGEM_SPEC_ADDR1_MASK_BOT 0x0C8 /* Specific Addr Mask1 [31:0]*/ 236 #define CGEM_SPEC_ADDR1_MASK_TOP 0x0CC /* Specific Addr Mask1[47:32]*/ 237 #define CGEM_MODULE_ID 0x0FC /* Module ID */ 238 #define CGEM_OCTETS_TX_BOT 0x100 /* Octets xmitted [31:0] */ 239 #define CGEM_OCTETS_TX_TOP 0x104 /* Octets xmitted [47:32] */ 240 #define CGEM_FRAMES_TX 0x108 /* Frames xmitted */ 241 #define CGEM_BCAST_FRAMES_TX 0x10C /* Broadcast Frames xmitted */ 242 #define CGEM_MULTI_FRAMES_TX 0x110 /* Multicast Frames xmitted */ 243 #define CGEM_PAUSE_FRAMES_TX 0x114 /* Pause Frames xmitted */ 244 #define CGEM_FRAMES_64B_TX 0x118 /* 64-Byte Frames xmitted */ 245 #define CGEM_FRAMES_65_127B_TX 0x11C /* 65-127 Byte Frames xmitted*/ 246 #define CGEM_FRAMES_128_255B_TX 0x120 /* 128-255 Byte Frames xmit */ 247 #define CGEM_FRAMES_256_511B_TX 0x124 /* 256-511 Byte Frames xmit */ 248 #define CGEM_FRAMES_512_1023B_TX 0x128 /* 512-1023 Byte frames xmit */ 249 #define CGEM_FRAMES_1024_1518B_TX 0x12C /* 1024-1518 Byte frames xmit*/ 250 #define CGEM_TX_UNDERRUNS 0x134 /* Transmit Under-runs */ 251 #define CGEM_SINGLE_COLL_FRAMES 0x138 /* Single-Collision Frames */ 252 #define CGEM_MULTI_COLL_FRAMES 0x13C /* Multi-Collision Frames */ 253 #define CGEM_EXCESSIVE_COLL_FRAMES 0x140 /* Excessive Collision Frames*/ 254 #define CGEM_LATE_COLL 0x144 /* Late Collisions */ 255 #define CGEM_DEFERRED_TX_FRAMES 0x148 /* Deferred Transmit Frames */ 256 #define CGEM_CARRIER_SENSE_ERRS 0x14C /* Carrier Sense Errors */ 257 #define CGEM_OCTETS_RX_BOT 0x150 /* Octets Received [31:0] */ 258 #define CGEM_OCTETS_RX_TOP 0x154 /* Octets Received [47:32] */ 259 #define CGEM_FRAMES_RX 0x158 /* Frames Received */ 260 #define CGEM_BCAST_FRAMES_RX 0x15C /* Broadcast Frames Received */ 261 #define CGEM_MULTI_FRAMES_RX 0x160 /* Multicast Frames Received */ 262 #define CGEM_PAUSE_FRAMES_RX 0x164 /* Pause Frames Reeived */ 263 #define CGEM_FRAMES_64B_RX 0x168 /* 64-Byte Frames Received */ 264 #define CGEM_FRAMES_65_127B_RX 0x16C /* 65-127 Byte Frames Rx'd */ 265 #define CGEM_FRAMES_128_255B_RX 0x170 /* 128-255 Byte Frames Rx'd */ 266 #define CGEM_FRAMES_256_511B_RX 0x174 /* 256-511 Byte Frames Rx'd */ 267 #define CGEM_FRAMES_512_1023B_RX 0x178 /* 512-1023 Byte Frames Rx'd */ 268 #define CGEM_FRAMES_1024_1518B_RX 0x17C /* 1024-1518 Byte Frames Rx'd*/ 269 #define CGEM_UNDERSZ_RX 0x184 /* Undersize Frames Rx'd */ 270 #define CGEM_OVERSZ_RX 0x188 /* Oversize Frames Rx'd */ 271 #define CGEM_JABBERS_RX 0x18C /* Jabbers received */ 272 #define CGEM_FCS_ERRS 0x190 /* Frame Check Sequence Errs */ 273 #define CGEM_LENGTH_FIELD_ERRS 0x194 /* Length Firled Frame Errs */ 274 #define CGEM_RX_SYMBOL_ERRS 0x198 /* Receive Symbol Errs */ 275 #define CGEM_ALIGN_ERRS 0x19C /* Alignment Errors */ 276 #define CGEM_RX_RESOURCE_ERRS 0x1A0 /* Receive Resoure Errors */ 277 #define CGEM_RX_OVERRUN_ERRS 0x1A4 /* Receive Overrun Errors */ 278 #define CGEM_IP_HDR_CKSUM_ERRS 0x1A8 /* IP Hdr Checksum Errors */ 279 #define CGEM_TCP_CKSUM_ERRS 0x1AC /* TCP Checksum Errors */ 280 #define CGEM_UDP_CKSUM_ERRS 0x1B0 /* UDP Checksum Errors */ 281 #define CGEM_TIMER_STROBE_S 0x1C8 /* 1588 timer sync strobe s */ 282 #define CGEM_TIMER_STROBE_NS 0x1CC /* timer sync strobe ns */ 283 #define CGEM_TIMER_S 0x1D0 /* 1588 timer seconds */ 284 #define CGEM_TIMER_NS 0x1D4 /* 1588 timer ns */ 285 #define CGEM_ADJUST 0x1D8 /* 1588 timer adjust */ 286 #define CGEM_INCR 0x1DC /* 1588 timer increment */ 287 #define CGEM_PTP_TX_S 0x1E0 /* PTP Event Frame xmit secs */ 288 #define CGEM_PTP_TX_NS 0x1E4 /* PTP Event Frame xmit ns */ 289 #define CGEM_PTP_RX_S 0x1E8 /* PTP Event Frame rcv'd s */ 290 #define CGEM_PTP_RX_NS 0x1EC /* PTP Event Frame rcv'd ns */ 291 #define CGEM_PTP_PEER_TX_S 0x1F0 /* PTP Peer Event xmit s */ 292 #define CGEM_PTP_PEER_TX_NS 0x1F4 /* PTP Peer Event xmit ns */ 293 #define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */ 294 #define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */ 295 296 #define CGEM_DESIGN_CFG1 0x280 /* Design Configuration 1 */ 297 #define CGEM_DESIGN_CFG1_AXI_CACHE_WIDTH_MASK (0xfU << 28) 298 #define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_MASK (7 << 25) 299 #define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_32 (1 << 25) 300 #define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_64 (2 << 25) 301 #define CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_128 (4 << 25) 302 #define CGEM_DESIGN_CFG1_IRQ_READ_CLR (1 << 23) 303 #define CGEM_DESIGN_CFG1_NO_SNAPSHOT (1 << 22) 304 #define CGEM_DESIGN_CFG1_NO_STATS (1 << 21) 305 #define CGEM_DESIGN_CFG1_NO_SCAN_PINS (1 << 20) 306 #define CGEM_DESIGN_CFG1_USER_IN_WIDTH_MASK (0x1f << 15) 307 #define CGEM_DESIGN_CFG1_USER_OUT_WIDTH_MASK (0x1f << 10) 308 #define CGEM_DESIGN_CFG1_USER_IO (1 << 9) 309 #define CGEM_DESIGN_CFG1_APB_REV2 (1 << 8) 310 #define CGEM_DESIGN_CFG1_APB_REV1 (1 << 7) 311 #define CGEM_DESIGN_CFG1_EXT_FIFO_INTERFACE (1 << 6) 312 #define CGEM_DESIGN_CFG1_NO_INT_LOOPBACK (1 << 5) 313 #define CGEM_DESIGN_CFG1_INT_LOOPBACK (1 << 4) 314 #define CGEM_DESIGN_CFG1_TDC_50 (1 << 3) 315 #define CGEM_DESIGN_CFG1_RDC_50 (1 << 2) 316 #define CGEM_DESIGN_CFG1_SERDES (1 << 1) 317 #define CGEM_DESIGN_CFG1_NO_PCS (1 << 0) 318 319 #define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */ 320 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_SHIFT 26 321 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf << 26) 322 #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_SHIFT 22 323 #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_MASK (0xf << 22) 324 #define CGEM_DESIGN_CFG2_TX_PKT_BUF (1 << 21) 325 #define CGEM_DESIGN_CFG2_RX_PKT_BUF (1 << 20) 326 #define CGEM_DESIGN_CFG2_HPROT_VAL_SHIFT 16 327 #define CGEM_DESIGN_CFG2_HPROT_VAL_MASK (0xf << 16) 328 #define CGEM_DESIGN_CFG2_JUMBO_MAX_LEN_MASK 0xffff 329 330 #define CGEM_DESIGN_CFG3 0x288 /* Design Configuration 3 */ 331 #define CGEM_DESIGN_CFG3_RX_BASE2_FIFO_SZ_MASK (0xffffU << 16) 332 #define CGEM_DESIGN_CFG3_RX_BASE2_FIFO_SZ_SHIFT 16 333 #define CGEM_DESIGN_CFG3_RX_FIFO_SIZE_MASK 0xffff 334 335 #define CGEM_DESIGN_CFG4 0x28C /* Design Configuration 4 */ 336 #define CGEM_DESIGN_CFG4_TX_BASE2_FIFO_SZ_SHIFT 16 337 #define CGEM_DESIGN_CFG4_TX_BASE2_FIFO_SZ_MASK (0xffffU << 16) 338 #define CGEM_DESIGN_CFG4_TX_FIFO_SIZE_MASK 0xffff 339 340 #define CGEM_DESIGN_CFG5 0x290 /* Design Configuration 5 */ 341 #define CGEM_DESIGN_CFG5_TSU_CLK (1 << 28) 342 #define CGEM_DESIGN_CFG5_RX_BUF_LEN_DEF_SHIFT 20 343 #define CGEM_DESIGN_CFG5_RX_BUF_LEN_DEF_MASK (0xff << 20) 344 #define CGEM_DESIGN_CFG5_TX_PBUF_SIZE_DEF (1 << 19) 345 #define CGEM_DESIGN_CFG5_RX_PBUF_SIZE_DEF_SHIFT 17 346 #define CGEM_DESIGN_CFG5_RX_PBUF_SIZE_DEF_MASK (3 << 17) 347 #define CGEM_DESIGN_CFG5_ENDIAN_SWAP_DEF_SHIFT 15 348 #define CGEM_DESIGN_CFG5_ENDIAN_SWAP_DEF_MASK (3 << 15) 349 #define CGEM_DESIGN_CFG5_MDC_CLOCK_DIV_SHIFT 12 350 #define CGEM_DESIGN_CFG5_MDC_CLOCK_DIV_MASK (7 << 12) 351 #define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_SHIFT 10 352 #define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_MASK (3 << 10) 353 #define CGEM_DESIGN_CFG5_PHY_IDENT (1 << 9) 354 #define CGEM_DESIGN_CFG5_TSU (1 << 8) 355 #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_SHIFT 4 356 #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf << 4) 357 #define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf 358 359 #define CGEM_DESIGN_CFG6 0x294 /* Design Configuration 6 */ 360 #define CGEM_DESIGN_CFG6_ADDR_64B (1 << 23) /* 64-bit addr cap */ 361 #define CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK 0xfffe 362 #define CGEM_DESIGN_CFG6_DMA_PRIO_Q(n) (1 << (n)) 363 364 #define CGEM_TX_QN_BAR(n) (0x440 + ((n) - 1) * 4) 365 #define CGEM_RX_QN_BAR(n) (0x480 + ((n) - 1) * 4) 366 367 #define CGEM_TX_QBAR_HI 0x4C8 368 #define CGEM_RX_QBAR_HI 0x4D4 369 370 /* 371 * Transmit Descriptors: two or four 32-bit words: 372 * word0: address 373 * word1: length and control 374 * word2: address upper 32-bits (64-bit mode) 375 * word3: unused (64-bit mode) 376 */ 377 378 struct cgem_tx_desc { 379 uint32_t addr; 380 uint32_t ctl; 381 #define CGEM_TXDESC_USED (1U << 31) /* done txmitting */ 382 #define CGEM_TXDESC_WRAP (1 << 30) /* end descr ring */ 383 #define CGEM_TXDESC_RETRY_ERR (1 << 29) 384 #define CGEM_TXDESC_AHB_ERR (1 << 27) 385 #define CGEM_TXDESC_LATE_COLL (1 << 26) 386 #define CGEM_TXDESC_CKSUM_GEN_STAT_MASK (7 << 20) 387 #define CGEM_TXDESC_CKSUM_GEN_STAT_VLAN_HDR_ERR (1 << 20) 388 #define CGEM_TXDESC_CKSUM_GEN_STAT_SNAP_HDR_ERR (2 << 20) 389 #define CGEM_TXDESC_CKSUM_GEN_STAT_IP_HDR_ERR (3 << 20) 390 #define CGEM_TXDESC_CKSUM_GEN_STAT_UNKNOWN_TYPE (4 << 20) 391 #define CGEM_TXDESC_CKSUM_GEN_STAT_UNSUPP_FRAG (5 << 20) 392 #define CGEM_TXDESC_CKSUM_GEN_STAT_NOT_TCPUDP (6 << 20) 393 #define CGEM_TXDESC_CKSUM_GEN_STAT_SHORT_PKT (7 << 20) 394 #define CGEM_TXDESC_NO_CRC_APPENDED (1 << 16) 395 #define CGEM_TXDESC_LAST_BUF (1 << 15) /* last in frame */ 396 #define CGEM_TXDESC_LENGTH_MASK 0x3fff 397 #ifdef CGEM64 398 uint32_t addrhi; 399 uint32_t unused; 400 #endif 401 }; 402 403 /* 404 * Receive Descriptors: two or four 32-bit words: 405 * word0: address | WRAP and OWN flags 406 * word1: length and control 407 * word2: address upper 32 bits (64-bit mode) 408 * word3: unused 409 */ 410 411 struct cgem_rx_desc { 412 uint32_t addr; 413 #define CGEM_RXDESC_WRAP (1 << 1) /* goes in addr! */ 414 #define CGEM_RXDESC_OWN (1 << 0) /* buf filled */ 415 uint32_t ctl; 416 #define CGEM_RXDESC_BCAST (1U << 31)/* all 1's bcast */ 417 #define CGEM_RXDESC_MULTI_MATCH (1 << 30) /* mutlicast match */ 418 #define CGEM_RXDESC_UNICAST_MATCH (1 << 29) 419 #define CGEM_RXDESC_EXTERNAL_MATCH (1 << 28) /* ext addr match */ 420 #define CGEM_RXDESC_SPEC_MATCH_SHIFT 25 421 #define CGEM_RXDESC_SPEC_MATCH_MASK (3 << 25) 422 #define CGEM_RXDESC_TYPE_ID_MATCH_SHIFT 22 423 #define CGEM_RXDESC_TYPE_ID_MATCH_MASK (3 << 22) 424 #define CGEM_RXDESC_CKSUM_STAT_MASK (3 << 22) /* same as above */ 425 #define CGEM_RXDESC_CKSUM_STAT_NONE (0 << 22) 426 #define CGEM_RXDESC_CKSUM_STAT_IP_GOOD (1 << 22) 427 #define CGEM_RXDESC_CKSUM_STAT_TCP_GOOD (2 << 22) /* and ip good */ 428 #define CGEM_RXDESC_CKSUM_STAT_UDP_GOOD (3 << 22) /* and ip good */ 429 #define CGEM_RXDESC_VLAN_DETECTED (1 << 21) 430 #define CGEM_RXDESC_PRIO_DETECTED (1 << 20) 431 #define CGEM_RXDESC_VLAN_PRIO_SHIFT 17 432 #define CGEM_RXDESC_VLAN_PRIO_MASK (7 << 17) 433 #define CGEM_RXDESC_CFI (1 << 16) 434 #define CGEM_RXDESC_EOF (1 << 15) /* end of frame */ 435 #define CGEM_RXDESC_SOF (1 << 14) /* start of frame */ 436 #define CGEM_RXDESC_BAD_FCS (1 << 13) 437 #define CGEM_RXDESC_LENGTH_MASK 0x1fff 438 #ifdef CGEM64 439 uint32_t addrhi; 440 uint32_t unused; 441 #endif 442 }; 443 444 #endif /* _IF_CGEM_HW_H_ */ 445