1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 The FreeBSD Foundation 5 * 6 * This software was developed by Landon Fuller under sponsorship from 7 * the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPC_GPIOVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPC_GPIOVAR_H_ 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 41 #include <dev/bhnd/bhnd.h> 42 43 /** 44 * ChipCommon GPIO device quirks. 45 */ 46 enum { 47 /** 48 * No GPIO event support. 49 * 50 * The CHIPC_GPIOEVENT, CHIPC_GPIOEVENT_INTM, and 51 * CHIPC_GPIOEVENT_INTPOLARITY registers are not available. 52 */ 53 CC_GPIO_QUIRK_NO_EVENTS = (1<<0), 54 55 /** 56 * No GPIO duty-cycle timer support. 57 * 58 * The CHIPC_GPIOTIMERVAL and CHIPC_GPIOTIMEROUTMASK registers are not 59 * available. 60 */ 61 CC_GPIO_QUIRK_NO_DCTIMER = (1<<1), 62 63 /** 64 * No GPIO pull-up/pull-down configuration support. 65 * 66 * The CHIPC_GPIOPU and CHIPC_GPIOPD registers are not available. 67 */ 68 CC_GPIO_QUIRK_NO_PULLUPDOWN = (1<<2), 69 70 /** 71 * Do not attach a child gpioc(4) device. 72 * 73 * This is primarily intended for use on bridged Wi-Fi adapters, where 74 * userspace modification of GPIO pin configuration could introduce 75 * significant undesirable behavior. 76 */ 77 CC_GPIO_QUIRK_NO_GPIOC = (1<<3), 78 }; 79 80 /** ChipCommon GPIO pin modes */ 81 typedef enum { 82 CC_GPIO_PIN_INPUT, 83 CC_GPIO_PIN_OUTPUT, 84 CC_GPIO_PIN_TRISTATE 85 } chipc_gpio_pin_mode; 86 87 /** 88 * A single GPIO update register. 89 */ 90 struct chipc_gpio_reg { 91 uint32_t value; /**< register update value */ 92 uint32_t mask; /**< register update mask */ 93 }; 94 95 /** 96 * A GPIO register update descriptor. 97 */ 98 struct chipc_gpio_update { 99 struct chipc_gpio_reg pullup; /**< CHIPC_GPIOPU changes */ 100 struct chipc_gpio_reg pulldown; /**< CHIPC_GPIOPD changes */ 101 struct chipc_gpio_reg out; /**< CHIPC_GPIOOUT changes */ 102 struct chipc_gpio_reg outen; /**< CHIPC_GPIOOUTEN changes */ 103 struct chipc_gpio_reg timeroutmask; /**< CHIPC_GPIOTIMEROUTMASK changes */ 104 struct chipc_gpio_reg ctrl; /**< CHIPC_GPIOCTRL changes */ 105 }; 106 107 #define CC_GPIO_UPDATE(_upd, _pin, _reg, _val) do { \ 108 (_upd)->_reg.mask |= (1 << (_pin)); \ 109 if (_val) \ 110 (_upd)->_reg.value |= (1 << (_pin)); \ 111 else \ 112 (_upd)->_reg.value &= ~(1 << (_pin)); \ 113 } while(0) 114 115 /** 116 * ChipCommon GPIO driver instance state. 117 */ 118 struct chipc_gpio_softc { 119 device_t dev; 120 device_t gpiobus; /**< attached gpiobus child */ 121 struct bhnd_resource *mem_res; /**< chipcommon register block */ 122 int mem_rid; /**< resource ID of mem_res */ 123 uint32_t quirks; /**< device quirks (see CC_GPIO_QUIRK_*) */ 124 struct mtx mtx; /**< lock protecting RMW register access */ 125 }; 126 127 #define CC_GPIO_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 128 device_get_nameunit((sc)->dev), NULL, MTX_DEF) 129 #define CC_GPIO_LOCK(sc) mtx_lock(&(sc)->mtx) 130 #define CC_GPIO_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 131 #define CC_GPIO_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 132 #define CC_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 133 134 #define CC_GPIO_WR4(sc, off, val) \ 135 bhnd_bus_write_4((sc)->mem_res, (off), (val)) 136 #define CC_GPIO_WRFLAG(sc, pin_num, flag, val) \ 137 CC_GPIO_WR4(sc, CHIPC_ ## flag, \ 138 (CC_GPIO_RD4(sc, CHIPC_ ## flag) & ~(1 << pin_num)) | \ 139 (val ? (1 << pin_num) : 0)) 140 141 #define CC_GPIO_RD4(sc, off) \ 142 bhnd_bus_read_4((sc)->mem_res, (off)) 143 #define CC_GPIO_RDFLAG(sc, pin_num, flag) \ 144 ((CC_GPIO_RD4(sc, CHIPC_ ## flag) & (1 << pin_num)) != 0) 145 146 #define CC_GPIO_NPINS 32 147 #define CC_GPIO_VALID_PIN(_pin) \ 148 ((_pin) >= 0 && (_pin) < CC_GPIO_NPINS) 149 #define CC_GPIO_VALID_PINS(_first, _num) \ 150 ((_num) <= CC_GPIO_NPINS && CC_GPIO_NPINS - (_num) >= _first) 151 152 #define CC_GPIO_ASSERT_VALID_PIN(sc, pin_num) \ 153 KASSERT(CC_GPIO_VALID_PIN(pin_num), ("invalid pin# %" PRIu32, pin_num)); 154 155 #define CC_GPIO_QUIRK(_sc, _name) \ 156 ((_sc)->quirks & CC_GPIO_QUIRK_ ## _name) 157 158 #define CC_GPIO_ASSERT_QUIRK(_sc, name) \ 159 KASSERT(CC_GPIO_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 160 161 #endif /* _BHND_PWRCTL_BHND_PWRCTLVAR_H_ */ 162