1 /*- 2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _DEV_XDMA_CONTROLLER_PL330_H_ 32 #define _DEV_XDMA_CONTROLLER_PL330_H_ 33 34 /* pl330 registers */ 35 #define DSR 0x000 /* DMA Manager Status */ 36 #define DPC 0x004 /* DMA Program Counter */ 37 #define INTEN 0x020 /* Interrupt Enable */ 38 #define INT_EVENT_RIS 0x024 /* Event-Interrupt Raw Status */ 39 #define INTMIS 0x028 /* Interrupt Status */ 40 #define INTCLR 0x02C /* Interrupt Clear */ 41 #define FSRD 0x030 /* Fault Status DMA Manager */ 42 #define FSRC 0x034 /* Fault Status DMA Channel */ 43 #define FTRD 0x038 /* Fault Type DMA Manager */ 44 #define FTR(n) (0x040 + 0x04 * (n)) /* Fault type for DMA channel n */ 45 #define CSR(n) (0x100 + 0x08 * (n)) /* Channel status for DMA channel n */ 46 #define CPC(n) (0x104 + 0x08 * (n)) /* Channel PC for DMA channel n */ 47 #define SAR(n) (0x400 + 0x20 * (n)) /* Source address for DMA channel n */ 48 #define DAR(n) (0x404 + 0x20 * (n)) /* Destination address for DMA channel n */ 49 #define CCR(n) (0x408 + 0x20 * (n)) /* Channel control for DMA channel n */ 50 #define CCR_DST_BURST_SIZE_S 15 51 #define CCR_DST_BURST_SIZE_1 (0 << CCR_DST_BURST_SIZE_S) 52 #define CCR_DST_BURST_SIZE_2 (1 << CCR_DST_BURST_SIZE_S) 53 #define CCR_DST_BURST_SIZE_4 (2 << CCR_DST_BURST_SIZE_S) 54 #define CCR_SRC_BURST_SIZE_S 1 55 #define CCR_SRC_BURST_SIZE_1 (0 << CCR_SRC_BURST_SIZE_S) 56 #define CCR_SRC_BURST_SIZE_2 (1 << CCR_SRC_BURST_SIZE_S) 57 #define CCR_SRC_BURST_SIZE_4 (2 << CCR_SRC_BURST_SIZE_S) 58 #define CCR_DST_INC (1 << 14) 59 #define CCR_SRC_INC (1 << 0) 60 #define CCR_DST_PROT_CTRL_S 22 61 #define CCR_DST_PROT_PRIV (1 << CCR_DST_PROT_CTRL_S) 62 #define LC0(n) (0x40C + 0x20 * (n)) /* Loop counter 0 for DMA channel n */ 63 #define LC1(n) (0x410 + 0x20 * (n)) /* Loop counter 1 for DMA channel n */ 64 65 #define DBGSTATUS 0xD00 /* Debug Status */ 66 #define DBGCMD 0xD04 /* Debug Command */ 67 #define DBGINST0 0xD08 /* Debug Instruction-0 */ 68 #define DBGINST1 0xD0C /* Debug Instruction-1 */ 69 #define CR0 0xE00 /* Configuration Register 0 */ 70 #define CR1 0xE04 /* Configuration Register 1 */ 71 #define CR2 0xE08 /* Configuration Register 2 */ 72 #define CR3 0xE0C /* Configuration Register 3 */ 73 #define CR4 0xE10 /* Configuration Register 4 */ 74 #define CRD 0xE14 /* DMA Configuration */ 75 #define WD 0xE80 /* Watchdog Register */ 76 77 #define R_SAR 0 78 #define R_CCR 1 79 #define R_DAR 2 80 81 /* 82 * 0xFE0- 0xFEC periph_id_n RO Configuration-dependent Peripheral Identification Registers 83 * 0xFF0- 0xFFC pcell_id_n RO Configuration-dependent Component Identification Registers 84 */ 85 86 /* pl330 ISA */ 87 #define DMAADDH 0x54 88 #define DMAADNH 0x5c 89 #define DMAEND 0x00 90 #define DMAFLUSHP 0x35 91 #define DMAGO 0xa0 92 #define DMAKILL 0x01 93 #define DMALD 0x04 94 #define DMALDP 0x25 95 #define DMALP 0x20 96 #define DMALPEND 0x28 97 #define DMALPEND_NF (1 << 4) /* DMALP started the loop */ 98 /* 99 * TODO: documentation miss opcode for infinite loop 100 * #define DMALPFE 0 101 */ 102 #define DMAMOV 0xbc 103 #define DMANOP 0x18 104 #define DMARMB 0x12 105 #define DMASEV 0x34 106 #define DMAST 0x08 107 #define DMASTP 0x29 108 #define DMASTZ 0x0c 109 #define DMAWFE 0x36 110 #define DMAWFP 0x30 111 #define DMAWMB 0x13 112 113 #endif /* !_DEV_XDMA_CONTROLLER_PL330_H_ */ 114