| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 457 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); checkRegUsage() local
506 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); optLEAALU() local
565 Register BaseReg = Base.getReg(); optTwoAddrLEA() local
758 Register BaseReg = Base.getReg(); processInstrForSlow3OpLEA() local
[all...] |
| H A D | X86AsmPrinter.cpp | 376 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
472 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| H A D | X86InsertPrefetch.cpp | 85 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 126 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
190 emitThumbRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,Register DestReg,Register BaseReg,int NumBytes,const TargetInstrInfo & TII,const ARMBaseRegisterInfo & MRI,unsigned MIFlags) emitThumbRegPlusImmediate() argument
443 resolveFrameIndex(MachineInstr & MI,Register BaseReg,int64_t Offset) const resolveFrameIndex() argument
[all...] |
| H A D | Thumb2SizeReduction.cpp | 497 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
527 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
535 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
548 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| H A D | ARMBaseRegisterInfo.cpp | 681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
722 Register BaseReg, in isFrameOffsetLegal()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.h | 38 Register BaseReg; global() member
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 291 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
364 Register BaseReg; in insertFrameReferenceRegisters() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FalkorHWPFFix.cpp | 214 Register BaseReg; member
643 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| H A D | AArch64StorePairSuppress.cpp | 168 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| H A D | AArch64RegisterInfo.cpp | 806 Register BaseReg, in isFrameOffsetLegal()
828 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
840 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | AArch64LoadStoreOptimizer.cpp | 1299 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1694 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
2055 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
2106 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
2184 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 649 Register BaseReg, in isFrameOffsetLegal()
676 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister() local
685 void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 90 SDValue &BaseReg, in SelectGlobalValueVariableOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 87 Register BaseReg; in getPointerInfo() local
204 Register BaseReg; in instMayAlias() local
744 Register BaseReg; in mergeTruncStore() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMemAbsolute.cpp | 143 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 130 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86IntelInstPrinter.cpp | 383 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| H A D | X86ATTInstPrinter.cpp | 426 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| H A D | X86MCTargetDesc.cpp | 665 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress() local
691 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 374 BaseReg = MBBIter->getOperand(1).getReg(); combineMemAluInBasicBlock() local
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| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | Store.cpp | 296 const MemRegion *BaseReg = MRMgr.getCXXBaseObjectRegion( in evalDerivedToBase() local
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