| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 457 Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg(); in checkRegUsage() local
506 Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg(); in optLEAALU() local
565 Register BaseReg = Base.getReg(); in optTwoAddrLEA() local
758 Register BaseReg = Base.getReg(); in processInstrForSlow3OpLEA() local
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| H A D | X86AsmPrinter.cpp | 420 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
515 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| H A D | X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 494 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
524 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
532 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
545 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| H A D | ThumbRegisterInfo.cpp | 124 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
252 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
519 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | ARMBaseRegisterInfo.cpp | 710 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
722 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
751 Register BaseReg, in isFrameOffsetLegal()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LocalStackSlotAllocation.cpp | 290 static inline bool lookupCandidateBaseReg(Register BaseReg, int64_t BaseOffset, in lookupCandidateBaseReg()
362 Register BaseReg; in insertFrameReferenceRegisters() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FalkorHWPFFix.cpp | 208 Register BaseReg; member
637 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| H A D | AArch64StorePairSuppress.cpp | 166 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| H A D | AArch64RegisterInfo.cpp | 873 Register BaseReg, in isFrameOffsetLegal()
895 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
907 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | AArch64LoadStoreOptimizer.cpp | 1567 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1973 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
2363 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in mergeConstOffsetInsn() local
2409 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
2490 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
2600 Register BaseReg = AArch64InstrInfo::getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| /freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | SFrame.h | 75 enum class BaseReg : uint8_t { enum
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelDAGToDAG.cpp | 91 SDValue &BaseReg, in SelectGlobalValueVariableOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.cpp | 735 Register BaseReg, in isFrameOffsetLegal()
762 Register BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass); in materializeFrameBaseRegister() local
771 void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| H A D | RISCVLoadStoreOptimizer.cpp | 229 Register BaseReg = FirstMI.getOperand(1).getReg(); in findMatchingInsn() local
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 84 Register BaseReg; in getPointerInfo() local
201 Register BaseReg; in instMayAlias() local
739 Register BaseReg; in mergeTruncStore() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMemAbsolute.cpp | 133 unsigned BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 129 MCRegister BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86IntelInstPrinter.cpp | 391 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| H A D | X86ATTInstPrinter.cpp | 450 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| H A D | X86MCTargetDesc.cpp | 664 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress() local
690 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in getMemoryOperandRelocationOffset() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 367 BaseReg = MBBIter->getOperand(1).getReg(); in combineMemAluInBasicBlock() local
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