xref: /illumos-gate/usr/src/uts/sun4v/io/n2piupc/n2piupc_tables.h (revision ea1a228c80597366447774aa1988868492330eb5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_N2PIUPC_TABLES_H
28 #define	_N2PIUPC_TABLES_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 /*
33  * Table definitions for the N2 PIU performance counter driver.
34  *
35  * Each table consists of one or more groups of counters.
36  *
37  * A counter group will a name (used by busstat as the kstat "module" name),
38  * have its own set of kstats, and a common event select register.  A group is
39  * represented as an n2piu_grp_t.
40  *
41  * Each counter is represented by an n2piu_cntr_t.  Each has its own register
42  * offset (or address), bits for the data it represents, plus an associated
43  * register for zeroing it.
44  *
45  * All registers for n2piu are 64 bit, but a size field can be entered into this
46  * structure if registers sizes vary for other implementations (as if this code
47  * is leveraged for a future driver).
48  *
49  * A select register is represented by an n2piu_regsel_t.  This defines the
50  * offset or address, and an array of fields which define the events for each
51  * counter it services.  All counters need to have an entry in the fields array
52  * even if they don't have any representation in a select register.  Please see
53  * the explanation of the events array (below) for more information.  Counters
54  * without representation in a select register can specify their (non-existant)
55  * select register field with mask NONPROG_DUMMY_MASK and offset
56  * NONPROG_DUMMY_OFF.
57  *
58  * This implementation supports only one select register per group.  If more
59  * are needed (e.g. if this implementation is used as a template for another
60  * device which has multiple select registers per group) the data structures can
61  * easily be changed to support an array of them.   Add an array index in the
62  * counter structure to associate that counter with a particular select
63  * register, and add a field for the number of select registers in the group
64  * structure.
65  *
66  * Each counter has an array of programmable events associated with it, even if
67  * it is not programmable.  This array is a series of name/value pairs defined
68  * by n2piu_event_t.  The value is the event value loaded into the select
69  * register to select that event for that counter.  The last entry in the array
70  * is always an entry with a bitmask of LSB-aligned bits of that counter's
71  * select register's field's width;  it is usually called the CLEAR_PIC entry.
72  * CLEAR_PIC entries are not shown to the user.
73  *
74  * Note that counters without programmable events still need to define a
75  * (small) events array with at least CLEAR_PIC and a single event, so that
76  * event's name can display in busstat output.  The CLEAR_PIC entry of
77  * nonprogrammable counters can have a value of NONPROG_DUMMY_MASK.
78  */
79 
80 #ifdef	__cplusplus
81 extern "C" {
82 #endif
83 
84 #include <sys/types.h>
85 #include <sys/kstat.h>
86 #include "n2piupc_acc.h"
87 
88 /*
89  * Description of a counter's events.  Each counter will have an array of these,
90  * to define the events it can be programmed to report.  Nonprogrammable
91  * counters still need an array of these, to contain the name busstat will
92  * display for it, and a CLEAR_PIC entry.
93  */
94 typedef struct n2piu_event {
95 	char *name;
96 	uint64_t value;
97 } n2piu_event_t;
98 
99 /*
100  * Description of a counter's event selection.  There will be one entry for
101  * each counter in the group.
102  */
103 typedef struct n2piu_regsel_fld {
104 	n2piu_event_t *events_p;
105 	int num_events;		/* Size of events array. */
106 	uint64_t event_mask;	/* Width of the event field. */
107 	int event_offset;	/* Offset of the event field. */
108 } n2piu_regsel_fld_t;
109 
110 #define	NUM_EVTS(x)	(sizeof (x) / sizeof (n2piu_event_t))
111 
112 /*
113  * Description of a group's select register.
114  */
115 typedef struct n2piu_regsel {
116 	off_t regoff;			/* Register offset or address. */
117 	n2piu_regsel_fld_t *fields_p;	/* select reg subfield descriptions.  */
118 	int num_fields;			/* Size of the fields array. */
119 } n2piu_regsel_t;
120 
121 #define	NUM_FLDS(x)	(sizeof (x) / sizeof (n2piu_regsel_fld_t))
122 
123 /*
124  * Counter description, including its access logistics and how to zero it.
125  */
126 typedef struct n2piu_cntr {
127 	off_t regoff;		/* Register offset or address. */
128 	uint64_t fld_mask;	/* Width of the active part of the register */
129 	off_t zero_regoff;	/* Offset of register used to zero counter. */
130 	uint64_t zero_value;	/* Value to write to zero_regoff, to clr cntr */
131 } n2piu_cntr_t;
132 
133 #define	FULL64BIT	-1ULL	/* Can use this for fld_mask. */
134 
135 /*
136  * Group description.
137  */
138 typedef struct n2piu_grp {
139 	char *grp_name;		  /* Name, shows up as busstat "module" name. */
140 	n2piu_regsel_t *regsel_p; /* Select register. */
141 	n2piu_cntr_t *counters_p; /* Counter definitions. */
142 	int num_counters;	  /* Size of the counters array. */
143 	kstat_t **name_kstats_pp; /* Named kstats.  One for all instances. */
144 } n2piu_grp_t;
145 
146 #define	NUM_CTRS(x) (sizeof (x) / sizeof (n2piu_cntr_t))
147 
148 /* N2PIU-specific definitions. */
149 
150 /* Where groups are in the leaf_grps array. */
151 
152 #define	NUM_GRPS	4
153 #define	IMU_GRP		0
154 #define	MMU_GRP		1
155 #define	PEU_GRP		2
156 #define	BIT_ERR_GRP	3
157 
158 /* The table itself. */
159 extern n2piu_grp_t *leaf_grps[];
160 
161 /* Standin symbol for when there is no register. */
162 #define	NO_REGISTER			(off_t)-1ULL
163 
164 /*
165  * Default event values used in n2piu_event_t structures for non-programmable
166  * registers.
167  */
168 #define	NONPROG_DUMMY_MASK	0
169 #define	NONPROG_DUMMY_OFF	0
170 
171 /*
172  * Event bitmask definitions for all groups.
173  */
174 #define	IMU_CTR_EVT_MASK	0xffull
175 #define	IMU_CTR_0_EVT_OFF	0
176 #define	IMU_CTR_1_EVT_OFF	8
177 
178 #define	MMU_CTR_EVT_MASK	0xffull
179 #define	MMU_CTR_0_EVT_OFF	0
180 #define	MMU_CTR_1_EVT_OFF	8
181 
182 #define	PEU_CTR_01_EVT_MASK	0xffull
183 #define	PEU_CTR_2_EVT_MASK	0x3ull
184 #define	PEU_CTR_0_EVT_OFF	0
185 #define	PEU_CTR_1_EVT_OFF	8
186 #define	PEU_CTR_2_EVT_OFF	16
187 
188 #define	BTERR_CTR_0_EVT_MASK	0x1ull
189 #define	BTERR_CTR_0_EVT_OFF	0
190 
191 /*
192  * Fake the biterr event register to be one with two fields, to store the
193  * overall enable/disable event (looks like pic0 reset) and the bterr3 events.
194  */
195 
196 #define	BTERR_CTR_3_EVT_MASK	0xfull
197 #define	BTERR_CTR_3_EVT_OFF	0
198 
199 /*
200  * Note: this "event" is really an enable, and it serves all 4 PICs.
201  *
202  * PICs 0,1,2 are from the first counter, PIC3 is from the second counter.
203  */
204 #define	BTERR_CTR_ENABLE_MASK	0x1ull
205 #define	BTERR_CTR_ENABLE_OFF	63
206 
207 #define	BTERR_CTR_ENABLE	(BTERR_CTR_ENABLE_MASK << BTERR_CTR_ENABLE_OFF)
208 
209 /*
210  * This register also has a bit to zero the counters.
211  */
212 #define	BTERR_CTR_CLR_MASK	0x1ull
213 #define	BTERR_CTR_CLR_OFF	62
214 
215 #define	BTERR_CTR_CLR		(BTERR_CTR_CLR_MASK << BTERR_CTR_CLR_OFF)
216 
217 #define	BTERR_CTR_ENABLE_AND_CLR	(BTERR_CTR_ENABLE | BTERR_CTR_CLR)
218 
219 /*
220  * Definitions of the different types of events.
221  *
222  * The first part says which registers these events are for.
223  * For example, IMU01 means the IMU performance counters 0 and 1
224  */
225 
226 /* String sought by busstat to locate the event field width "event" entry. */
227 #define	COMMON_S_CLEAR_PIC			"clear_pic"
228 
229 
230 #define	IMU01_S_EVT_NONE			"event_none"
231 #define	IMU01_S_EVT_CLK				"clock_cyc"
232 #define	IMU01_S_EVT_TOTAL_MONDO			"total_mondo"
233 #define	IMU01_S_EVT_TOTAL_MSI			"total_msi"
234 #define	IMU01_S_EVT_NAK_MONDO			"mondo_nak"
235 #define	IMU01_S_EVT_EQ_WR			"eq_write"
236 #define	IMU01_S_EVT_EQ_MONDO			"eq_mondo"
237 
238 #define	IMU01_EVT_NONE				0
239 #define	IMU01_EVT_CLK				1
240 #define	IMU01_EVT_TOTAL_MONDO			2
241 #define	IMU01_EVT_TOTAL_MSI			3
242 #define	IMU01_EVT_NAK_MONDO			4
243 #define	IMU01_EVT_EQ_WR				5
244 #define	IMU01_EVT_EQ_MONDO			6
245 
246 
247 #define	MMU01_S_EVT_NONE			"event_none"
248 #define	MMU01_S_EVT_CLK				"clock_cyc"
249 #define	MMU01_S_EVT_TRANS			"total_transl"
250 #define	MMU01_S_EVT_STALL			"total_stall_cyc"
251 #define	MMU01_S_EVT_TRANS_MISS			"total_transl_miss"
252 #define	MMU01_S_EVT_TBLWLK_STALL		"tblwlk_stall_cyc"
253 #define	MMU01_S_EVT_BYPASS_TRANSL		"bypass_transl"
254 #define	MMU01_S_EVT_TRANSL_TRANSL		"transl_transl"
255 #define	MMU01_S_EVT_FLOW_CNTL_STALL		"flow_stall_cyc"
256 #define	MMU01_S_EVT_FLUSH_CACHE_ENT		"cache_entr_flush"
257 
258 #define	MMU01_EVT_NONE				0
259 #define	MMU01_EVT_CLK				1
260 #define	MMU01_EVT_TRANS				2
261 #define	MMU01_EVT_STALL				3
262 #define	MMU01_EVT_TRANS_MISS			4
263 #define	MMU01_EVT_TBLWLK_STALL			5
264 #define	MMU01_EVT_BYPASS_TRANSL			6
265 #define	MMU01_EVT_TRANSL_TRANSL			7
266 #define	MMU01_EVT_FLOW_CNTL_STALL		8
267 #define	MMU01_EVT_FLUSH_CACHE_ENT		9
268 
269 
270 #define	PEU2_S_EVT_NONE				"event_none"
271 #define	PEU2_S_EVT_NONPST_CMPL_TIME		"npost_compl_time"
272 #define	PEU2_S_EVT_XMIT_DATA			"xmit_data"
273 #define	PEU2_S_EVT_RCVD_DATA			"rcvd_data"
274 
275 #define	PEU2_EVT_NONE				0
276 #define	PEU2_EVT_NONPST_CMPL_TIME		1
277 #define	PEU2_EVT_XMIT_DATA			2
278 #define	PEU2_EVT_RCVD_DATA			3
279 
280 
281 #define	PEU01_S_EVT_NONE			"event_none"
282 #define	PEU01_S_EVT_CLK				"clock_cyc"
283 #define	PEU01_S_EVT_COMPL			"compl_recvd"
284 #define	PEU01_S_EVT_XMT_POST_CR_UNAV		"post_cr_unav_cyc"
285 #define	PEU01_S_EVT_XMT_NPOST_CR_UNAV		"npost_cr_unav_cyc"
286 #define	PEU01_S_EVT_XMT_CMPL_CR_UNAV		"compl_cr_unav_cyc"
287 #define	PEU01_S_EVT_XMT_ANY_CR_UNAV		"trans_cr_any_unav"
288 #define	PEU01_S_EVT_RETRY_CR_UNAV		"retry_cr_unav"
289 #define	PEU01_S_EVT_MEMRD_PKT_RCVD		"recvd_mem_rd_pkt"
290 #define	PEU01_S_EVT_MEMWR_PKT_RCVD		"recvd_mem_wr_pkt"
291 #define	PEU01_S_EVT_RCV_CR_THRESH		"recv_cr_thresh"
292 #define	PEU01_S_EVT_RCV_PST_HDR_CR_EXH		"recv_hdr_cr_exh_cyc"
293 #define	PEU01_S_EVT_RCV_PST_DA_CR_MPS		"recv_post_da_cr_mps"
294 #define	PEU01_S_EVT_RCV_NPST_HDR_CR_EXH		"recv_npost_hdr_cr_exh"
295 #define	PEU01_S_EVT_RCVR_L0S			"recvr_l0s_cyc"
296 #define	PEU01_S_EVT_RCVR_L0S_TRANS		"recvr_l0s_trans"
297 #define	PEU01_S_EVT_XMTR_L0S			"trans_l0s_cyc"
298 #define	PEU01_S_EVT_XMTR_L0S_TRANS		"trans_l0s_trans"
299 #define	PEU01_S_EVT_RCVR_ERR			"recvr_err"
300 #define	PEU01_S_EVT_BAD_TLP			"bad_tlp"
301 #define	PEU01_S_EVT_BAD_DLLP			"bad_dllp"
302 #define	PEU01_S_EVT_REPLAY_ROLLOVER		"replay_rollover"
303 #define	PEU01_S_EVT_REPLAY_TMO			"replay_to"
304 
305 #define	PEU01_EVT_NONE				0x0
306 #define	PEU01_EVT_CLK				0x1
307 #define	PEU01_EVT_COMPL				0x2
308 #define	PEU01_EVT_XMT_POST_CR_UNAV		0x10
309 #define	PEU01_EVT_XMT_NPOST_CR_UNAV		0x11
310 #define	PEU01_EVT_XMT_CMPL_CR_UNAV		0x12
311 #define	PEU01_EVT_XMT_ANY_CR_UNAV		0x13
312 #define	PEU01_EVT_RETRY_CR_UNAV			0x14
313 #define	PEU01_EVT_MEMRD_PKT_RCVD		0x20
314 #define	PEU01_EVT_MEMWR_PKT_RCVD		0x21
315 #define	PEU01_EVT_RCV_CR_THRESH			0x22
316 #define	PEU01_EVT_RCV_PST_HDR_CR_EXH		0x23
317 #define	PEU01_EVT_RCV_PST_DA_CR_MPS		0x24
318 #define	PEU01_EVT_RCV_NPST_HDR_CR_EXH		0x25
319 #define	PEU01_EVT_RCVR_L0S			0x30
320 #define	PEU01_EVT_RCVR_L0S_TRANS		0x31
321 #define	PEU01_EVT_XMTR_L0S			0x32
322 #define	PEU01_EVT_XMTR_L0S_TRANS		0x33
323 #define	PEU01_EVT_RCVR_ERR			0x40
324 #define	PEU01_EVT_BAD_TLP			0x42
325 #define	PEU01_EVT_BAD_DLLP			0x43
326 #define	PEU01_EVT_REPLAY_ROLLOVER		0x44
327 #define	PEU01_EVT_REPLAY_TMO			0x47
328 
329 /*
330  * BTERR counter 3 is presented by the device as one register with 8 different
331  * counters.  Since busstat displays in decimal and not in hex, display of the
332  * raw data is impractical except to make a non-zero test.  Fake that this
333  * register has multiple modes, so that each lane can be shown separately.
334  * Then one can use Busstat capabilities to display alternating events of a
335  * register.
336  */
337 
338 #define	BTERR3_S_EVT_NONE			"event_none"
339 #define	BTERR3_S_EVT_ENC_ALL			"encd_err_ln_all"
340 #define	BTERR3_S_EVT_ENC_LANE_0			"encd_err_ln_0"
341 #define	BTERR3_S_EVT_ENC_LANE_1			"encd_err_ln_1"
342 #define	BTERR3_S_EVT_ENC_LANE_2			"encd_err_ln_2"
343 #define	BTERR3_S_EVT_ENC_LANE_3			"encd_err_ln_3"
344 #define	BTERR3_S_EVT_ENC_LANE_4			"encd_err_ln_4"
345 #define	BTERR3_S_EVT_ENC_LANE_5			"encd_err_ln_5"
346 #define	BTERR3_S_EVT_ENC_LANE_6			"encd_err_ln_6"
347 #define	BTERR3_S_EVT_ENC_LANE_7			"encd_err_ln_7"
348 
349 #define	BTERR3_EVT_ENC_NONE			0
350 #define	BTERR3_EVT_ENC_ALL			1
351 #define	BTERR3_EVT_ENC_LANE_0			2
352 #define	BTERR3_EVT_ENC_LANE_1			3
353 #define	BTERR3_EVT_ENC_LANE_2			4
354 #define	BTERR3_EVT_ENC_LANE_3			5
355 #define	BTERR3_EVT_ENC_LANE_4			6
356 #define	BTERR3_EVT_ENC_LANE_5			7
357 #define	BTERR3_EVT_ENC_LANE_6			8
358 #define	BTERR3_EVT_ENC_LANE_7			9
359 
360 /*
361  * For non-programmable registers, include an n2piu_event_t which has two
362  * fields, a default field (which gives the field a name even though it
363  * can't be programmed, and clear_pic which busstat needs.
364  */
365 #define	BTERR2_S_EVT_PRE			"phys_rcvr_errs"
366 
367 #define	BTERR2_EVT_PRE				0
368 
369 #define	BTERR1_S_EVT_BTLP			"bad_tlps"
370 
371 #define	BTERR1_EVT_BTLP				0
372 
373 /*
374  * Note: All 4 biterr counter fields (split among two counter registers) are
375  * tied together with a single enable.  Treat the first field as programmable
376  * to provide a way to reset the counter set.
377  */
378 #define	BTERR0_S_EVT_RESET	"reset_bterr"	/* All biterr counter zero */
379 #define	BTERR0_S_EVT_BDLLP	"bad_dllps"
380 
381 #define	BTERR0_EVT_RESET	0
382 #define	BTERR0_EVT_BDLLP	1
383 
384 /*
385  * First bit error counter register has three counters.  Here are the
386  * placements of these counters within the (virtual) registers.
387  */
388 #define	BE1_BAD_DLLP_MASK	0xff000000ULL
389 #define	BE1_BAD_TLP_MASK	0xff0000ULL
390 #define	BE1_BAD_PRE_MASK	0x3ffULL
391 #define	BE2_8_10_MASK		FULL64BIT
392 
393 #ifdef	__cplusplus
394 }
395 #endif
396 
397 #endif	/* _N2PIUPC_TABLES_H */
398