1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2025 Broadcom */ 3 4 #ifndef _BNGE_RMEM_H_ 5 #define _BNGE_RMEM_H_ 6 7 struct bnge_ctx_mem_type; 8 struct bnge_dev; 9 10 #define PTU_PTE_VALID 0x1UL 11 #define PTU_PTE_LAST 0x2UL 12 #define PTU_PTE_NEXT_TO_LAST 0x4UL 13 14 struct bnge_ring_mem_info { 15 /* Number of pages to next level */ 16 int nr_pages; 17 int page_size; 18 u16 flags; 19 #define BNGE_RMEM_VALID_PTE_FLAG 1 20 #define BNGE_RMEM_RING_PTE_FLAG 2 21 #define BNGE_RMEM_USE_FULL_PAGE_FLAG 4 22 23 u16 depth; 24 25 void **pg_arr; 26 dma_addr_t *dma_arr; 27 28 __le64 *pg_tbl; 29 dma_addr_t dma_pg_tbl; 30 31 int vmem_size; 32 void **vmem; 33 34 struct bnge_ctx_mem_type *ctx_mem; 35 }; 36 37 /* The hardware supports certain page sizes. 38 * Use the supported page sizes to allocate the rings. 39 */ 40 #if (PAGE_SHIFT < 12) 41 #define BNGE_PAGE_SHIFT 12 42 #elif (PAGE_SHIFT <= 13) 43 #define BNGE_PAGE_SHIFT PAGE_SHIFT 44 #elif (PAGE_SHIFT < 16) 45 #define BNGE_PAGE_SHIFT 13 46 #else 47 #define BNGE_PAGE_SHIFT 16 48 #endif 49 #define BNGE_PAGE_SIZE (1 << BNGE_PAGE_SHIFT) 50 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 51 #if (PAGE_SHIFT > 15) 52 #define BNGE_RX_PAGE_SHIFT 15 53 #else 54 #define BNGE_RX_PAGE_SHIFT PAGE_SHIFT 55 #endif 56 #define MAX_CTX_PAGES (BNGE_PAGE_SIZE / 8) 57 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 58 59 struct bnge_ctx_pg_info { 60 u32 entries; 61 u32 nr_pages; 62 void *ctx_pg_arr[MAX_CTX_PAGES]; 63 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; 64 struct bnge_ring_mem_info ring_mem; 65 struct bnge_ctx_pg_info **ctx_pg_tbl; 66 }; 67 68 #define BNGE_MAX_TQM_SP_RINGS 1 69 #define BNGE_MAX_TQM_FP_RINGS 8 70 #define BNGE_MAX_TQM_RINGS \ 71 (BNGE_MAX_TQM_SP_RINGS + BNGE_MAX_TQM_FP_RINGS) 72 #define BNGE_BACKING_STORE_CFG_LEGACY_LEN 256 73 #define BNGE_SET_CTX_PAGE_ATTR(attr) \ 74 do { \ 75 if (BNGE_PAGE_SIZE == 0x2000) \ 76 attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K; \ 77 else if (BNGE_PAGE_SIZE == 0x10000) \ 78 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K; \ 79 else \ 80 attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K; \ 81 } while (0) 82 83 #define BNGE_CTX_MRAV_AV_SPLIT_ENTRY 0 84 85 #define BNGE_CTX_QP \ 86 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 87 #define BNGE_CTX_SRQ \ 88 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 89 #define BNGE_CTX_CQ \ 90 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 91 #define BNGE_CTX_VNIC \ 92 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 93 #define BNGE_CTX_STAT \ 94 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 95 #define BNGE_CTX_STQM \ 96 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 97 #define BNGE_CTX_FTQM \ 98 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 99 #define BNGE_CTX_MRAV \ 100 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 101 #define BNGE_CTX_TIM \ 102 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 103 #define BNGE_CTX_TCK \ 104 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 105 #define BNGE_CTX_RCK \ 106 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 107 #define BNGE_CTX_MTQM \ 108 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 109 #define BNGE_CTX_SQDBS \ 110 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 111 #define BNGE_CTX_RQDBS \ 112 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 113 #define BNGE_CTX_SRQDBS \ 114 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 115 #define BNGE_CTX_CQDBS \ 116 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 117 #define BNGE_CTX_SRT_TRACE \ 118 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 119 #define BNGE_CTX_SRT2_TRACE \ 120 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 121 #define BNGE_CTX_CRT_TRACE \ 122 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 123 #define BNGE_CTX_CRT2_TRACE \ 124 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 125 #define BNGE_CTX_RIGP0_TRACE \ 126 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 127 #define BNGE_CTX_L2_HWRM_TRACE \ 128 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 129 #define BNGE_CTX_ROCE_HWRM_TRACE \ 130 FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 131 132 #define BNGE_CTX_MAX (BNGE_CTX_TIM + 1) 133 #define BNGE_CTX_L2_MAX (BNGE_CTX_FTQM + 1) 134 #define BNGE_CTX_INV ((u16)-1) 135 136 #define BNGE_CTX_V2_MAX \ 137 (FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE + 1) 138 139 #define BNGE_BS_CFG_ALL_DONE \ 140 FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 141 142 struct bnge_ctx_mem_type { 143 u16 type; 144 u16 entry_size; 145 u32 flags; 146 #define BNGE_CTX_MEM_TYPE_VALID \ 147 FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 148 u32 instance_bmap; 149 u8 init_value; 150 u8 entry_multiple; 151 u16 init_offset; 152 #define BNGE_CTX_INIT_INVALID_OFFSET 0xffff 153 u32 max_entries; 154 u32 min_entries; 155 u8 last:1; 156 u8 split_entry_cnt; 157 #define BNGE_MAX_SPLIT_ENTRY 4 158 union { 159 struct { 160 u32 qp_l2_entries; 161 u32 qp_qp1_entries; 162 u32 qp_fast_qpmd_entries; 163 }; 164 u32 srq_l2_entries; 165 u32 cq_l2_entries; 166 u32 vnic_entries; 167 struct { 168 u32 mrav_av_entries; 169 u32 mrav_num_entries_units; 170 }; 171 u32 split[BNGE_MAX_SPLIT_ENTRY]; 172 }; 173 struct bnge_ctx_pg_info *pg_info; 174 }; 175 176 struct bnge_ctx_mem_info { 177 u8 tqm_fp_rings_count; 178 u32 flags; 179 #define BNGE_CTX_FLAG_INITED 0x01 180 struct bnge_ctx_mem_type ctx_arr[BNGE_CTX_V2_MAX]; 181 }; 182 183 int bnge_alloc_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem); 184 void bnge_free_ring(struct bnge_dev *bd, struct bnge_ring_mem_info *rmem); 185 int bnge_alloc_ctx_mem(struct bnge_dev *bd); 186 void bnge_free_ctx_mem(struct bnge_dev *bd); 187 188 #endif /* _BNGE_RMEM_H_ */ 189