1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2005-2006 Atheros Communications, Inc. 6 * All rights reserved. 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #ifndef __AH_REGDOMAIN_DOMAINS_H__ 22 #define __AH_REGDOMAIN_DOMAINS_H__ 23 24 /* 25 * BMLEN defines the size of the bitmask used to hold frequency 26 * band specifications. Note this must agree with the BM macro 27 * definition that's used to setup initializers. See also further 28 * comments below. 29 */ 30 /* BMLEN is now defined in ah_regdomain.h */ 31 #define W0(_a) \ 32 (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 33 #define W1(_a) \ 34 (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 35 #define BM1(_fa) { W0(_fa), W1(_fa) } 36 #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 37 #define BM3(_fa, _fb, _fc) \ 38 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 39 #define BM4(_fa, _fb, _fc, _fd) \ 40 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 41 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 42 #define BM5(_fa, _fb, _fc, _fd, _fe) \ 43 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 44 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 45 #define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 46 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 47 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 48 #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 49 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 50 W0(_fg),\ 51 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 52 W1(_fg) } 53 #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 54 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 55 W0(_fg) | W0(_fh) , \ 56 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 57 W1(_fg) | W1(_fh) } 58 #define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \ 59 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 60 W0(_fg) | W0(_fh) | W0(_fi) , \ 61 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 62 W1(_fg) | W1(_fh) | W1(_fi) } 63 64 static REG_DOMAIN regDomains[] = { 65 {.regDmnEnum = DEBUG_REG_DMN, 66 .conformanceTestLimit = FCC, 67 .dfsMask = DFS_FCC3, 68 .chan11a = BM4(F1_4950_4980, 69 F1_5120_5240, 70 F1_5260_5700, 71 F1_5745_5825), 72 .chan11a_half = BM4(F1_4945_4985, 73 F2_5120_5240, 74 F2_5260_5700, 75 F7_5745_5825), 76 .chan11a_quarter = BM4(F1_4942_4987, 77 F3_5120_5240, 78 F3_5260_5700, 79 F8_5745_5825), 80 .chan11a_turbo = BM8(T1_5130_5210, 81 T1_5250_5330, 82 T1_5370_5490, 83 T1_5530_5650, 84 T1_5150_5190, 85 T1_5230_5310, 86 T1_5350_5470, 87 T1_5510_5670), 88 .chan11a_dyn_turbo = BM4(T1_5200_5240, 89 T1_5280_5280, 90 T1_5540_5660, 91 T1_5765_5805), 92 .chan11b = BM4(F1_2312_2372, 93 F1_2412_2472, 94 F1_2484_2484, 95 F1_2512_2732), 96 .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 97 .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 98 .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 99 .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 100 }, 101 102 {.regDmnEnum = APL1, 103 .conformanceTestLimit = FCC, 104 .chan11a = BM1(F4_5745_5825), 105 }, 106 107 {.regDmnEnum = APL2, 108 .conformanceTestLimit = FCC, 109 .chan11a = BM1(F1_5745_5805), 110 }, 111 112 {.regDmnEnum = APL3, 113 .conformanceTestLimit = FCC, 114 .chan11a = BM2(F1_5280_5320, F2_5745_5805), 115 }, 116 117 {.regDmnEnum = APL4, 118 .conformanceTestLimit = FCC, 119 .chan11a = BM2(F4_5180_5240, F3_5745_5825), 120 }, 121 122 {.regDmnEnum = APL5, 123 .conformanceTestLimit = FCC, 124 .chan11a = BM1(F2_5745_5825), 125 }, 126 127 {.regDmnEnum = APL6, 128 .conformanceTestLimit = ETSI, 129 .dfsMask = DFS_ETSI, 130 .pscan = PSCAN_FCC_T | PSCAN_FCC, 131 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 132 .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 133 }, 134 135 {.regDmnEnum = APL8, 136 .conformanceTestLimit = ETSI, 137 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 138 .chan11a = BM2(F6_5260_5320, F4_5745_5825), 139 }, 140 141 {.regDmnEnum = APL9, 142 .conformanceTestLimit = ETSI, 143 .dfsMask = DFS_ETSI, 144 .pscan = PSCAN_ETSI, 145 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 146 .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 147 }, 148 149 {.regDmnEnum = ETSI1, 150 .conformanceTestLimit = ETSI, 151 .dfsMask = DFS_ETSI, 152 .pscan = PSCAN_ETSI, 153 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 154 .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 155 }, 156 157 {.regDmnEnum = ETSI2, 158 .conformanceTestLimit = ETSI, 159 .dfsMask = DFS_ETSI, 160 .pscan = PSCAN_ETSI, 161 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 162 .chan11a = BM1(F3_5180_5240), 163 }, 164 165 {.regDmnEnum = ETSI3, 166 .conformanceTestLimit = ETSI, 167 .dfsMask = DFS_ETSI, 168 .pscan = PSCAN_ETSI, 169 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 170 .chan11a = BM2(W2_5180_5240, F2_5260_5320), 171 }, 172 173 {.regDmnEnum = ETSI4, 174 .conformanceTestLimit = ETSI, 175 .dfsMask = DFS_ETSI, 176 .pscan = PSCAN_ETSI, 177 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 178 .chan11a = BM2(F3_5180_5240, F1_5260_5320), 179 }, 180 181 {.regDmnEnum = ETSI5, 182 .conformanceTestLimit = ETSI, 183 .dfsMask = DFS_ETSI, 184 .pscan = PSCAN_ETSI, 185 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 186 .chan11a = BM1(F1_5180_5240), 187 }, 188 189 {.regDmnEnum = ETSI6, 190 .conformanceTestLimit = ETSI, 191 .dfsMask = DFS_ETSI, 192 .pscan = PSCAN_ETSI, 193 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 194 .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 195 }, 196 197 {.regDmnEnum = FCC1, 198 .conformanceTestLimit = FCC, 199 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 200 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 201 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 202 }, 203 204 {.regDmnEnum = FCC2, 205 .conformanceTestLimit = FCC, 206 .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 207 .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 208 }, 209 210 {.regDmnEnum = FCC3, 211 .conformanceTestLimit = FCC, 212 .dfsMask = DFS_FCC3, 213 .pscan = PSCAN_FCC | PSCAN_FCC_T, 214 .chan11a = BM4(F2_5180_5240, 215 F3_5260_5320, 216 F1_5500_5700, 217 F5_5745_5825), 218 .chan11a_turbo = BM4(T1_5210_5210, 219 T1_5250_5250, 220 T1_5290_5290, 221 T2_5760_5800), 222 .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 223 }, 224 225 {.regDmnEnum = FCC4, 226 .conformanceTestLimit = FCC, 227 .dfsMask = DFS_FCC3, 228 .pscan = PSCAN_FCC | PSCAN_FCC_T, 229 .chan11a = BM1(F1_4950_4980), 230 .chan11a_half = BM1(F1_4945_4985), 231 .chan11a_quarter = BM1(F1_4942_4987), 232 }, 233 234 /* FCC1 w/ 1/2 and 1/4 width channels */ 235 {.regDmnEnum = FCC5, 236 .conformanceTestLimit = FCC, 237 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 238 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 239 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 240 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 241 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 242 }, 243 244 {.regDmnEnum = FCC6, 245 .conformanceTestLimit = FCC, 246 .chan11a = BM5(F8_5180_5240, F5_5260_5320, F1_5500_5580, F2_5660_5720, F6_5745_5825), 247 .chan11a_turbo = BM3(T7_5210_5210, T3_5250_5290, T2_5760_5800), 248 .chan11a_dyn_turbo = BM4(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805), 249 #if 0 250 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 251 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 252 #endif 253 }, 254 255 {.regDmnEnum = MKK1, 256 .conformanceTestLimit = MKK, 257 .pscan = PSCAN_MKK1, 258 .flags = DISALLOW_ADHOC_11A_TURB, 259 .chan11a = BM1(F1_5170_5230), 260 }, 261 262 {.regDmnEnum = MKK2, 263 .conformanceTestLimit = MKK, 264 .pscan = PSCAN_MKK2, 265 .flags = DISALLOW_ADHOC_11A_TURB, 266 .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 267 .chan11a_half = BM4(F1_4915_4925, 268 F1_4935_4945, 269 F1_5035_5040, 270 F1_5055_5055), 271 }, 272 273 /* UNI-1 even */ 274 {.regDmnEnum = MKK3, 275 .conformanceTestLimit = MKK, 276 .pscan = PSCAN_MKK3, 277 .flags = DISALLOW_ADHOC_11A_TURB, 278 .chan11a = BM1(F4_5180_5240), 279 }, 280 281 /* UNI-1 even + UNI-2 */ 282 {.regDmnEnum = MKK4, 283 .conformanceTestLimit = MKK, 284 .dfsMask = DFS_MKK4, 285 .pscan = PSCAN_MKK3, 286 .flags = DISALLOW_ADHOC_11A_TURB, 287 .chan11a = BM2(F4_5180_5240, F2_5260_5320), 288 }, 289 290 /* UNI-1 even + UNI-2 + mid-band */ 291 {.regDmnEnum = MKK5, 292 .conformanceTestLimit = MKK, 293 .dfsMask = DFS_MKK4, 294 .pscan = PSCAN_MKK3, 295 .flags = DISALLOW_ADHOC_11A_TURB, 296 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 297 }, 298 299 /* UNI-1 odd + even */ 300 {.regDmnEnum = MKK6, 301 .conformanceTestLimit = MKK, 302 .pscan = PSCAN_MKK1, 303 .flags = DISALLOW_ADHOC_11A_TURB, 304 .chan11a = BM2(F2_5170_5230, F4_5180_5240), 305 }, 306 307 /* UNI-1 odd + UNI-1 even + UNI-2 */ 308 {.regDmnEnum = MKK7, 309 .conformanceTestLimit = MKK, 310 .dfsMask = DFS_MKK4, 311 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 312 .flags = DISALLOW_ADHOC_11A_TURB, 313 .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 314 }, 315 316 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 317 {.regDmnEnum = MKK8, 318 .conformanceTestLimit = MKK, 319 .dfsMask = DFS_MKK4, 320 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 321 .flags = DISALLOW_ADHOC_11A_TURB, 322 .chan11a = BM4(F1_5170_5230, 323 F4_5180_5240, 324 F2_5260_5320, 325 F4_5500_5700), 326 }, 327 328 /* UNI-1 even + 4.9 GHZ */ 329 {.regDmnEnum = MKK9, 330 .conformanceTestLimit = MKK, 331 .pscan = PSCAN_MKK3, 332 .flags = DISALLOW_ADHOC_11A_TURB, 333 .chan11a = BM7(F1_4915_4925, 334 F1_4935_4945, 335 F1_4920_4980, 336 F1_5035_5040, 337 F1_5055_5055, 338 F1_5040_5080, 339 F4_5180_5240), 340 }, 341 342 /* UNI-1 even + UNI-2 + 4.9 GHZ */ 343 {.regDmnEnum = MKK10, 344 .conformanceTestLimit = MKK, 345 .dfsMask = DFS_MKK4, 346 .pscan = PSCAN_MKK3, 347 .flags = DISALLOW_ADHOC_11A_TURB, 348 .chan11a = BM8(F1_4915_4925, 349 F1_4935_4945, 350 F1_4920_4980, 351 F1_5035_5040, 352 F1_5055_5055, 353 F1_5040_5080, 354 F4_5180_5240, 355 F2_5260_5320), 356 }, 357 358 /* Defined here to use when 2G channels are authorised for country K2 */ 359 {.regDmnEnum = APLD, 360 .conformanceTestLimit = NO_CTL, 361 .chan11b = BM2(F2_2312_2372,F2_2412_2472), 362 .chan11g = BM2(G2_2312_2372,G2_2412_2472), 363 }, 364 365 {.regDmnEnum = ETSIA, 366 .conformanceTestLimit = NO_CTL, 367 .pscan = PSCAN_ETSIA, 368 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 369 .chan11b = BM1(F1_2457_2472), 370 .chan11g = BM1(G1_2457_2472), 371 .chan11g_turbo = BM1(T2_2437_2437) 372 }, 373 374 {.regDmnEnum = ETSIB, 375 .conformanceTestLimit = ETSI, 376 .pscan = PSCAN_ETSIB, 377 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 378 .chan11b = BM1(F1_2432_2442), 379 .chan11g = BM1(G1_2432_2442), 380 .chan11g_turbo = BM1(T2_2437_2437) 381 }, 382 383 {.regDmnEnum = ETSIC, 384 .conformanceTestLimit = ETSI, 385 .pscan = PSCAN_ETSIC, 386 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 387 .chan11b = BM1(F3_2412_2472), 388 .chan11g = BM1(G3_2412_2472), 389 .chan11g_turbo = BM1(T2_2437_2437) 390 }, 391 392 {.regDmnEnum = FCCA, 393 .conformanceTestLimit = FCC, 394 .chan11b = BM1(F1_2412_2462), 395 .chan11g = BM1(G1_2412_2462), 396 .chan11g_turbo = BM1(T2_2437_2437), 397 }, 398 399 /* FCCA w/ 1/2 and 1/4 width channels */ 400 {.regDmnEnum = FCCB, 401 .conformanceTestLimit = FCC, 402 .chan11b = BM1(F1_2412_2462), 403 .chan11g = BM1(G1_2412_2462), 404 .chan11g_turbo = BM1(T2_2437_2437), 405 .chan11g_half = BM1(G3_2412_2462), 406 .chan11g_quarter = BM1(G4_2412_2462), 407 }, 408 409 {.regDmnEnum = MKKA, 410 .conformanceTestLimit = MKK, 411 .pscan = PSCAN_MKKA | PSCAN_MKKA_G 412 | PSCAN_MKKA1 | PSCAN_MKKA1_G 413 | PSCAN_MKKA2 | PSCAN_MKKA2_G, 414 .flags = DISALLOW_ADHOC_11A_TURB, 415 .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 416 .chan11g = BM2(G2_2412_2462, G1_2467_2472), 417 .chan11g_turbo = BM1(T2_2437_2437) 418 }, 419 420 {.regDmnEnum = MKKC, 421 .conformanceTestLimit = MKK, 422 .chan11b = BM1(F2_2412_2472), 423 .chan11g = BM1(G2_2412_2472), 424 .chan11g_turbo = BM1(T2_2437_2437) 425 }, 426 427 {.regDmnEnum = WORLD, 428 .conformanceTestLimit = ETSI, 429 .chan11b = BM1(F2_2412_2472), 430 .chan11g = BM1(G2_2412_2472), 431 .chan11g_turbo = BM1(T2_2437_2437) 432 }, 433 434 {.regDmnEnum = WOR0_WORLD, 435 .conformanceTestLimit = NO_CTL, 436 .dfsMask = DFS_FCC3 | DFS_ETSI, 437 .pscan = PSCAN_WWR, 438 .flags = ADHOC_PER_11D, 439 .chan11a = BM5(W1_5260_5320, 440 W1_5180_5240, 441 W1_5170_5230, 442 W1_5745_5825, 443 W1_5500_5700), 444 .chan11a_turbo = BM3(WT1_5210_5250, 445 WT1_5290_5290, 446 WT1_5760_5800), 447 .chan11b = BM8(W1_2412_2412, 448 W1_2437_2442, 449 W1_2462_2462, 450 W1_2472_2472, 451 W1_2417_2432, 452 W1_2447_2457, 453 W1_2467_2467, 454 W1_2484_2484), 455 .chan11g = BM7(WG1_2412_2412, 456 WG1_2437_2442, 457 WG1_2462_2462, 458 WG1_2472_2472, 459 WG1_2417_2432, 460 WG1_2447_2457, 461 WG1_2467_2467), 462 .chan11g_turbo = BM1(T3_2437_2437) 463 }, 464 465 {.regDmnEnum = WOR01_WORLD, 466 .conformanceTestLimit = NO_CTL, 467 .dfsMask = DFS_FCC3 | DFS_ETSI, 468 .pscan = PSCAN_WWR, 469 .flags = ADHOC_PER_11D, 470 .chan11a = BM5(W1_5260_5320, 471 W1_5180_5240, 472 W1_5170_5230, 473 W1_5745_5825, 474 W1_5500_5700), 475 .chan11a_turbo = BM3(WT1_5210_5250, 476 WT1_5290_5290, 477 WT1_5760_5800), 478 .chan11b = BM5(W1_2412_2412, 479 W1_2437_2442, 480 W1_2462_2462, 481 W1_2417_2432, 482 W1_2447_2457), 483 .chan11g = BM5(WG1_2412_2412, 484 WG1_2437_2442, 485 WG1_2462_2462, 486 WG1_2417_2432, 487 WG1_2447_2457), 488 .chan11g_turbo = BM1(T3_2437_2437)}, 489 490 {.regDmnEnum = WOR02_WORLD, 491 .conformanceTestLimit = NO_CTL, 492 .dfsMask = DFS_FCC3 | DFS_ETSI, 493 .pscan = PSCAN_WWR, 494 .flags = ADHOC_PER_11D, 495 .chan11a = BM5(W1_5260_5320, 496 W1_5180_5240, 497 W1_5170_5230, 498 W1_5745_5825, 499 W1_5500_5700), 500 .chan11a_turbo = BM3(WT1_5210_5250, 501 WT1_5290_5290, 502 WT1_5760_5800), 503 .chan11b = BM7(W1_2412_2412, 504 W1_2437_2442, 505 W1_2462_2462, 506 W1_2472_2472, 507 W1_2417_2432, 508 W1_2447_2457, 509 W1_2467_2467), 510 .chan11g = BM7(WG1_2412_2412, 511 WG1_2437_2442, 512 WG1_2462_2462, 513 WG1_2472_2472, 514 WG1_2417_2432, 515 WG1_2447_2457, 516 WG1_2467_2467), 517 .chan11g_turbo = BM1(T3_2437_2437)}, 518 519 {.regDmnEnum = EU1_WORLD, 520 .conformanceTestLimit = NO_CTL, 521 .dfsMask = DFS_FCC3 | DFS_ETSI, 522 .pscan = PSCAN_WWR, 523 .flags = ADHOC_PER_11D, 524 .chan11a = BM5(W1_5260_5320, 525 W1_5180_5240, 526 W1_5170_5230, 527 W1_5745_5825, 528 W1_5500_5700), 529 .chan11a_turbo = BM3(WT1_5210_5250, 530 WT1_5290_5290, 531 WT1_5760_5800), 532 .chan11b = BM7(W1_2412_2412, 533 W1_2437_2442, 534 W1_2462_2462, 535 W2_2472_2472, 536 W1_2417_2432, 537 W1_2447_2457, 538 W2_2467_2467), 539 .chan11g = BM7(WG1_2412_2412, 540 WG1_2437_2442, 541 WG1_2462_2462, 542 WG2_2472_2472, 543 WG1_2417_2432, 544 WG1_2447_2457, 545 WG2_2467_2467), 546 .chan11g_turbo = BM1(T3_2437_2437)}, 547 548 {.regDmnEnum = WOR1_WORLD, 549 .conformanceTestLimit = NO_CTL, 550 .dfsMask = DFS_FCC3 | DFS_ETSI, 551 .pscan = PSCAN_WWR, 552 .flags = DISALLOW_ADHOC_11A, 553 .chan11a = BM5(W1_5260_5320, 554 W1_5180_5240, 555 W1_5170_5230, 556 W1_5745_5825, 557 W1_5500_5700), 558 .chan11b = BM8(W1_2412_2412, 559 W1_2437_2442, 560 W1_2462_2462, 561 W1_2472_2472, 562 W1_2417_2432, 563 W1_2447_2457, 564 W1_2467_2467, 565 W1_2484_2484), 566 .chan11g = BM7(WG1_2412_2412, 567 WG1_2437_2442, 568 WG1_2462_2462, 569 WG1_2472_2472, 570 WG1_2417_2432, 571 WG1_2447_2457, 572 WG1_2467_2467), 573 .chan11g_turbo = BM1(T3_2437_2437) 574 }, 575 576 {.regDmnEnum = WOR2_WORLD, 577 .conformanceTestLimit = NO_CTL, 578 .dfsMask = DFS_FCC3 | DFS_ETSI, 579 .pscan = PSCAN_WWR, 580 .flags = DISALLOW_ADHOC_11A, 581 .chan11a = BM5(W1_5260_5320, 582 W1_5180_5240, 583 W1_5170_5230, 584 W1_5745_5825, 585 W1_5500_5700), 586 .chan11a_turbo = BM3(WT1_5210_5250, 587 WT1_5290_5290, 588 WT1_5760_5800), 589 .chan11b = BM8(W1_2412_2412, 590 W1_2437_2442, 591 W1_2462_2462, 592 W1_2472_2472, 593 W1_2417_2432, 594 W1_2447_2457, 595 W1_2467_2467, 596 W1_2484_2484), 597 .chan11g = BM7(WG1_2412_2412, 598 WG1_2437_2442, 599 WG1_2462_2462, 600 WG1_2472_2472, 601 WG1_2417_2432, 602 WG1_2447_2457, 603 WG1_2467_2467), 604 .chan11g_turbo = BM1(T3_2437_2437)}, 605 606 {.regDmnEnum = WOR3_WORLD, 607 .conformanceTestLimit = NO_CTL, 608 .dfsMask = DFS_FCC3 | DFS_ETSI, 609 .pscan = PSCAN_WWR, 610 .flags = ADHOC_PER_11D, 611 .chan11a = BM4(W1_5260_5320, 612 W1_5180_5240, 613 W1_5170_5230, 614 W1_5745_5825), 615 .chan11a_turbo = BM3(WT1_5210_5250, 616 WT1_5290_5290, 617 WT1_5760_5800), 618 .chan11b = BM7(W1_2412_2412, 619 W1_2437_2442, 620 W1_2462_2462, 621 W1_2472_2472, 622 W1_2417_2432, 623 W1_2447_2457, 624 W1_2467_2467), 625 .chan11g = BM7(WG1_2412_2412, 626 WG1_2437_2442, 627 WG1_2462_2462, 628 WG1_2472_2472, 629 WG1_2417_2432, 630 WG1_2447_2457, 631 WG1_2467_2467), 632 .chan11g_turbo = BM1(T3_2437_2437)}, 633 634 {.regDmnEnum = WOR4_WORLD, 635 .conformanceTestLimit = NO_CTL, 636 .dfsMask = DFS_FCC3 | DFS_ETSI, 637 .pscan = PSCAN_WWR, 638 .flags = DISALLOW_ADHOC_11A, 639 .chan11a = BM4(W2_5260_5320, 640 W2_5180_5240, 641 F2_5745_5805, 642 W2_5825_5825), 643 .chan11a_turbo = BM3(WT1_5210_5250, 644 WT1_5290_5290, 645 WT1_5760_5800), 646 .chan11b = BM5(W1_2412_2412, 647 W1_2437_2442, 648 W1_2462_2462, 649 W1_2417_2432, 650 W1_2447_2457), 651 .chan11g = BM5(WG1_2412_2412, 652 WG1_2437_2442, 653 WG1_2462_2462, 654 WG1_2417_2432, 655 WG1_2447_2457), 656 .chan11g_turbo = BM1(T3_2437_2437)}, 657 658 {.regDmnEnum = WOR5_ETSIC, 659 .conformanceTestLimit = NO_CTL, 660 .dfsMask = DFS_FCC3 | DFS_ETSI, 661 .pscan = PSCAN_WWR, 662 .flags = DISALLOW_ADHOC_11A, 663 .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 664 .chan11b = BM7(W1_2412_2412, 665 W1_2437_2442, 666 W1_2462_2462, 667 W2_2472_2472, 668 W1_2417_2432, 669 W1_2447_2457, 670 W2_2467_2467), 671 .chan11g = BM7(WG1_2412_2412, 672 WG1_2437_2442, 673 WG1_2462_2462, 674 WG2_2472_2472, 675 WG1_2417_2432, 676 WG1_2447_2457, 677 WG2_2467_2467), 678 .chan11g_turbo = BM1(T3_2437_2437)}, 679 680 {.regDmnEnum = WOR9_WORLD, 681 .conformanceTestLimit = NO_CTL, 682 .dfsMask = DFS_FCC3 | DFS_ETSI, 683 .pscan = PSCAN_WWR, 684 .flags = DISALLOW_ADHOC_11A, 685 .chan11a = BM4(W1_5260_5320, 686 W1_5180_5240, 687 W1_5745_5825, 688 W1_5500_5700), 689 .chan11a_turbo = BM3(WT1_5210_5250, 690 WT1_5290_5290, 691 WT1_5760_5800), 692 .chan11b = BM5(W1_2412_2412, 693 W1_2437_2442, 694 W1_2462_2462, 695 W1_2417_2432, 696 W1_2447_2457), 697 .chan11g = BM5(WG1_2412_2412, 698 WG1_2437_2442, 699 WG1_2462_2462, 700 WG1_2417_2432, 701 WG1_2447_2457), 702 .chan11g_turbo = BM1(T3_2437_2437)}, 703 704 {.regDmnEnum = WORA_WORLD, 705 .conformanceTestLimit = NO_CTL, 706 .dfsMask = DFS_FCC3 | DFS_ETSI, 707 .pscan = PSCAN_WWR, 708 .flags = DISALLOW_ADHOC_11A, 709 .chan11a = BM4(W1_5260_5320, 710 W1_5180_5240, 711 W1_5745_5825, 712 W1_5500_5700), 713 .chan11b = BM7(W1_2412_2412, 714 W1_2437_2442, 715 W1_2462_2462, 716 W1_2472_2472, 717 W1_2417_2432, 718 W1_2447_2457, 719 W1_2467_2467), 720 .chan11g = BM7(WG1_2412_2412, 721 WG1_2437_2442, 722 WG1_2462_2462, 723 WG1_2472_2472, 724 WG1_2417_2432, 725 WG1_2447_2457, 726 WG1_2467_2467), 727 .chan11g_turbo = BM1(T3_2437_2437)}, 728 729 {.regDmnEnum = WORB_WORLD, 730 .conformanceTestLimit = NO_CTL, 731 .dfsMask = DFS_FCC3 | DFS_ETSI, 732 .pscan = PSCAN_WWR, 733 .flags = DISALLOW_ADHOC_11A, 734 .chan11a = BM4(W1_5260_5320, 735 W1_5180_5240, 736 W1_5745_5825, 737 W1_5500_5700), 738 .chan11b = BM7(W1_2412_2412, 739 W1_2437_2442, 740 W1_2462_2462, 741 W1_2472_2472, 742 W1_2417_2432, 743 W1_2447_2457, 744 W1_2467_2467), 745 .chan11g = BM7(WG1_2412_2412, 746 WG1_2437_2442, 747 WG1_2462_2462, 748 WG1_2472_2472, 749 WG1_2417_2432, 750 WG1_2447_2457, 751 WG1_2467_2467), 752 .chan11g_turbo = BM1(T3_2437_2437)}, 753 754 {.regDmnEnum = WORC_WORLD, 755 .conformanceTestLimit = NO_CTL, 756 .dfsMask = DFS_FCC3 | DFS_ETSI, 757 .pscan = PSCAN_WWR, 758 .flags = ADHOC_PER_11D, 759 .chan11a = BM4(W1_5260_5320, 760 W1_5180_5240, 761 W1_5745_5825, 762 W1_5500_5700), 763 .chan11b = BM7(W1_2412_2412, 764 W1_2437_2442, 765 W1_2462_2462, 766 W1_2472_2472, 767 W1_2417_2432, 768 W1_2447_2457, 769 W1_2467_2467), 770 .chan11g = BM7(WG1_2412_2412, 771 WG1_2437_2442, 772 WG1_2462_2462, 773 WG1_2472_2472, 774 WG1_2417_2432, 775 WG1_2447_2457, 776 WG1_2467_2467), 777 .chan11g_turbo = BM1(T3_2437_2437)}, 778 779 {.regDmnEnum = NULL1, 780 .conformanceTestLimit = NO_CTL, 781 } 782 }; 783 784 #endif 785