1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
4
5 #include <linux/bits.h>
6 #include <linux/cleanup.h>
7 #include <linux/err.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/irqhandler.h>
11 #include <linux/lockdep.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/pinctrl/pinctrl.h>
14 #include <linux/property.h>
15 #include <linux/spinlock_types.h>
16 #include <linux/types.h>
17 #include <linux/util_macros.h>
18
19 #ifdef CONFIG_GENERIC_MSI_IRQ
20 #include <asm/msi.h>
21 #endif
22
23 struct device;
24 struct irq_chip;
25 struct irq_data;
26 struct module;
27 struct of_phandle_args;
28 struct pinctrl_dev;
29 struct seq_file;
30
31 struct gpio_chip;
32 struct gpio_desc;
33 struct gpio_device;
34
35 enum gpio_lookup_flags;
36 enum gpiod_flags;
37
38 union gpio_irq_fwspec {
39 struct irq_fwspec fwspec;
40 #ifdef CONFIG_GENERIC_MSI_IRQ
41 msi_alloc_info_t msiinfo;
42 #endif
43 };
44
45 #define GPIO_LINE_DIRECTION_IN 1
46 #define GPIO_LINE_DIRECTION_OUT 0
47
48 /**
49 * struct gpio_irq_chip - GPIO interrupt controller
50 */
51 struct gpio_irq_chip {
52 /**
53 * @chip:
54 *
55 * GPIO IRQ chip implementation, provided by GPIO driver.
56 */
57 struct irq_chip *chip;
58
59 /**
60 * @domain:
61 *
62 * Interrupt translation domain; responsible for mapping between GPIO
63 * hwirq number and Linux IRQ number.
64 */
65 struct irq_domain *domain;
66
67 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
68 /**
69 * @fwnode:
70 *
71 * Firmware node corresponding to this gpiochip/irqchip, necessary
72 * for hierarchical irqdomain support.
73 */
74 struct fwnode_handle *fwnode;
75
76 /**
77 * @parent_domain:
78 *
79 * If non-NULL, will be set as the parent of this GPIO interrupt
80 * controller's IRQ domain to establish a hierarchical interrupt
81 * domain. The presence of this will activate the hierarchical
82 * interrupt support.
83 */
84 struct irq_domain *parent_domain;
85
86 /**
87 * @child_to_parent_hwirq:
88 *
89 * This callback translates a child hardware IRQ offset to a parent
90 * hardware IRQ offset on a hierarchical interrupt chip. The child
91 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
92 * ngpio field of struct gpio_chip) and the corresponding parent
93 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
94 * the driver. The driver can calculate this from an offset or using
95 * a lookup table or whatever method is best for this chip. Return
96 * 0 on successful translation in the driver.
97 *
98 * If some ranges of hardware IRQs do not have a corresponding parent
99 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
100 * @need_valid_mask to make these GPIO lines unavailable for
101 * translation.
102 */
103 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
104 unsigned int child_hwirq,
105 unsigned int child_type,
106 unsigned int *parent_hwirq,
107 unsigned int *parent_type);
108
109 /**
110 * @populate_parent_alloc_arg :
111 *
112 * This optional callback allocates and populates the specific struct
113 * for the parent's IRQ domain. If this is not specified, then
114 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
115 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
116 * available.
117 */
118 int (*populate_parent_alloc_arg)(struct gpio_chip *gc,
119 union gpio_irq_fwspec *fwspec,
120 unsigned int parent_hwirq,
121 unsigned int parent_type);
122
123 /**
124 * @child_offset_to_irq:
125 *
126 * This optional callback is used to translate the child's GPIO line
127 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
128 * callback. If this is not specified, then a default callback will be
129 * provided that returns the line offset.
130 */
131 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
132 unsigned int pin);
133
134 /**
135 * @child_irq_domain_ops:
136 *
137 * The IRQ domain operations that will be used for this GPIO IRQ
138 * chip. If no operations are provided, then default callbacks will
139 * be populated to setup the IRQ hierarchy. Some drivers need to
140 * supply their own translate function.
141 */
142 struct irq_domain_ops child_irq_domain_ops;
143 #endif
144
145 /**
146 * @handler:
147 *
148 * The IRQ handler to use (often a predefined IRQ core function) for
149 * GPIO IRQs, provided by GPIO driver.
150 */
151 irq_flow_handler_t handler;
152
153 /**
154 * @default_type:
155 *
156 * Default IRQ triggering type applied during GPIO driver
157 * initialization, provided by GPIO driver.
158 */
159 unsigned int default_type;
160
161 /**
162 * @lock_key:
163 *
164 * Per GPIO IRQ chip lockdep class for IRQ lock.
165 */
166 struct lock_class_key *lock_key;
167
168 /**
169 * @request_key:
170 *
171 * Per GPIO IRQ chip lockdep class for IRQ request.
172 */
173 struct lock_class_key *request_key;
174
175 /**
176 * @parent_handler:
177 *
178 * The interrupt handler for the GPIO chip's parent interrupts, may be
179 * NULL if the parent interrupts are nested rather than cascaded.
180 */
181 irq_flow_handler_t parent_handler;
182
183 union {
184 /**
185 * @parent_handler_data:
186 *
187 * If @per_parent_data is false, @parent_handler_data is a
188 * single pointer used as the data associated with every
189 * parent interrupt.
190 */
191 void *parent_handler_data;
192
193 /**
194 * @parent_handler_data_array:
195 *
196 * If @per_parent_data is true, @parent_handler_data_array is
197 * an array of @num_parents pointers, and is used to associate
198 * different data for each parent. This cannot be NULL if
199 * @per_parent_data is true.
200 */
201 void **parent_handler_data_array;
202 };
203
204 /**
205 * @num_parents:
206 *
207 * The number of interrupt parents of a GPIO chip.
208 */
209 unsigned int num_parents;
210
211 /**
212 * @parents:
213 *
214 * A list of interrupt parents of a GPIO chip. This is owned by the
215 * driver, so the core will only reference this list, not modify it.
216 */
217 unsigned int *parents;
218
219 /**
220 * @map:
221 *
222 * A list of interrupt parents for each line of a GPIO chip.
223 */
224 unsigned int *map;
225
226 /**
227 * @threaded:
228 *
229 * True if set the interrupt handling uses nested threads.
230 */
231 bool threaded;
232
233 /**
234 * @per_parent_data:
235 *
236 * True if parent_handler_data_array describes a @num_parents
237 * sized array to be used as parent data.
238 */
239 bool per_parent_data;
240
241 /**
242 * @initialized:
243 *
244 * Flag to track GPIO chip irq member's initialization.
245 * This flag will make sure GPIO chip irq members are not used
246 * before they are initialized.
247 */
248 bool initialized;
249
250 /**
251 * @domain_is_allocated_externally:
252 *
253 * True it the irq_domain was allocated outside of gpiolib, in which
254 * case gpiolib won't free the irq_domain itself.
255 */
256 bool domain_is_allocated_externally;
257
258 /**
259 * @init_hw: optional routine to initialize hardware before
260 * an IRQ chip will be added. This is quite useful when
261 * a particular driver wants to clear IRQ related registers
262 * in order to avoid undesired events.
263 */
264 int (*init_hw)(struct gpio_chip *gc);
265
266 /**
267 * @init_valid_mask: optional routine to initialize @valid_mask, to be
268 * used if not all GPIO lines are valid interrupts. Sometimes some
269 * lines just cannot fire interrupts, and this routine, when defined,
270 * is passed a bitmap in "valid_mask" and it will have ngpios
271 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
272 * then directly set some bits to "0" if they cannot be used for
273 * interrupts.
274 */
275 void (*init_valid_mask)(struct gpio_chip *gc,
276 unsigned long *valid_mask,
277 unsigned int ngpios);
278
279 /**
280 * @valid_mask:
281 *
282 * If not %NULL, holds bitmask of GPIOs which are valid to be included
283 * in IRQ domain of the chip.
284 */
285 unsigned long *valid_mask;
286
287 /**
288 * @first:
289 *
290 * Required for static IRQ allocation. If set,
291 * irq_domain_create_simple() will allocate and map all IRQs
292 * during initialization.
293 */
294 unsigned int first;
295
296 /**
297 * @irq_enable:
298 *
299 * Store old irq_chip irq_enable callback
300 */
301 void (*irq_enable)(struct irq_data *data);
302
303 /**
304 * @irq_disable:
305 *
306 * Store old irq_chip irq_disable callback
307 */
308 void (*irq_disable)(struct irq_data *data);
309 /**
310 * @irq_unmask:
311 *
312 * Store old irq_chip irq_unmask callback
313 */
314 void (*irq_unmask)(struct irq_data *data);
315
316 /**
317 * @irq_mask:
318 *
319 * Store old irq_chip irq_mask callback
320 */
321 void (*irq_mask)(struct irq_data *data);
322 };
323
324 /**
325 * struct gpio_chip - abstract a GPIO controller
326 * @label: a functional name for the GPIO device, such as a part
327 * number or the name of the SoC IP-block implementing it.
328 * @gpiodev: the internal state holder, opaque struct
329 * @parent: optional parent device providing the GPIOs
330 * @fwnode: optional fwnode providing this controller's properties
331 * @owner: helps prevent removal of modules exporting active GPIOs
332 * @request: optional hook for chip-specific activation, such as
333 * enabling module power and clock; may sleep; must return 0 on success
334 * or negative error number on failure
335 * @free: optional hook for chip-specific deactivation, such as
336 * disabling module power and clock; may sleep
337 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
338 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
339 * or negative error. It is recommended to always implement this
340 * function, even on input-only or output-only gpio chips.
341 * @direction_input: configures signal "offset" as input, returns 0 on success
342 * or a negative error number. This can be omitted on input-only or
343 * output-only gpio chips.
344 * @direction_output: configures signal "offset" as output, returns 0 on
345 * success or a negative error number. This can be omitted on input-only
346 * or output-only gpio chips.
347 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
348 * @get_multiple: reads values for multiple signals defined by "mask" and
349 * stores them in "bits", returns 0 on success or negative error
350 * @set: **DEPRECATED** - please use set_rv() instead
351 * @set_multiple: **DEPRECATED** - please use set_multiple_rv() instead
352 * @set_rv: assigns output value for signal "offset", returns 0 on success or
353 * negative error value
354 * @set_multiple_rv: assigns output values for multiple signals defined by
355 * "mask", returns 0 on success or negative error value
356 * @set_config: optional hook for all kinds of settings. Uses the same
357 * packed config format as generic pinconf. Must return 0 on success and
358 * a negative error number on failure.
359 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings;
360 * implementation may not sleep
361 * @dbg_show: optional routine to show contents in debugfs; default code
362 * will be used when this is omitted, but custom code can show extra
363 * state (such as pullup/pulldown configuration).
364 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
365 * not all GPIOs are valid.
366 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
367 * requires special mapping of the pins that provides GPIO functionality.
368 * It is called after adding GPIO chip and before adding IRQ chip.
369 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to
370 * enable hardware timestamp.
371 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to
372 * disable hardware timestamp.
373 * @base: identifies the first GPIO number handled by this chip;
374 * or, if negative during registration, requests dynamic ID allocation.
375 * DEPRECATION: providing anything non-negative and nailing the base
376 * offset of GPIO chips is deprecated. Please pass -1 as base to
377 * let gpiolib select the chip base in all possible cases. We want to
378 * get rid of the static GPIO number space in the long run.
379 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
380 * handled is (base + ngpio - 1).
381 * @offset: when multiple gpio chips belong to the same device this
382 * can be used as offset within the device so friendly names can
383 * be properly assigned.
384 * @names: if set, must be an array of strings to use as alternative
385 * names for the GPIOs in this chip. Any entry in the array
386 * may be NULL if there is no alias for the GPIO, however the
387 * array must be @ngpio entries long.
388 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
389 * must while accessing GPIO expander chips over I2C or SPI. This
390 * implies that if the chip supports IRQs, these IRQs need to be threaded
391 * as the chip access may sleep when e.g. reading out the IRQ status
392 * registers.
393 * @read_reg: reader function for generic GPIO
394 * @write_reg: writer function for generic GPIO
395 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
396 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
397 * generic GPIO core. It is for internal housekeeping only.
398 * @reg_dat: data (in) register for generic GPIO
399 * @reg_set: output set register (out=high) for generic GPIO
400 * @reg_clr: output clear register (out=low) for generic GPIO
401 * @reg_dir_out: direction out setting register for generic GPIO
402 * @reg_dir_in: direction in setting register for generic GPIO
403 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
404 * be read and we need to rely on out internal state tracking.
405 * @bgpio_pinctrl: the generic GPIO uses a pin control backend.
406 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
407 * <register width> * 8
408 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
409 * shadowed and real data registers writes together.
410 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
411 * safely.
412 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
413 * direction safely. A "1" in this word means the line is set as
414 * output.
415 *
416 * A gpio_chip can help platforms abstract various sources of GPIOs so
417 * they can all be accessed through a common programming interface.
418 * Example sources would be SOC controllers, FPGAs, multifunction
419 * chips, dedicated GPIO expanders, and so on.
420 *
421 * Each chip controls a number of signals, identified in method calls
422 * by "offset" values in the range 0..(@ngpio - 1). When those signals
423 * are referenced through calls like gpio_get_value(gpio), the offset
424 * is calculated by subtracting @base from the gpio number.
425 */
426 struct gpio_chip {
427 const char *label;
428 struct gpio_device *gpiodev;
429 struct device *parent;
430 struct fwnode_handle *fwnode;
431 struct module *owner;
432
433 int (*request)(struct gpio_chip *gc,
434 unsigned int offset);
435 void (*free)(struct gpio_chip *gc,
436 unsigned int offset);
437 int (*get_direction)(struct gpio_chip *gc,
438 unsigned int offset);
439 int (*direction_input)(struct gpio_chip *gc,
440 unsigned int offset);
441 int (*direction_output)(struct gpio_chip *gc,
442 unsigned int offset, int value);
443 int (*get)(struct gpio_chip *gc,
444 unsigned int offset);
445 int (*get_multiple)(struct gpio_chip *gc,
446 unsigned long *mask,
447 unsigned long *bits);
448 void (*set)(struct gpio_chip *gc,
449 unsigned int offset, int value);
450 void (*set_multiple)(struct gpio_chip *gc,
451 unsigned long *mask,
452 unsigned long *bits);
453 int (*set_rv)(struct gpio_chip *gc,
454 unsigned int offset,
455 int value);
456 int (*set_multiple_rv)(struct gpio_chip *gc,
457 unsigned long *mask,
458 unsigned long *bits);
459 int (*set_config)(struct gpio_chip *gc,
460 unsigned int offset,
461 unsigned long config);
462 int (*to_irq)(struct gpio_chip *gc,
463 unsigned int offset);
464
465 void (*dbg_show)(struct seq_file *s,
466 struct gpio_chip *gc);
467
468 int (*init_valid_mask)(struct gpio_chip *gc,
469 unsigned long *valid_mask,
470 unsigned int ngpios);
471
472 int (*add_pin_ranges)(struct gpio_chip *gc);
473
474 int (*en_hw_timestamp)(struct gpio_chip *gc,
475 u32 offset,
476 unsigned long flags);
477 int (*dis_hw_timestamp)(struct gpio_chip *gc,
478 u32 offset,
479 unsigned long flags);
480 int base;
481 u16 ngpio;
482 u16 offset;
483 const char *const *names;
484 bool can_sleep;
485
486 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
487 unsigned long (*read_reg)(void __iomem *reg);
488 void (*write_reg)(void __iomem *reg, unsigned long data);
489 bool be_bits;
490 void __iomem *reg_dat;
491 void __iomem *reg_set;
492 void __iomem *reg_clr;
493 void __iomem *reg_dir_out;
494 void __iomem *reg_dir_in;
495 bool bgpio_dir_unreadable;
496 bool bgpio_pinctrl;
497 int bgpio_bits;
498 raw_spinlock_t bgpio_lock;
499 unsigned long bgpio_data;
500 unsigned long bgpio_dir;
501 #endif /* CONFIG_GPIO_GENERIC */
502
503 #ifdef CONFIG_GPIOLIB_IRQCHIP
504 /*
505 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
506 * to handle IRQs for most practical cases.
507 */
508
509 /**
510 * @irq:
511 *
512 * Integrates interrupt chip functionality with the GPIO chip. Can be
513 * used to handle IRQs for most practical cases.
514 */
515 struct gpio_irq_chip irq;
516 #endif /* CONFIG_GPIOLIB_IRQCHIP */
517
518 #if defined(CONFIG_OF_GPIO)
519 /*
520 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
521 * the device tree automatically may have an OF translation
522 */
523
524 /**
525 * @of_gpio_n_cells:
526 *
527 * Number of cells used to form the GPIO specifier. The standard is 2
528 * cells:
529 *
530 * gpios = <&gpio offset flags>;
531 *
532 * some complex GPIO controllers instantiate more than one chip per
533 * device tree node and have 3 cells:
534 *
535 * gpios = <&gpio instance offset flags>;
536 *
537 * Legacy GPIO controllers may even have 1 cell:
538 *
539 * gpios = <&gpio offset>;
540 */
541 unsigned int of_gpio_n_cells;
542
543 /**
544 * @of_node_instance_match:
545 *
546 * Determine if a chip is the right instance. Must be implemented by
547 * any driver using more than one gpio_chip per device tree node.
548 * Returns true if gc is the instance indicated by i (which is the
549 * first cell in the phandles for GPIO lines and gpio-ranges).
550 */
551 bool (*of_node_instance_match)(struct gpio_chip *gc, unsigned int i);
552
553 /**
554 * @of_xlate:
555 *
556 * Callback to translate a device tree GPIO specifier into a chip-
557 * relative GPIO number and flags.
558 */
559 int (*of_xlate)(struct gpio_chip *gc,
560 const struct of_phandle_args *gpiospec, u32 *flags);
561 #endif /* CONFIG_OF_GPIO */
562 };
563
564 char *gpiochip_dup_line_label(struct gpio_chip *gc, unsigned int offset);
565
566
567 struct _gpiochip_for_each_data {
568 const char **label;
569 unsigned int *i;
570 };
571
572 DEFINE_CLASS(_gpiochip_for_each_data,
573 struct _gpiochip_for_each_data,
574 if (*_T.label) kfree(*_T.label),
575 ({
576 struct _gpiochip_for_each_data _data = { label, i };
577 *_data.i = 0;
578 _data;
579 }),
580 const char **label, int *i)
581
582 /**
583 * for_each_hwgpio_in_range - Iterates over all GPIOs in a given range
584 * @_chip: Chip to iterate over.
585 * @_i: Loop counter.
586 * @_base: First GPIO in the ranger.
587 * @_size: Amount of GPIOs to check starting from @base.
588 * @_label: Place to store the address of the label if the GPIO is requested.
589 * Set to NULL for unused GPIOs.
590 */
591 #define for_each_hwgpio_in_range(_chip, _i, _base, _size, _label) \
592 for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \
593 _i < _size; \
594 _i++, kfree(_label), _label = NULL) \
595 for_each_if(!IS_ERR(_label = gpiochip_dup_line_label(_chip, _base + _i)))
596
597 /**
598 * for_each_hwgpio - Iterates over all GPIOs for given chip.
599 * @_chip: Chip to iterate over.
600 * @_i: Loop counter.
601 * @_label: Place to store the address of the label if the GPIO is requested.
602 * Set to NULL for unused GPIOs.
603 */
604 #define for_each_hwgpio(_chip, _i, _label) \
605 for_each_hwgpio_in_range(_chip, _i, 0, _chip->ngpio, _label)
606
607 /**
608 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
609 * @_chip: the chip to query
610 * @_i: loop variable
611 * @_base: first GPIO in the range
612 * @_size: amount of GPIOs to check starting from @base
613 * @_label: label of current GPIO
614 */
615 #define for_each_requested_gpio_in_range(_chip, _i, _base, _size, _label) \
616 for_each_hwgpio_in_range(_chip, _i, _base, _size, _label) \
617 for_each_if(_label)
618
619 /* Iterates over all requested GPIO of the given @chip */
620 #define for_each_requested_gpio(chip, i, label) \
621 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
622
623 /* add/remove chips */
624 int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
625 struct lock_class_key *lock_key,
626 struct lock_class_key *request_key);
627
628 /**
629 * gpiochip_add_data() - register a gpio_chip
630 * @gc: the chip to register, with gc->base initialized
631 * @data: driver-private data associated with this chip
632 *
633 * Context: potentially before irqs will work
634 *
635 * When gpiochip_add_data() is called very early during boot, so that GPIOs
636 * can be freely used, the gc->parent device must be registered before
637 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
638 * for GPIOs will fail rudely.
639 *
640 * gpiochip_add_data() must only be called after gpiolib initialization,
641 * i.e. after core_initcall().
642 *
643 * If gc->base is negative, this requests dynamic assignment of
644 * a range of valid GPIOs.
645 *
646 * Returns:
647 * A negative errno if the chip can't be registered, such as because the
648 * gc->base is invalid or already associated with a different chip.
649 * Otherwise it returns zero as a success code.
650 */
651 #ifdef CONFIG_LOCKDEP
652 #define gpiochip_add_data(gc, data) ({ \
653 static struct lock_class_key lock_key; \
654 static struct lock_class_key request_key; \
655 gpiochip_add_data_with_key(gc, data, &lock_key, \
656 &request_key); \
657 })
658 #define devm_gpiochip_add_data(dev, gc, data) ({ \
659 static struct lock_class_key lock_key; \
660 static struct lock_class_key request_key; \
661 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
662 &request_key); \
663 })
664 #else
665 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
666 #define devm_gpiochip_add_data(dev, gc, data) \
667 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
668 #endif /* CONFIG_LOCKDEP */
669
670 void gpiochip_remove(struct gpio_chip *gc);
671 int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc,
672 void *data, struct lock_class_key *lock_key,
673 struct lock_class_key *request_key);
674
675 struct gpio_device *gpio_device_find(const void *data,
676 int (*match)(struct gpio_chip *gc,
677 const void *data));
678
679 struct gpio_device *gpio_device_get(struct gpio_device *gdev);
680 void gpio_device_put(struct gpio_device *gdev);
681
682 DEFINE_FREE(gpio_device_put, struct gpio_device *,
683 if (!IS_ERR_OR_NULL(_T)) gpio_device_put(_T))
684
685 struct device *gpio_device_to_device(struct gpio_device *gdev);
686
687 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
688 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
689 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
690 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
691 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
692
693 /* irq_data versions of the above */
694 int gpiochip_irq_reqres(struct irq_data *data);
695 void gpiochip_irq_relres(struct irq_data *data);
696
697 /* Paste this in your irq_chip structure */
698 #define GPIOCHIP_IRQ_RESOURCE_HELPERS \
699 .irq_request_resources = gpiochip_irq_reqres, \
700 .irq_release_resources = gpiochip_irq_relres
701
gpio_irq_chip_set_chip(struct gpio_irq_chip * girq,const struct irq_chip * chip)702 static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq,
703 const struct irq_chip *chip)
704 {
705 /* Yes, dropping const is ugly, but it isn't like we have a choice */
706 girq->chip = (struct irq_chip *)chip;
707 }
708
709 /* Line status inquiry for drivers */
710 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
711 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
712
713 /* Sleep persistence inquiry for drivers */
714 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
715 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
716 const unsigned long *gpiochip_query_valid_mask(const struct gpio_chip *gc);
717
718 /* get driver data */
719 void *gpiochip_get_data(struct gpio_chip *gc);
720
721 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
722
723 int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
724 union gpio_irq_fwspec *gfwspec,
725 unsigned int parent_hwirq,
726 unsigned int parent_type);
727 int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
728 union gpio_irq_fwspec *gfwspec,
729 unsigned int parent_hwirq,
730 unsigned int parent_type);
731
732 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
733
734 int bgpio_init(struct gpio_chip *gc, struct device *dev,
735 unsigned long sz, void __iomem *dat, void __iomem *set,
736 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
737 unsigned long flags);
738
739 #define BGPIOF_BIG_ENDIAN BIT(0)
740 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
741 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
742 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
743 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
744 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
745 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
746 #define BGPIOF_PINCTRL_BACKEND BIT(7) /* Call pinctrl direction setters */
747 #define BGPIOF_NO_INPUT BIT(8) /* only output */
748
749 #ifdef CONFIG_GPIOLIB_IRQCHIP
750 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
751 struct irq_domain *domain);
752 #else
753
754 #include <asm/bug.h>
755
gpiochip_irqchip_add_domain(struct gpio_chip * gc,struct irq_domain * domain)756 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
757 struct irq_domain *domain)
758 {
759 WARN_ON(1);
760 return -EINVAL;
761 }
762 #endif
763
764 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
765 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
766 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
767 unsigned long config);
768
769 /**
770 * struct gpio_pin_range - pin range controlled by a gpio chip
771 * @node: list for maintaining set of pin ranges, used internally
772 * @pctldev: pinctrl device which handles corresponding pins
773 * @range: actual range of pins controlled by a gpio controller
774 */
775 struct gpio_pin_range {
776 struct list_head node;
777 struct pinctrl_dev *pctldev;
778 struct pinctrl_gpio_range range;
779 };
780
781 #ifdef CONFIG_PINCTRL
782
783 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
784 unsigned int gpio_offset, unsigned int pin_offset,
785 unsigned int npins);
786 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
787 struct pinctrl_dev *pctldev,
788 unsigned int gpio_offset, const char *pin_group);
789 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
790
791 #else /* ! CONFIG_PINCTRL */
792
793 static inline int
gpiochip_add_pin_range(struct gpio_chip * gc,const char * pinctl_name,unsigned int gpio_offset,unsigned int pin_offset,unsigned int npins)794 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
795 unsigned int gpio_offset, unsigned int pin_offset,
796 unsigned int npins)
797 {
798 return 0;
799 }
800 static inline int
gpiochip_add_pingroup_range(struct gpio_chip * gc,struct pinctrl_dev * pctldev,unsigned int gpio_offset,const char * pin_group)801 gpiochip_add_pingroup_range(struct gpio_chip *gc,
802 struct pinctrl_dev *pctldev,
803 unsigned int gpio_offset, const char *pin_group)
804 {
805 return 0;
806 }
807
808 static inline void
gpiochip_remove_pin_ranges(struct gpio_chip * gc)809 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
810 {
811 }
812
813 #endif /* CONFIG_PINCTRL */
814
815 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
816 unsigned int hwnum,
817 const char *label,
818 enum gpio_lookup_flags lflags,
819 enum gpiod_flags dflags);
820 void gpiochip_free_own_desc(struct gpio_desc *desc);
821
822 struct gpio_desc *
823 gpio_device_get_desc(struct gpio_device *gdev, unsigned int hwnum);
824
825 struct gpio_chip *gpio_device_get_chip(struct gpio_device *gdev);
826
827 #ifdef CONFIG_GPIOLIB
828
829 /* lock/unlock as IRQ */
830 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
831 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
832
833 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
834 struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc);
835
836 /* struct gpio_device getters */
837 int gpio_device_get_base(struct gpio_device *gdev);
838 const char *gpio_device_get_label(struct gpio_device *gdev);
839
840 struct gpio_device *gpio_device_find_by_label(const char *label);
841 struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode);
842
843 #else /* CONFIG_GPIOLIB */
844
845 #include <asm/bug.h>
846
gpiod_to_chip(const struct gpio_desc * desc)847 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
848 {
849 /* GPIO can never have been requested */
850 WARN_ON(1);
851 return ERR_PTR(-ENODEV);
852 }
853
gpiod_to_gpio_device(struct gpio_desc * desc)854 static inline struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc)
855 {
856 WARN_ON(1);
857 return ERR_PTR(-ENODEV);
858 }
859
gpio_device_get_base(struct gpio_device * gdev)860 static inline int gpio_device_get_base(struct gpio_device *gdev)
861 {
862 WARN_ON(1);
863 return -ENODEV;
864 }
865
gpio_device_get_label(struct gpio_device * gdev)866 static inline const char *gpio_device_get_label(struct gpio_device *gdev)
867 {
868 WARN_ON(1);
869 return NULL;
870 }
871
gpio_device_find_by_label(const char * label)872 static inline struct gpio_device *gpio_device_find_by_label(const char *label)
873 {
874 WARN_ON(1);
875 return NULL;
876 }
877
gpio_device_find_by_fwnode(const struct fwnode_handle * fwnode)878 static inline struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode)
879 {
880 WARN_ON(1);
881 return NULL;
882 }
883
gpiochip_lock_as_irq(struct gpio_chip * gc,unsigned int offset)884 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
885 unsigned int offset)
886 {
887 WARN_ON(1);
888 return -EINVAL;
889 }
890
gpiochip_unlock_as_irq(struct gpio_chip * gc,unsigned int offset)891 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
892 unsigned int offset)
893 {
894 WARN_ON(1);
895 }
896 #endif /* CONFIG_GPIOLIB */
897
898 #define for_each_gpiochip_node(dev, child) \
899 device_for_each_child_node(dev, child) \
900 for_each_if(fwnode_property_present(child, "gpio-controller"))
901
gpiochip_node_count(struct device * dev)902 static inline unsigned int gpiochip_node_count(struct device *dev)
903 {
904 struct fwnode_handle *child;
905 unsigned int count = 0;
906
907 for_each_gpiochip_node(dev, child)
908 count++;
909
910 return count;
911 }
912
gpiochip_node_get_first(struct device * dev)913 static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev)
914 {
915 struct fwnode_handle *fwnode;
916
917 for_each_gpiochip_node(dev, fwnode)
918 return fwnode;
919
920 return NULL;
921 }
922
923 #endif /* __LINUX_GPIO_DRIVER_H */
924