1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Stuart Walsh 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _BFE_H 29 #define _BFE_H 30 31 /* PCI registers */ 32 #define BFE_PCI_MEMLO 0x10 33 #define BFE_PCI_MEMHIGH 0x14 34 #define BFE_PCI_INTLINE 0x3C 35 36 /* Register layout. */ 37 #define BFE_DEVCTRL 0x00000000 /* Device Control */ 38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */ 39 #define BFE_IPP 0x00000400 /* Internal EPHY Present */ 40 #define BFE_EPR 0x00008000 /* EPHY Reset */ 41 #define BFE_PME 0x00001000 /* PHY Mode Enable */ 42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */ 43 #define BFE_PADDR 0x0007c000 /* PHY Address */ 44 #define BFE_PADDR_SHIFT 18 45 46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */ 47 #define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */ 48 49 #define BFE_ISTAT 0x00000020 /* Interrupt Status */ 50 #define BFE_ISTAT_PME 0x00000040 /* Power Management Event */ 51 #define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */ 52 #define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */ 53 #define BFE_ISTAT_DATAE 0x00000800 /* Data Error */ 54 #define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */ 55 #define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */ 56 #define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */ 57 #define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */ 58 #define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */ 59 #define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */ 60 #define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */ 61 #define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */ 62 #define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */ 63 #define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\ 64 BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU) 65 66 #define BFE_IMASK 0x00000024 /* Interrupt Mask */ 67 #define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \ 68 BFE_ISTAT_TX) 69 70 #define BFE_MAC_CTRL 0x000000A8 /* MAC Control */ 71 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */ 72 #define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */ 73 #define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */ 74 #define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */ 75 #define BFE_CTRL_LED_SHIFT 5 76 77 #define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */ 78 #define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */ 79 #define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */ 80 81 #define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */ 82 #define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */ 83 #define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */ 84 #define BFE_LAZY_FC_SHIFT 24 85 86 #define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */ 87 #define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */ 88 #define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */ 89 #define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */ 90 #define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */ 91 #define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */ 92 93 #define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */ 94 #define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */ 95 #define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */ 96 #define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 97 #define BFE_STAT_SMASK 0x0000f000 /* State Mask */ 98 #define BFE_STAT_DISABLE 0x00000000 /* State Disabled */ 99 #define BFE_STAT_SACTIVE 0x00001000 /* State Active */ 100 #define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */ 101 #define BFE_STAT_STOPPED 0x00003000 /* State Stopped */ 102 #define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */ 103 #define BFE_STAT_EMASK 0x000f0000 /* Error Mask */ 104 #define BFE_STAT_ENONE 0x00000000 /* Error None */ 105 #define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */ 106 #define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */ 107 #define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */ 108 #define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */ 109 #define BFE_STAT_FLUSHED 0x00100000 /* Flushed */ 110 111 #define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */ 112 #define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */ 113 #define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */ 114 #define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */ 115 116 #define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */ 117 #define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */ 118 #define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */ 119 120 #define BFE_RXCONF 0x00000400 /* EMAC RX Config */ 121 #define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */ 122 #define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */ 123 #define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */ 124 #define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */ 125 #define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */ 126 #define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */ 127 #define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */ 128 #define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */ 129 130 #define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */ 131 #define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */ 132 133 #define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */ 134 #define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */ 135 #define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */ 136 137 #define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */ 138 #define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */ 139 #define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */ 140 #define BFE_MDIO_TA_SHIFT 16 141 #define BFE_MDIO_TA_VALID 2 142 143 #define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */ 144 #define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */ 145 #define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */ 146 #define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */ 147 #define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */ 148 #define BFE_MDIO_RA_SHIFT 18 149 #define BFE_MDIO_PMD_SHIFT 23 150 #define BFE_MDIO_OP_SHIFT 28 151 #define BFE_MDIO_OP_WRITE 1 152 #define BFE_MDIO_OP_READ 2 153 #define BFE_MDIO_SB_SHIFT 30 154 155 #define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */ 156 #define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */ 157 #define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */ 158 #define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */ 159 #define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */ 160 161 #define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */ 162 #define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */ 163 #define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */ 164 165 #define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */ 166 #define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */ 167 #define BFE_CAM_MSEL 0x00000002 /* Mask Select */ 168 #define BFE_CAM_READ 0x00000004 /* Read */ 169 #define BFE_CAM_WRITE 0x00000008 /* Read */ 170 #define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */ 171 #define BFE_CAM_BUSY 0x80000000 /* CAM Busy */ 172 #define BFE_CAM_INDEX_SHIFT 16 173 174 #define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */ 175 #define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */ 176 #define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */ 177 #define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */ 178 #define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */ 179 180 #define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */ 181 #define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */ 182 #define BFE_TX_FMODE 0x00000002 /* Flow Mode */ 183 #define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */ 184 #define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */ 185 186 #define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */ 187 188 #define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */ 189 #define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */ 190 191 /* Status registers */ 192 #define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */ 193 #define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */ 194 #define BFE_TX_O 0x00000508 /* MIB TX Octets */ 195 #define BFE_TX_P 0x0000050C /* MIB TX Packets */ 196 #define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */ 197 #define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */ 198 #define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */ 199 #define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */ 200 #define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */ 201 #define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */ 202 #define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */ 203 #define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */ 204 #define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */ 205 #define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */ 206 #define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */ 207 #define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */ 208 #define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */ 209 #define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */ 210 #define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */ 211 #define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */ 212 #define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */ 213 #define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */ 214 #define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */ 215 #define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */ 216 #define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */ 217 #define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */ 218 #define BFE_RX_O 0x00000588 /* MIB RX Octets */ 219 #define BFE_RX_P 0x0000058C /* MIB RX Packets */ 220 #define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */ 221 #define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */ 222 #define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */ 223 #define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */ 224 #define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */ 225 #define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */ 226 #define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */ 227 #define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */ 228 #define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */ 229 #define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */ 230 #define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */ 231 #define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */ 232 #define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */ 233 #define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */ 234 #define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */ 235 #define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */ 236 #define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */ 237 #define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */ 238 #define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */ 239 240 #define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */ 241 #define BFE_PC 0x0000000f /* Pipe Count */ 242 #define BFE_AP_MASK 0x00000030 /* Arbitration Priority */ 243 #define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */ 244 #define BFE_AP_TS 0x00000010 /* Use timeslices only */ 245 #define BFE_AP_TK 0x00000020 /* Use token only */ 246 #define BFE_AP_RSV 0x00000030 /* Reserved */ 247 #define BFE_IBE 0x00020000 /* In Band Error */ 248 #define BFE_TO 0x00040000 /* Timeout */ 249 250 /* Seems the bcm440x has a fairly generic core, we only need be concerned with 251 * a couple of these 252 */ 253 #define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */ 254 #define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ 255 #define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ 256 #define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ 257 #define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ 258 #define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ 259 #define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ 260 #define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ 261 262 #define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */ 263 #define BFE_RESET 0x00000001 /* Reset */ 264 #define BFE_REJECT 0x00000002 /* Reject */ 265 #define BFE_CLOCK 0x00010000 /* Clock Enable */ 266 #define BFE_FGC 0x00020000 /* Force Gated Clocks On */ 267 #define BFE_PE 0x40000000 /* Power Management Enable */ 268 #define BFE_BE 0x80000000 /* BIST Enable */ 269 270 #define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */ 271 #define BFE_SERR 0x00000001 /* S-error */ 272 #define BFE_INT 0x00000002 /* Interrupt */ 273 #define BFE_BUSY 0x00000004 /* Busy */ 274 #define BFE_GCR 0x20000000 /* Gated Clock Request */ 275 #define BFE_BISTF 0x40000000 /* BIST Failed */ 276 #define BFE_BISTD 0x80000000 /* BIST Done */ 277 278 #define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */ 279 #define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */ 280 #define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */ 281 #define BFE_TAB0_SHIFT 0 282 #define BFE_TAB1_SHIFT 16 283 284 #define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */ 285 #define BFE_STO_MASK 0x00000003 /* Service Timeout */ 286 #define BFE_RTO_MASK 0x00000030 /* Request Timeout */ 287 #define BFE_CID_MASK 0x00ff0000 /* Connection ID */ 288 #define BFE_RTO_SHIFT 4 289 #define BFE_CID_SHIFT 16 290 291 #define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */ 292 #define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */ 293 #define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */ 294 #define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */ 295 #define BFE_TEM_SHIFT 4 296 #define BFE_BEM_SHIFT 6 297 298 #define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */ 299 #define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */ 300 #define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */ 301 #define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */ 302 #define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */ 303 #define BFE_LOW_CO_SHIFT 11 304 #define BFE_LOW_IF_SHIFT 18 305 #define BFE_LOW_IM_SHIFT 24 306 307 #define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */ 308 #define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */ 309 #define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */ 310 #define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */ 311 #define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */ 312 #define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */ 313 #define BFE_HIGH_RM_SHIFT 2 314 #define BFE_HIGH_SM_SHIFT 4 315 #define BFE_HIGH_EM_SHIFT 8 316 #define BFE_HIGH_IM_SHIFT 10 317 318 #define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */ 319 #define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */ 320 #define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */ 321 #define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */ 322 #define BFE_MAX0_SHIFT 16 323 #define BFE_MAX1_SHIFT 20 324 325 #define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */ 326 #define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */ 327 #define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */ 328 329 #define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */ 330 #define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */ 331 332 #define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */ 333 #define BFE_CS_MASK 0x00000003 /* Config Space Mask */ 334 #define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */ 335 #define BFE_SYNCH 0x00000040 /* Sync */ 336 #define BFE_INIT 0x00000080 /* Initiator */ 337 #define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */ 338 #define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */ 339 #define BFE_FIRST 0x00010000 /* This Initiator is First */ 340 #define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */ 341 #define BFE_TP_MASK 0x00f00000 /* Target Ports */ 342 #define BFE_IP_MASK 0x0f000000 /* Initiator Ports */ 343 #define BFE_AR_SHIFT 3 344 #define BFE_MINLAT_SHIFT 8 345 #define BFE_MAXLAT_SHIFT 12 346 #define BFE_CW_SHIFT 18 347 #define BFE_TP_SHIFT 20 348 #define BFE_IP_SHIFT 24 349 350 #define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */ 351 #define BFE_RC_MASK 0x0000000f /* Revision Code */ 352 #define BFE_CC_MASK 0x0000fff0 /* Core Code */ 353 #define BFE_VC_MASK 0xffff0000 /* Vendor Code */ 354 #define BFE_CC_SHIFT 4 355 #define BFE_VC_SHIFT 16 356 357 #define BFE_CORE_ILINE20 0x801 358 #define BFE_CORE_SDRAM 0x803 359 #define BFE_CORE_PCI 0x804 360 #define BFE_CORE_MIPS 0x805 361 #define BFE_CORE_ENET 0x806 362 #define BFE_CORE_CODEC 0x807 363 #define BFE_CORE_USB 0x808 364 #define BFE_CORE_ILINE100 0x80a 365 #define BFE_CORE_EXTIF 0x811 366 367 /* SSB PCI config space registers. */ 368 #define BFE_BAR0_WIN 0x80 369 #define BFE_BAR1_WIN 0x84 370 #define BFE_SPROM_CONTROL 0x88 371 #define BFE_BAR1_CONTROL 0x8c 372 373 /* SSB core and hsot control registers. */ 374 #define BFE_SSB_CONTROL 0x00000000 375 #define BFE_SSB_ARBCONTROL 0x00000010 376 #define BFE_SSB_ISTAT 0x00000020 377 #define BFE_SSB_IMASK 0x00000024 378 #define BFE_SSB_MBOX 0x00000028 379 #define BFE_SSB_BCAST_ADDR 0x00000050 380 #define BFE_SSB_BCAST_DATA 0x00000054 381 #define BFE_SSB_PCI_TRANS_0 0x00000100 382 #define BFE_SSB_PCI_TRANS_1 0x00000104 383 #define BFE_SSB_PCI_TRANS_2 0x00000108 384 #define BFE_SSB_SPROM 0x00000800 385 386 #define BFE_SSB_PCI_MEM 0x00000000 387 #define BFE_SSB_PCI_IO 0x00000001 388 #define BFE_SSB_PCI_CFG0 0x00000002 389 #define BFE_SSB_PCI_CFG1 0x00000003 390 #define BFE_SSB_PCI_PREF 0x00000004 391 #define BFE_SSB_PCI_BURST 0x00000008 392 #define BFE_SSB_PCI_MASK0 0xfc000000 393 #define BFE_SSB_PCI_MASK1 0xfc000000 394 #define BFE_SSB_PCI_MASK2 0xc0000000 395 396 #define BFE_DESC_LEN 0x00001fff 397 #define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */ 398 #define BFE_DESC_EOT 0x10000000 /* End of Table */ 399 #define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */ 400 #define BFE_DESC_EOF 0x40000000 /* End of Frame */ 401 #define BFE_DESC_SOF 0x80000000 /* Start of Frame */ 402 403 #define BFE_RX_CP_THRESHOLD 256 404 #define BFE_RX_HEADER_LEN 28 405 406 #define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */ 407 #define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */ 408 #define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */ 409 #define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */ 410 #define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */ 411 #define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */ 412 #define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */ 413 #define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */ 414 #define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */ 415 #define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \ 416 BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO) 417 418 #define BFE_MCAST_TBL_SIZE 32 419 #define BFE_PCI_DMA 0x40000000 420 #define BFE_REG_PCI 0x18002000 421 422 #define BCOM_VENDORID 0x14E4 423 #define BCOM_DEVICEID_BCM4401 0x4401 424 #define BCOM_DEVICEID_BCM4401B0 0x170c 425 426 #define PCI_SETBIT(dev, reg, x, s) \ 427 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 428 #define PCI_CLRBIT(dev, reg, x, s) \ 429 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 430 431 #define BFE_TX_LIST_CNT 128 432 #define BFE_RX_LIST_CNT 128 433 #define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc) 434 #define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc) 435 #define BFE_RX_OFFSET 30 436 #define BFE_TX_QLEN 256 437 438 #define BFE_RX_RING_ALIGN 4096 439 #define BFE_TX_RING_ALIGN 4096 440 #define BFE_MAXTXSEGS 16 441 #define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */ 442 #define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 443 444 #define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg) 445 446 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val) 447 448 #define BFE_OR(sc, name, val) \ 449 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val) 450 451 #define BFE_AND(sc, name, val) \ 452 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val) 453 454 #define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED) 455 #define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx) 456 #define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx) 457 458 #define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1 459 460 struct bfe_tx_data { 461 struct mbuf *bfe_mbuf; 462 bus_dmamap_t bfe_map; 463 }; 464 465 struct bfe_rx_data { 466 struct mbuf *bfe_mbuf; 467 bus_dmamap_t bfe_map; 468 u_int32_t bfe_ctrl; 469 }; 470 471 struct bfe_desc { 472 u_int32_t bfe_ctrl; 473 u_int32_t bfe_addr; 474 }; 475 476 struct bfe_rxheader { 477 u_int16_t len; 478 u_int16_t flags; 479 u_int16_t pad[12]; 480 }; 481 482 #define MIB_TX_GOOD_O 0 483 #define MIB_TX_GOOD_P 1 484 #define MIB_TX_O 2 485 #define MIB_TX_P 3 486 #define MIB_TX_BCAST 4 487 #define MIB_TX_MCAST 5 488 #define MIB_TX_64 6 489 #define MIB_TX_65_127 7 490 #define MIB_TX_128_255 8 491 #define MIB_TX_256_511 9 492 #define MIB_TX_512_1023 10 493 #define MIB_TX_1024_MAX 11 494 #define MIB_TX_JABBER 12 495 #define MIB_TX_OSIZE 13 496 #define MIB_TX_FRAG 14 497 #define MIB_TX_URUNS 15 498 #define MIB_TX_TCOLS 16 499 #define MIB_TX_SCOLS 17 500 #define MIB_TX_MCOLS 18 501 #define MIB_TX_ECOLS 19 502 #define MIB_TX_LCOLS 20 503 #define MIB_TX_DEFERED 21 504 #define MIB_TX_CLOST 22 505 #define MIB_TX_PAUSE 23 506 #define MIB_RX_GOOD_O 24 507 #define MIB_RX_GOOD_P 25 508 #define MIB_RX_O 26 509 #define MIB_RX_P 27 510 #define MIB_RX_BCAST 28 511 #define MIB_RX_MCAST 29 512 #define MIB_RX_64 30 513 #define MIB_RX_65_127 31 514 #define MIB_RX_128_255 32 515 #define MIB_RX_256_511 33 516 #define MIB_RX_512_1023 34 517 #define MIB_RX_1024_MAX 35 518 #define MIB_RX_JABBER 36 519 #define MIB_RX_OSIZE 37 520 #define MIB_RX_FRAG 38 521 #define MIB_RX_MISS 39 522 #define MIB_RX_CRCA 40 523 #define MIB_RX_USIZE 41 524 #define MIB_RX_CRC 42 525 #define MIB_RX_ALIGN 43 526 #define MIB_RX_SYM 44 527 #define MIB_RX_PAUSE 45 528 #define MIB_RX_NPAUSE 46 529 530 #define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1) 531 532 struct bfe_hw_stats { 533 uint64_t tx_good_octets; 534 uint64_t tx_good_frames; 535 uint64_t tx_octets; 536 uint64_t tx_frames; 537 uint64_t tx_bcast_frames; 538 uint64_t tx_mcast_frames; 539 uint64_t tx_pkts_64; 540 uint64_t tx_pkts_65_127; 541 uint64_t tx_pkts_128_255; 542 uint64_t tx_pkts_256_511; 543 uint64_t tx_pkts_512_1023; 544 uint64_t tx_pkts_1024_max; 545 uint32_t tx_jabbers; 546 uint64_t tx_oversize_frames; 547 uint64_t tx_frag_frames; 548 uint32_t tx_underruns; 549 uint32_t tx_colls; 550 uint32_t tx_single_colls; 551 uint32_t tx_multi_colls; 552 uint32_t tx_excess_colls; 553 uint32_t tx_late_colls; 554 uint32_t tx_deferrals; 555 uint32_t tx_carrier_losts; 556 uint32_t tx_pause_frames; 557 558 uint64_t rx_good_octets; 559 uint64_t rx_good_frames; 560 uint64_t rx_octets; 561 uint64_t rx_frames; 562 uint64_t rx_bcast_frames; 563 uint64_t rx_mcast_frames; 564 uint64_t rx_pkts_64; 565 uint64_t rx_pkts_65_127; 566 uint64_t rx_pkts_128_255; 567 uint64_t rx_pkts_256_511; 568 uint64_t rx_pkts_512_1023; 569 uint64_t rx_pkts_1024_max; 570 uint32_t rx_jabbers; 571 uint64_t rx_oversize_frames; 572 uint64_t rx_frag_frames; 573 uint32_t rx_missed_frames; 574 uint32_t rx_crc_align_errs; 575 uint32_t rx_runts; 576 uint32_t rx_crc_errs; 577 uint32_t rx_align_errs; 578 uint32_t rx_symbol_errs; 579 uint32_t rx_pause_frames; 580 uint32_t rx_control_frames; 581 }; 582 583 struct bfe_softc 584 { 585 if_t bfe_ifp; /* interface info */ 586 device_t bfe_dev; 587 device_t bfe_miibus; 588 bus_dma_tag_t bfe_tag; 589 bus_dma_tag_t bfe_parent_tag; 590 bus_dma_tag_t bfe_tx_tag, bfe_rx_tag; 591 bus_dmamap_t bfe_tx_map, bfe_rx_map; 592 bus_dma_tag_t bfe_txmbuf_tag, bfe_rxmbuf_tag; 593 bus_dmamap_t bfe_rx_sparemap; 594 void *bfe_intrhand; 595 struct resource *bfe_irq; 596 struct resource *bfe_res; 597 struct callout bfe_stat_co; 598 struct bfe_hw_stats bfe_stats; 599 struct bfe_desc *bfe_tx_list, *bfe_rx_list; 600 struct bfe_tx_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */ 601 struct bfe_rx_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */ 602 struct mtx bfe_mtx; 603 u_int32_t bfe_flags; 604 #define BFE_FLAG_DETACH 0x4000 605 #define BFE_FLAG_LINK 0x8000 606 u_int32_t bfe_imask; 607 u_int32_t bfe_dma_offset; 608 u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod; 609 u_int32_t bfe_rx_prod, bfe_rx_cons; 610 u_int32_t bfe_tx_dma, bfe_rx_dma; 611 int bfe_watchdog_timer; 612 u_int8_t bfe_phyaddr; /* Address of the card's PHY */ 613 u_int8_t bfe_mdc_port; 614 u_int8_t bfe_core_unit; 615 u_char bfe_enaddr[6]; 616 int bfe_if_flags; 617 }; 618 619 struct bfe_type 620 { 621 u_int16_t bfe_vid; 622 u_int16_t bfe_did; 623 char *bfe_name; 624 }; 625 626 #endif /* _BFE_H */ 627