1 /* 2 * Copyright 2014-2017 Cavium, Inc. 3 * The contents of this file are subject to the terms of the Common Development 4 * and Distribution License, v.1, (the "License"). 5 * 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the License at available 9 * at http://opensource.org/licenses/CDDL-1.0 10 * 11 * See the License for the specific language governing permissions and 12 * limitations under the License. 13 */ 14 15 #ifndef _54xx_reg_h 16 #define _54xx_reg_h 17 18 #include "bits.h" 19 20 21 22 /* Control register. */ 23 #define PHY_CTRL_REG 0x00 24 #define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) 25 #define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE 26 #define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 27 #define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 28 #define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 29 #define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 30 #define PHY_CTRL_RESTART_AUTO_NEG BIT_9 31 #define PHY_CTRL_ISOLATE_PHY BIT_10 32 #define PHY_CTRL_LOWER_POWER_MODE BIT_11 33 #define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 34 #define PHY_CTRL_LOOPBACK_MODE BIT_14 35 #define PHY_CTRL_PHY_RESET BIT_15 36 37 38 /* Status register. */ 39 #define PHY_STATUS_REG 0x01 40 #define PHY_STATUS_LINK_PASS BIT_2 41 #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 42 43 44 /* Phy Id registers. */ 45 #define PHY_ID1_REG 0x02 46 #define PHY_ID2_REG 0x03 47 48 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 49 #define PHY_BCM5400_PHY_ID 0x00206040 50 #define PHY_BCM5401_PHY_ID 0x00206050 51 #define PHY_BCM5411_PHY_ID 0x00206070 52 #define PHY_BCM5701_PHY_ID 0x00206110 53 #define PHY_BCM5703_PHY_ID 0x00206160 54 #define PHY_BCM5706_PHY_ID 0x00206160 55 56 #define PHY_ID(id) ((id) & 0xfffffff0) 57 #define PHY_REV_ID(id) ((id) & 0xf) 58 #define PHY_BCM5401_B0_REV 0x1 59 #define PHY_BCM5401_B2_REV 0x3 60 #define PHY_BCM5401_C0_REV 0x6 61 62 63 /* Auto-negotiation advertisement register. */ 64 #define PHY_AN_AD_REG 0x04 65 #define PHY_AN_AD_10BASET_HALF BIT_5 66 #define PHY_AN_AD_10BASET_FULL BIT_6 67 #define PHY_AN_AD_100BASETX_HALF BIT_7 68 #define PHY_AN_AD_100BASETX_FULL BIT_8 69 #define PHY_AN_AD_PAUSE_CAPABLE BIT_10 70 #define PHY_AN_AD_ASYM_PAUSE BIT_11 71 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 72 73 74 /* Apply to 1000-X fiber mode only */ 75 #define PHY_AN_AD_1000X_FULL_DUPLEX BIT_5 76 #define PHY_AN_AD_1000X_HALF_DUPLEX BIT_6 77 #define PHY_AN_AD_1000X_PAUSE_CAPABLE BIT_7 78 #define PHY_AN_AD_1000X_ASYM_PAUSE BIT_8 79 #define PHY_AN_AD_1000X_REMOTE_FAULT_LINK_FAILURE BIT_12 80 #define PHY_AN_AD_1000X_REMOTE_FAULT_OFFLINE BIT_13 81 #define PHY_AN_AD_1000X_REMOTE_FAULT_AUTONEG_ERR (BIT_12 | BIT_13) 82 83 /* Auto-negotiation Link Partner Ability register. */ 84 #define PHY_LINK_PARTNER_ABILITY_REG 0x05 85 #define PHY_LINK_PARTNER_10BASET_HALF BIT_5 86 #define PHY_LINK_PARTNER_10BASET_FULL BIT_6 87 #define PHY_LINK_PARTNER_100BASETX_HALF BIT_7 88 #define PHY_LINK_PARTNER_100BASETX_FULL BIT_8 89 #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 90 #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 91 92 93 /* Auto-negotiation expansion register. */ 94 #define PHY_AN_EXPANSION_REG 0x06 95 #define PHY_LINK_PARTNER_AUTONEG_ABILITY BIT_0 96 97 98 /* 1000Base-T control/advertisement register. */ 99 #define PHY_1000BASET_CTRL_REG 0x09 100 #define PHY_AN_AD_1000BASET_HALF BIT_8 101 #define PHY_AN_AD_1000BASET_FULL BIT_9 102 #define PHY_CONFIG_AS_MASTER BIT_11 103 #define PHY_ENABLE_CONFIG_AS_MASTER BIT_12 104 105 106 /* 1000Base-T status/link partner advertisement. */ 107 #define PHY_1000BASET_STATUS_REG 0x0a 108 #define PHY_LINK_PARTNER_1000BASET_HALF BIT_10 109 #define PHY_LINK_PARTNER_1000BASET_FULL BIT_11 110 111 112 /* Extended control register. */ 113 #define BCM540X_EXT_CTRL_REG 0x10 114 115 #define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 116 #define BCM540X_EXT_CTRL_TBI BIT_15 117 118 119 /* DSP Coefficient Read/Write Port. */ 120 #define BCM540X_DSP_RW_PORT 0x15 121 122 123 /* DSP Coeficient Address Register. */ 124 #define BCM540X_DSP_ADDRESS_REG 0x17 125 126 #define BCM540X_DSP_TAP_NUMBER_MASK 0x00 127 #define BCM540X_DSP_AGC_A 0x00 128 #define BCM540X_DSP_AGC_B 0x01 129 #define BCM540X_DSP_MSE_PAIR_STATUS 0x02 130 #define BCM540X_DSP_SOFT_DECISION 0x03 131 #define BCM540X_DSP_PHASE_REG 0x04 132 #define BCM540X_DSP_SKEW 0x05 133 #define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 134 #define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 135 #define BCM540X_DSP_LAST_ECHO 0x08 136 #define BCM540X_DSP_FREQUENCY 0x09 137 #define BCM540X_DSP_PLL_BANDWIDTH 0x0a 138 #define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b 139 140 #define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) 141 #define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) 142 #define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) 143 #define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) 144 #define BCM540X_DSP_FILTER_FEXT0 BIT_11 145 #define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) 146 #define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) 147 #define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) 148 #define BCM540X_DSP_FILTER_NEXT0 BIT_10 149 #define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) 150 #define BCM540X_DSP_FILTER_DFE BIT_9 151 #define BCM540X_DSP_FILTER_FFE BIT_8 152 153 #define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 154 155 #define BCM540X_DSP_SEL_CH_0 BIT_NONE 156 #define BCM540X_DSP_SEL_CH_1 BIT_13 157 #define BCM540X_DSP_SEL_CH_2 BIT_14 158 #define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) 159 160 #define BCM540X_CONTROL_ALL_CHANNELS BIT_15 161 162 163 /* Auxilliary Control Register (Shadow Register) */ 164 #define BCM5401_AUX_CTRL 0x18 165 166 #define BCM5401_SHADOW_SEL_MASK 0x7 167 #define BCM5401_SHADOW_SEL_NORMAL 0x00 168 #define BCM5401_SHADOW_SEL_10BASET 0x01 169 #define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 170 #define BCM5401_SHADOW_SEL_IP_PHONE 0x03 171 #define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 172 #define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 173 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 174 175 176 /* Shadow register selector == '000' */ 177 #define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 178 #define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 179 #define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 180 #define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 181 #define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 182 #define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE 183 #define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 184 #define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 185 #define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) 186 #define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 187 #define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 188 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE 189 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 190 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 191 #define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) 192 #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 193 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 194 195 196 /* Auxilliary status summary. */ 197 #define BCM540X_AUX_STATUS_REG 0x19 198 199 #define BCM540X_AUX_LINK_PASS BIT_2 200 #define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) 201 #define BCM540X_AUX_10BASET_HD BIT_8 202 #define BCM540X_AUX_10BASET_FD BIT_9 203 #define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) 204 #define BCM540X_AUX_100BASET4 BIT_10 205 #define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) 206 #define BCM540X_AUX_1000BASET_HD (BIT_9 | BIT_10) 207 #define BCM540X_AUX_1000BASET_FD (BIT_8 | BIT_9 | BIT_10) 208 209 210 /* Interrupt status. */ 211 #define BCM540X_INT_STATUS_REG 0x1a 212 213 #define BCM540X_INT_LINK_CHNG BIT_1 214 #define BCM540X_INT_SPEED_CHNG BIT_2 215 #define BCM540X_INT_DUPLEX_CHNG BIT_3 216 #define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 217 218 219 /* Interrupt mask register. */ 220 #define BCM540X_INT_MASK_REG 0x1b 221 222 223 224 #endif // _54xx_reg_h 225