1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2001 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 /* 28 * Platform Power Management 29 * 30 * Register and bit definitions of the power-related parts 31 */ 32 33 #ifndef _SYS_XCALPPM_REG_H 34 #define _SYS_XCALPPM_REG_H 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* 43 * Registers accessed by the ppm driver. These registers actually come 44 * from different ASICs on the system and are collected for us 45 * by the prom into a single device node. These registers are: 46 * 47 * BBC E* Control Register (other registers like E* Assert Change Time 48 * or E* PLL Settle Time are offseted from this address) 49 * Mode Auxio Register 50 * SuperI/O Configuration Register 51 * SuperI/O GPIO Registers 52 */ 53 struct xcppmreg { 54 volatile uint16_t *bbc_estar_ctrl; /* set cpu clock rate */ 55 volatile uint32_t *bbc_assert_change; /* set t1 cpu trans time */ 56 volatile uint32_t *bbc_pll_settle; /* set t4 cpu trans time */ 57 volatile uint32_t *rio_mode_auxio; /* transition cpu clock */ 58 volatile uint8_t *gpio_bank_sel_index; /* index GPIO bank sel. */ 59 volatile uint8_t *gpio_bank_sel_data; /* data GPIO bank select */ 60 volatile uint8_t *gpio_port1_data; /* set LED */ 61 volatile uint8_t *gpio_port2_data; /* set DC-DC, 1394, FET */ 62 }; 63 64 struct xcppmhndl { 65 ddi_acc_handle_t bbc_estar_ctrl; 66 ddi_acc_handle_t rio_mode_auxio; 67 ddi_acc_handle_t gpio_bank_select; 68 ddi_acc_handle_t gpio_data_ports; 69 }; 70 71 /* 72 * Register offsets 73 */ 74 #define BBC_ESTAR_CTRL_OFFSET 0x0 75 #define BBC_ASSERT_CHANGE_OFFSET 0x2 76 #define BBC_PLL_SETTLE_OFFSET 0xa 77 78 #define GPIO_BANK_SEL_INDEX_OFFSET 0x0 79 #define GPIO_BANK_SEL_DATA_OFFSET 0x1 80 81 #define GPIO_PORT1_DATA_OFFSET 0x0 82 #define GPIO_PORT2_DATA_OFFSET 0x4 83 84 /* 85 * Definitions for the RIO Mode Auxio register 86 */ 87 #define RIO_BBC_ESTAR_MODE 0x800 88 89 /* 90 * Index for SuperIO Configuration 2 register 91 */ 92 #define SIO_CONFIG2_INDEX 0x22 93 94 /* 95 * GPIO Data Port 1 bit assignments 96 */ 97 #define LED 0x02 /* Controls front panel LED */ 98 99 /* 100 * GPIO Data Port 2 bit assignments 101 */ 102 #define CPEN 0x02 /* Controls 1394 cable power [1 = on] */ 103 #define HIGHPWR 0x08 /* Enter/Leave low pwr mode [1 = high pwr] */ 104 #define DRVON 0x10 /* Controls pwr to internal drives [1 = on] */ 105 106 /* 107 * BBC timing registers are set according to "bbc_delay" variable 108 * and adjusted based on current clock speed. 109 */ 110 extern int bbc_delay; /* microsec */ 111 #define BBC_DELAY (bbc_delay * 1000000) /* nanosec */ 112 #define EXCAL_CLOCK 10 /* 10 nsec or 100 MHz */ 113 #define BBC_CLOCK (2 * EXCAL_CLOCK) /* BBC clock is half speed */ 114 115 #define XCPPM_BBC_DELAY(index) \ 116 (index == 0) ? (BBC_DELAY/(BBC_CLOCK * 32)) : \ 117 ((index == 1) ? (BBC_DELAY/(BBC_CLOCK * 2)) : \ 118 BBC_DELAY/BBC_CLOCK) 119 120 /* 121 * BBC E* Control Reg bit masks 122 */ 123 #define BBC_ESTAR_SLOW 0x20 /* 1/32 speed */ 124 #define BBC_ESTAR_MEDIUM 0x2 /* 1/2 speed */ 125 #define BBC_ESTAR_FAST 0x1 /* full speed */ 126 127 /* 128 * register access IO 129 */ 130 #define XCPPM_CLRBIT 0x0 131 #define XCPPM_SETBIT 0x1 132 #define XCPPM_GETBIT 0x2 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 #endif /* _SYS_XCALPPM_REG_H */ 139