1 //===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the entry points for global functions defined in 10 // the LLVM NVPTX back-end. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTX_H 15 #define LLVM_LIB_TARGET_NVPTX_NVPTX_H 16 17 #include "llvm/CodeGen/ISDOpcodes.h" 18 #include "llvm/IR/PassManager.h" 19 #include "llvm/Pass.h" 20 #include "llvm/Support/AtomicOrdering.h" 21 #include "llvm/Support/CodeGen.h" 22 #include "llvm/Target/TargetMachine.h" 23 namespace llvm { 24 class FunctionPass; 25 class MachineFunctionPass; 26 class NVPTXTargetMachine; 27 class PassRegistry; 28 29 namespace NVPTXCC { 30 enum CondCodes { 31 EQ, 32 NE, 33 LT, 34 LE, 35 GT, 36 GE 37 }; 38 } 39 40 FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM, 41 llvm::CodeGenOptLevel OptLevel); 42 ModulePass *createNVPTXAssignValidGlobalNamesPass(); 43 ModulePass *createGenericToNVVMLegacyPass(); 44 ModulePass *createNVPTXCtorDtorLoweringLegacyPass(); 45 FunctionPass *createNVVMIntrRangePass(); 46 ModulePass *createNVVMReflectPass(unsigned int SmVersion); 47 MachineFunctionPass *createNVPTXPrologEpilogPass(); 48 MachineFunctionPass *createNVPTXReplaceImageHandlesPass(); 49 FunctionPass *createNVPTXImageOptimizerPass(); 50 FunctionPass *createNVPTXLowerArgsPass(); 51 FunctionPass *createNVPTXLowerAllocaPass(); 52 FunctionPass *createNVPTXLowerUnreachablePass(bool TrapUnreachable, 53 bool NoTrapAfterNoreturn); 54 FunctionPass *createNVPTXTagInvariantLoadsPass(); 55 MachineFunctionPass *createNVPTXPeephole(); 56 MachineFunctionPass *createNVPTXProxyRegErasurePass(); 57 MachineFunctionPass *createNVPTXForwardParamsPass(); 58 59 void initializeNVVMReflectLegacyPassPass(PassRegistry &); 60 void initializeGenericToNVVMLegacyPassPass(PassRegistry &); 61 void initializeNVPTXAllocaHoistingPass(PassRegistry &); 62 void initializeNVPTXAsmPrinterPass(PassRegistry &); 63 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &); 64 void initializeNVPTXAtomicLowerPass(PassRegistry &); 65 void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &); 66 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &); 67 void initializeNVPTXLowerAllocaPass(PassRegistry &); 68 void initializeNVPTXLowerUnreachablePass(PassRegistry &); 69 void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &); 70 void initializeNVPTXLowerArgsLegacyPassPass(PassRegistry &); 71 void initializeNVPTXProxyRegErasurePass(PassRegistry &); 72 void initializeNVPTXForwardParamsPassPass(PassRegistry &); 73 void initializeNVVMIntrRangePass(PassRegistry &); 74 void initializeNVVMReflectPass(PassRegistry &); 75 void initializeNVPTXAAWrapperPassPass(PassRegistry &); 76 void initializeNVPTXExternalAAWrapperPass(PassRegistry &); 77 void initializeNVPTXPeepholePass(PassRegistry &); 78 void initializeNVPTXTagInvariantLoadLegacyPassPass(PassRegistry &); 79 void initializeNVPTXPrologEpilogPassPass(PassRegistry &); 80 81 struct NVVMIntrRangePass : PassInfoMixin<NVVMIntrRangePass> { 82 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 83 }; 84 85 struct NVVMReflectPass : PassInfoMixin<NVVMReflectPass> { NVVMReflectPassNVVMReflectPass86 NVVMReflectPass() : SmVersion(0) {} NVVMReflectPassNVVMReflectPass87 NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {} 88 PreservedAnalyses run(Module &F, ModuleAnalysisManager &AM); 89 90 private: 91 unsigned SmVersion; 92 }; 93 94 struct GenericToNVVMPass : PassInfoMixin<GenericToNVVMPass> { 95 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); 96 }; 97 98 struct NVPTXCopyByValArgsPass : PassInfoMixin<NVPTXCopyByValArgsPass> { 99 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 100 }; 101 102 struct NVPTXLowerArgsPass : PassInfoMixin<NVPTXLowerArgsPass> { 103 private: 104 TargetMachine &TM; 105 106 public: NVPTXLowerArgsPassNVPTXLowerArgsPass107 NVPTXLowerArgsPass(TargetMachine &TM) : TM(TM) {}; 108 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 109 }; 110 111 struct NVPTXTagInvariantLoadsPass : PassInfoMixin<NVPTXTagInvariantLoadsPass> { 112 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM); 113 }; 114 115 namespace NVPTX { 116 enum DrvInterface { 117 NVCL, 118 CUDA 119 }; 120 121 // A field inside TSFlags needs a shift and a mask. The usage is 122 // always as follows : 123 // ((TSFlags & fieldMask) >> fieldShift) 124 // The enum keeps the mask, the shift, and all valid values of the 125 // field in one place. 126 enum VecInstType { 127 VecInstTypeShift = 0, 128 VecInstTypeMask = 0xF, 129 130 VecNOP = 0, 131 VecLoad = 1, 132 VecStore = 2, 133 VecBuild = 3, 134 VecShuffle = 4, 135 VecExtract = 5, 136 VecInsert = 6, 137 VecDest = 7, 138 VecOther = 15 139 }; 140 141 enum SimpleMove { 142 SimpleMoveMask = 0x10, 143 SimpleMoveShift = 4 144 }; 145 enum LoadStore { 146 isLoadMask = 0x20, 147 isLoadShift = 5, 148 isStoreMask = 0x40, 149 isStoreShift = 6 150 }; 151 152 // Extends LLVM AtomicOrdering with PTX Orderings: 153 using OrderingUnderlyingType = unsigned int; 154 enum Ordering : OrderingUnderlyingType { 155 NotAtomic = (OrderingUnderlyingType) 156 AtomicOrdering::NotAtomic, // PTX calls these: "Weak" 157 // Unordered = 1, // NVPTX maps LLVM Unorderd to Relaxed 158 Relaxed = (OrderingUnderlyingType)AtomicOrdering::Monotonic, 159 // Consume = 3, // Unimplemented in LLVM; NVPTX would map to "Acquire" 160 Acquire = (OrderingUnderlyingType)AtomicOrdering::Acquire, 161 Release = (OrderingUnderlyingType)AtomicOrdering::Release, 162 AcquireRelease = (OrderingUnderlyingType)AtomicOrdering::AcquireRelease, 163 SequentiallyConsistent = 164 (OrderingUnderlyingType)AtomicOrdering::SequentiallyConsistent, 165 Volatile = SequentiallyConsistent + 1, 166 RelaxedMMIO = Volatile + 1, 167 LASTORDERING = RelaxedMMIO 168 }; 169 170 using ScopeUnderlyingType = unsigned int; 171 enum Scope : ScopeUnderlyingType { 172 Thread = 0, 173 Block = 1, 174 Cluster = 2, 175 Device = 3, 176 System = 4, 177 LASTSCOPE = System 178 }; 179 180 using AddressSpaceUnderlyingType = unsigned int; 181 enum AddressSpace : AddressSpaceUnderlyingType { 182 Generic = 0, 183 Global = 1, 184 Shared = 3, 185 Const = 4, 186 Local = 5, 187 SharedCluster = 7, 188 189 // NVPTX Backend Private: 190 Param = 101 191 }; 192 193 namespace PTXLdStInstCode { 194 enum FromType { Unsigned = 0, Signed, Float, Untyped }; 195 } // namespace PTXLdStInstCode 196 197 /// PTXCvtMode - Conversion code enumeration 198 namespace PTXCvtMode { 199 enum CvtMode { 200 NONE = 0, 201 RNI, 202 RZI, 203 RMI, 204 RPI, 205 RN, 206 RZ, 207 RM, 208 RP, 209 RNA, 210 211 BASE_MASK = 0x0F, 212 FTZ_FLAG = 0x10, 213 SAT_FLAG = 0x20, 214 RELU_FLAG = 0x40 215 }; 216 } 217 218 /// PTXCmpMode - Comparison mode enumeration 219 namespace PTXCmpMode { 220 enum CmpMode { 221 EQ = 0, 222 NE, 223 LT, 224 LE, 225 GT, 226 GE, 227 EQU, 228 NEU, 229 LTU, 230 LEU, 231 GTU, 232 GEU, 233 NUM, 234 // NAN is a MACRO 235 NotANumber, 236 }; 237 } 238 239 namespace PTXPrmtMode { 240 enum PrmtMode { 241 NONE, 242 F4E, 243 B4E, 244 RC8, 245 ECL, 246 ECR, 247 RC16, 248 }; 249 } 250 251 enum class DivPrecisionLevel : unsigned { 252 Approx = 0, 253 Full = 1, 254 IEEE754 = 2, 255 IEEE754_NoFTZ = 3, 256 }; 257 258 } // namespace NVPTX 259 void initializeNVPTXDAGToDAGISelLegacyPass(PassRegistry &); 260 } // namespace llvm 261 262 // Defines symbolic names for NVPTX registers. This defines a mapping from 263 // register name to register number. 264 #define GET_REGINFO_ENUM 265 #include "NVPTXGenRegisterInfo.inc" 266 267 // Defines symbolic names for the NVPTX instructions. 268 #define GET_INSTRINFO_ENUM 269 #define GET_INSTRINFO_MC_HELPER_DECLS 270 #include "NVPTXGenInstrInfo.inc" 271 272 #endif 273