xref: /titanic_41/usr/src/uts/common/io/chxge/com/regs.h (revision d39a76e7b087a3d0927cbe6898dc0a6770fa6c68)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /* This file is automatically generated --- do not edit */
23 
24 #pragma ident	"%Z%%M%	%I%	%E% SMI"	/* regs.h */
25 
26 /* SGE registers */
27 #define A_SG_CONTROL 0x0
28 
29 #define S_CMDQ0_ENABLE    0
30 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
31 #define F_CMDQ0_ENABLE    V_CMDQ0_ENABLE(1U)
32 
33 #define S_CMDQ1_ENABLE    1
34 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
35 #define F_CMDQ1_ENABLE    V_CMDQ1_ENABLE(1U)
36 
37 #define S_FL0_ENABLE    2
38 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
39 #define F_FL0_ENABLE    V_FL0_ENABLE(1U)
40 
41 #define S_FL1_ENABLE    3
42 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
43 #define F_FL1_ENABLE    V_FL1_ENABLE(1U)
44 
45 #define S_CPL_ENABLE    4
46 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
47 #define F_CPL_ENABLE    V_CPL_ENABLE(1U)
48 
49 #define S_RESPONSE_QUEUE_ENABLE    5
50 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
51 #define F_RESPONSE_QUEUE_ENABLE    V_RESPONSE_QUEUE_ENABLE(1U)
52 
53 #define S_CMDQ_PRIORITY    6
54 #define M_CMDQ_PRIORITY    0x3
55 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
56 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
57 
58 #define S_DISABLE_CMDQ0_GTS    8
59 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
60 #define F_DISABLE_CMDQ0_GTS    V_DISABLE_CMDQ0_GTS(1U)
61 
62 #define S_DISABLE_CMDQ1_GTS    9
63 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
64 #define F_DISABLE_CMDQ1_GTS    V_DISABLE_CMDQ1_GTS(1U)
65 
66 #define S_DISABLE_FL0_GTS    10
67 #define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
68 #define F_DISABLE_FL0_GTS    V_DISABLE_FL0_GTS(1U)
69 
70 #define S_DISABLE_FL1_GTS    11
71 #define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
72 #define F_DISABLE_FL1_GTS    V_DISABLE_FL1_GTS(1U)
73 
74 #define S_ENABLE_BIG_ENDIAN    12
75 #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
76 #define F_ENABLE_BIG_ENDIAN    V_ENABLE_BIG_ENDIAN(1U)
77 
78 #define S_FL_SELECTION_CRITERIA    13
79 #define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
80 #define F_FL_SELECTION_CRITERIA    V_FL_SELECTION_CRITERIA(1U)
81 
82 #define S_ISCSI_COALESCE    14
83 #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
84 #define F_ISCSI_COALESCE    V_ISCSI_COALESCE(1U)
85 
86 #define S_RX_PKT_OFFSET    15
87 #define M_RX_PKT_OFFSET    0x7
88 #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
89 #define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
90 
91 #define S_VLAN_XTRACT    18
92 #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
93 #define F_VLAN_XTRACT    V_VLAN_XTRACT(1U)
94 
95 #define A_SG_DOORBELL 0x4
96 #define A_SG_CMD0BASELWR 0x8
97 #define A_SG_CMD0BASEUPR 0xc
98 #define A_SG_CMD1BASELWR 0x10
99 #define A_SG_CMD1BASEUPR 0x14
100 #define A_SG_FL0BASELWR 0x18
101 #define A_SG_FL0BASEUPR 0x1c
102 #define A_SG_FL1BASELWR 0x20
103 #define A_SG_FL1BASEUPR 0x24
104 #define A_SG_CMD0SIZE 0x28
105 
106 #define S_CMDQ0_SIZE    0
107 #define M_CMDQ0_SIZE    0x1ffff
108 #define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
109 #define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
110 
111 #define A_SG_FL0SIZE 0x2c
112 
113 #define S_FL0_SIZE    0
114 #define M_FL0_SIZE    0x1ffff
115 #define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
116 #define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
117 
118 #define A_SG_RSPSIZE 0x30
119 
120 #define S_RESPQ_SIZE    0
121 #define M_RESPQ_SIZE    0x1ffff
122 #define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
123 #define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
124 
125 #define A_SG_RSPBASELWR 0x34
126 #define A_SG_RSPBASEUPR 0x38
127 #define A_SG_FLTHRESHOLD 0x3c
128 
129 #define S_FL_THRESHOLD    0
130 #define M_FL_THRESHOLD    0xffff
131 #define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
132 #define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
133 
134 #define A_SG_RSPQUEUECREDIT 0x40
135 
136 #define S_RESPQ_CREDIT    0
137 #define M_RESPQ_CREDIT    0x1ffff
138 #define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
139 #define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
140 
141 #define A_SG_SLEEPING 0x48
142 
143 #define S_SLEEPING    0
144 #define M_SLEEPING    0xffff
145 #define V_SLEEPING(x) ((x) << S_SLEEPING)
146 #define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
147 
148 #define A_SG_INTRTIMER 0x4c
149 
150 #define S_INTERRUPT_TIMER_COUNT    0
151 #define M_INTERRUPT_TIMER_COUNT    0xffffff
152 #define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
153 #define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
154 
155 #define A_SG_CMD0PTR 0x50
156 
157 #define S_CMDQ0_POINTER    0
158 #define M_CMDQ0_POINTER    0xffff
159 #define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
160 #define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
161 
162 #define S_CURRENT_GENERATION_BIT    16
163 #define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
164 #define F_CURRENT_GENERATION_BIT    V_CURRENT_GENERATION_BIT(1U)
165 
166 #define A_SG_CMD1PTR 0x54
167 
168 #define S_CMDQ1_POINTER    0
169 #define M_CMDQ1_POINTER    0xffff
170 #define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
171 #define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
172 
173 #define A_SG_FL0PTR 0x58
174 
175 #define S_FL0_POINTER    0
176 #define M_FL0_POINTER    0xffff
177 #define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
178 #define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
179 
180 #define A_SG_FL1PTR 0x5c
181 
182 #define S_FL1_POINTER    0
183 #define M_FL1_POINTER    0xffff
184 #define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
185 #define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
186 
187 #define A_SG_VERSION 0x6c
188 
189 #define S_DAY    0
190 #define M_DAY    0x1f
191 #define V_DAY(x) ((x) << S_DAY)
192 #define G_DAY(x) (((x) >> S_DAY) & M_DAY)
193 
194 #define S_MONTH    5
195 #define M_MONTH    0xf
196 #define V_MONTH(x) ((x) << S_MONTH)
197 #define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
198 
199 #define A_SG_CMD1SIZE 0xb0
200 
201 #define S_CMDQ1_SIZE    0
202 #define M_CMDQ1_SIZE    0x1ffff
203 #define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
204 #define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
205 
206 #define A_SG_FL1SIZE 0xb4
207 
208 #define S_FL1_SIZE    0
209 #define M_FL1_SIZE    0x1ffff
210 #define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
211 #define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
212 
213 #define A_SG_INT_ENABLE 0xb8
214 
215 #define S_RESPQ_EXHAUSTED    0
216 #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
217 #define F_RESPQ_EXHAUSTED    V_RESPQ_EXHAUSTED(1U)
218 
219 #define S_RESPQ_OVERFLOW    1
220 #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
221 #define F_RESPQ_OVERFLOW    V_RESPQ_OVERFLOW(1U)
222 
223 #define S_FL_EXHAUSTED    2
224 #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
225 #define F_FL_EXHAUSTED    V_FL_EXHAUSTED(1U)
226 
227 #define S_PACKET_TOO_BIG    3
228 #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
229 #define F_PACKET_TOO_BIG    V_PACKET_TOO_BIG(1U)
230 
231 #define S_PACKET_MISMATCH    4
232 #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
233 #define F_PACKET_MISMATCH    V_PACKET_MISMATCH(1U)
234 
235 #define A_SG_INT_CAUSE 0xbc
236 #define A_SG_RESPACCUTIMER 0xc0
237 
238 /* MC3 registers */
239 #define A_MC3_CFG 0x100
240 
241 #define S_CLK_ENABLE    0
242 #define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
243 #define F_CLK_ENABLE    V_CLK_ENABLE(1U)
244 
245 #define S_READY    1
246 #define V_READY(x) ((x) << S_READY)
247 #define F_READY    V_READY(1U)
248 
249 #define S_READ_TO_WRITE_DELAY    2
250 #define M_READ_TO_WRITE_DELAY    0x7
251 #define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
252 #define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
253 
254 #define S_WRITE_TO_READ_DELAY    5
255 #define M_WRITE_TO_READ_DELAY    0x7
256 #define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
257 #define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
258 
259 #define S_MC3_BANK_CYCLE    8
260 #define M_MC3_BANK_CYCLE    0xf
261 #define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
262 #define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
263 
264 #define S_REFRESH_CYCLE    12
265 #define M_REFRESH_CYCLE    0xf
266 #define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
267 #define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
268 
269 #define S_PRECHARGE_CYCLE    16
270 #define M_PRECHARGE_CYCLE    0x3
271 #define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
272 #define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
273 
274 #define S_ACTIVE_TO_READ_WRITE_DELAY    18
275 #define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
276 #define F_ACTIVE_TO_READ_WRITE_DELAY    V_ACTIVE_TO_READ_WRITE_DELAY(1U)
277 
278 #define S_ACTIVE_TO_PRECHARGE_DELAY    19
279 #define M_ACTIVE_TO_PRECHARGE_DELAY    0x7
280 #define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
281 #define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
282 
283 #define S_WRITE_RECOVERY_DELAY    22
284 #define M_WRITE_RECOVERY_DELAY    0x3
285 #define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
286 #define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
287 
288 #define S_DENSITY    24
289 #define M_DENSITY    0x3
290 #define V_DENSITY(x) ((x) << S_DENSITY)
291 #define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
292 
293 #define S_ORGANIZATION    26
294 #define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
295 #define F_ORGANIZATION    V_ORGANIZATION(1U)
296 
297 #define S_BANKS    27
298 #define V_BANKS(x) ((x) << S_BANKS)
299 #define F_BANKS    V_BANKS(1U)
300 
301 #define S_UNREGISTERED    28
302 #define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
303 #define F_UNREGISTERED    V_UNREGISTERED(1U)
304 
305 #define S_MC3_WIDTH    29
306 #define M_MC3_WIDTH    0x3
307 #define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
308 #define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
309 
310 #define S_MC3_SLOW    31
311 #define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
312 #define F_MC3_SLOW    V_MC3_SLOW(1U)
313 
314 #define A_MC3_MODE 0x104
315 
316 #define S_MC3_MODE    0
317 #define M_MC3_MODE    0x3fff
318 #define V_MC3_MODE(x) ((x) << S_MC3_MODE)
319 #define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
320 
321 #define S_BUSY    31
322 #define V_BUSY(x) ((x) << S_BUSY)
323 #define F_BUSY    V_BUSY(1U)
324 
325 #define A_MC3_EXT_MODE 0x108
326 
327 #define S_MC3_EXTENDED_MODE    0
328 #define M_MC3_EXTENDED_MODE    0x3fff
329 #define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
330 #define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
331 
332 #define A_MC3_PRECHARG 0x10c
333 #define A_MC3_REFRESH 0x110
334 
335 #define S_REFRESH_ENABLE    0
336 #define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
337 #define F_REFRESH_ENABLE    V_REFRESH_ENABLE(1U)
338 
339 #define S_REFRESH_DIVISOR    1
340 #define M_REFRESH_DIVISOR    0x3fff
341 #define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
342 #define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
343 
344 #define A_MC3_STROBE 0x114
345 
346 #define S_MASTER_DLL_RESET    0
347 #define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
348 #define F_MASTER_DLL_RESET    V_MASTER_DLL_RESET(1U)
349 
350 #define S_MASTER_DLL_TAP_COUNT    1
351 #define M_MASTER_DLL_TAP_COUNT    0xff
352 #define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
353 #define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
354 
355 #define S_MASTER_DLL_LOCKED    9
356 #define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
357 #define F_MASTER_DLL_LOCKED    V_MASTER_DLL_LOCKED(1U)
358 
359 #define S_MASTER_DLL_MAX_TAP_COUNT    10
360 #define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
361 #define F_MASTER_DLL_MAX_TAP_COUNT    V_MASTER_DLL_MAX_TAP_COUNT(1U)
362 
363 #define S_MASTER_DLL_TAP_COUNT_OFFSET    11
364 #define M_MASTER_DLL_TAP_COUNT_OFFSET    0x3f
365 #define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
366 #define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
367 
368 #define S_SLAVE_DLL_RESET    11
369 #define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
370 #define F_SLAVE_DLL_RESET    V_SLAVE_DLL_RESET(1U)
371 
372 #define S_SLAVE_DLL_DELTA    12
373 #define M_SLAVE_DLL_DELTA    0xf
374 #define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
375 #define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
376 
377 #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT    17
378 #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT    0x3f
379 #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
380 #define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
381 
382 #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE    23
383 #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
384 #define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE    V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
385 
386 #define S_SLAVE_DELAY_LINE_TAP_COUNT    24
387 #define M_SLAVE_DELAY_LINE_TAP_COUNT    0x3f
388 #define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
389 #define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
390 
391 #define A_MC3_ECC_CNTL 0x118
392 
393 #define S_ECC_GENERATION_ENABLE    0
394 #define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
395 #define F_ECC_GENERATION_ENABLE    V_ECC_GENERATION_ENABLE(1U)
396 
397 #define S_ECC_CHECK_ENABLE    1
398 #define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
399 #define F_ECC_CHECK_ENABLE    V_ECC_CHECK_ENABLE(1U)
400 
401 #define S_CORRECTABLE_ERROR_COUNT    2
402 #define M_CORRECTABLE_ERROR_COUNT    0xff
403 #define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
404 #define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
405 
406 #define S_UNCORRECTABLE_ERROR_COUNT    10
407 #define M_UNCORRECTABLE_ERROR_COUNT    0xff
408 #define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
409 #define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
410 
411 #define A_MC3_CE_ADDR 0x11c
412 
413 #define S_MC3_CE_ADDR    4
414 #define M_MC3_CE_ADDR    0xfffffff
415 #define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
416 #define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
417 
418 #define A_MC3_CE_DATA0 0x120
419 #define A_MC3_CE_DATA1 0x124
420 #define A_MC3_CE_DATA2 0x128
421 #define A_MC3_CE_DATA3 0x12c
422 #define A_MC3_CE_DATA4 0x130
423 #define A_MC3_UE_ADDR 0x134
424 
425 #define S_MC3_UE_ADDR    4
426 #define M_MC3_UE_ADDR    0xfffffff
427 #define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
428 #define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
429 
430 #define A_MC3_UE_DATA0 0x138
431 #define A_MC3_UE_DATA1 0x13c
432 #define A_MC3_UE_DATA2 0x140
433 #define A_MC3_UE_DATA3 0x144
434 #define A_MC3_UE_DATA4 0x148
435 #define A_MC3_BD_ADDR 0x14c
436 #define A_MC3_BD_DATA0 0x150
437 #define A_MC3_BD_DATA1 0x154
438 #define A_MC3_BD_DATA2 0x158
439 #define A_MC3_BD_DATA3 0x15c
440 #define A_MC3_BD_DATA4 0x160
441 #define A_MC3_BD_OP 0x164
442 
443 #define S_BACK_DOOR_OPERATION    0
444 #define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
445 #define F_BACK_DOOR_OPERATION    V_BACK_DOOR_OPERATION(1U)
446 
447 #define A_MC3_BIST_ADDR_BEG 0x168
448 #define A_MC3_BIST_ADDR_END 0x16c
449 #define A_MC3_BIST_DATA 0x170
450 #define A_MC3_BIST_OP 0x174
451 
452 #define S_OP    0
453 #define V_OP(x) ((x) << S_OP)
454 #define F_OP    V_OP(1U)
455 
456 #define S_DATA_PATTERN    1
457 #define M_DATA_PATTERN    0x3
458 #define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
459 #define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
460 
461 #define S_CONTINUOUS    3
462 #define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
463 #define F_CONTINUOUS    V_CONTINUOUS(1U)
464 
465 #define A_MC3_INT_ENABLE 0x178
466 
467 #define S_MC3_CORR_ERR    0
468 #define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
469 #define F_MC3_CORR_ERR    V_MC3_CORR_ERR(1U)
470 
471 #define S_MC3_UNCORR_ERR    1
472 #define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
473 #define F_MC3_UNCORR_ERR    V_MC3_UNCORR_ERR(1U)
474 
475 #define S_MC3_PARITY_ERR    2
476 #define M_MC3_PARITY_ERR    0xff
477 #define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
478 #define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
479 
480 #define S_MC3_ADDR_ERR    10
481 #define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
482 #define F_MC3_ADDR_ERR    V_MC3_ADDR_ERR(1U)
483 
484 #define A_MC3_INT_CAUSE 0x17c
485 
486 /* MC4 registers */
487 #define A_MC4_CFG 0x180
488 
489 #define S_POWER_UP    0
490 #define V_POWER_UP(x) ((x) << S_POWER_UP)
491 #define F_POWER_UP    V_POWER_UP(1U)
492 
493 #define S_MC4_BANK_CYCLE    8
494 #define M_MC4_BANK_CYCLE    0x7
495 #define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
496 #define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
497 
498 #define S_MC4_NARROW    24
499 #define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
500 #define F_MC4_NARROW    V_MC4_NARROW(1U)
501 
502 #define S_MC4_SLOW    25
503 #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
504 #define F_MC4_SLOW    V_MC4_SLOW(1U)
505 
506 #define S_MC4A_WIDTH    24
507 #define M_MC4A_WIDTH    0x3
508 #define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
509 #define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
510 
511 #define S_MC4A_SLOW    26
512 #define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
513 #define F_MC4A_SLOW    V_MC4A_SLOW(1U)
514 
515 #define A_MC4_MODE 0x184
516 
517 #define S_MC4_MODE    0
518 #define M_MC4_MODE    0x7fff
519 #define V_MC4_MODE(x) ((x) << S_MC4_MODE)
520 #define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
521 
522 #define A_MC4_EXT_MODE 0x188
523 
524 #define S_MC4_EXTENDED_MODE    0
525 #define M_MC4_EXTENDED_MODE    0x7fff
526 #define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
527 #define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
528 
529 #define A_MC4_REFRESH 0x190
530 #define A_MC4_STROBE 0x194
531 #define A_MC4_ECC_CNTL 0x198
532 #define A_MC4_CE_ADDR 0x19c
533 
534 #define S_MC4_CE_ADDR    4
535 #define M_MC4_CE_ADDR    0xffffff
536 #define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
537 #define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
538 
539 #define A_MC4_CE_DATA0 0x1a0
540 #define A_MC4_CE_DATA1 0x1a4
541 #define A_MC4_CE_DATA2 0x1a8
542 #define A_MC4_CE_DATA3 0x1ac
543 #define A_MC4_CE_DATA4 0x1b0
544 #define A_MC4_UE_ADDR 0x1b4
545 
546 #define S_MC4_UE_ADDR    4
547 #define M_MC4_UE_ADDR    0xffffff
548 #define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
549 #define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
550 
551 #define A_MC4_UE_DATA0 0x1b8
552 #define A_MC4_UE_DATA1 0x1bc
553 #define A_MC4_UE_DATA2 0x1c0
554 #define A_MC4_UE_DATA3 0x1c4
555 #define A_MC4_UE_DATA4 0x1c8
556 #define A_MC4_BD_ADDR 0x1cc
557 
558 #define S_MC4_BACK_DOOR_ADDR    0
559 #define M_MC4_BACK_DOOR_ADDR    0xfffffff
560 #define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
561 #define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
562 
563 #define A_MC4_BD_DATA0 0x1d0
564 #define A_MC4_BD_DATA1 0x1d4
565 #define A_MC4_BD_DATA2 0x1d8
566 #define A_MC4_BD_DATA3 0x1dc
567 #define A_MC4_BD_DATA4 0x1e0
568 #define A_MC4_BD_OP 0x1e4
569 
570 #define S_OPERATION    0
571 #define V_OPERATION(x) ((x) << S_OPERATION)
572 #define F_OPERATION    V_OPERATION(1U)
573 
574 #define A_MC4_BIST_ADDR_BEG 0x1e8
575 #define A_MC4_BIST_ADDR_END 0x1ec
576 #define A_MC4_BIST_DATA 0x1f0
577 #define A_MC4_BIST_OP 0x1f4
578 #define A_MC4_INT_ENABLE 0x1f8
579 
580 #define S_MC4_CORR_ERR    0
581 #define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
582 #define F_MC4_CORR_ERR    V_MC4_CORR_ERR(1U)
583 
584 #define S_MC4_UNCORR_ERR    1
585 #define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
586 #define F_MC4_UNCORR_ERR    V_MC4_UNCORR_ERR(1U)
587 
588 #define S_MC4_ADDR_ERR    2
589 #define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
590 #define F_MC4_ADDR_ERR    V_MC4_ADDR_ERR(1U)
591 
592 #define A_MC4_INT_CAUSE 0x1fc
593 
594 /* TPI registers */
595 #define A_TPI_ADDR 0x280
596 
597 #define S_TPI_ADDRESS    0
598 #define M_TPI_ADDRESS    0xffffff
599 #define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
600 #define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
601 
602 #define A_TPI_WR_DATA 0x284
603 #define A_TPI_RD_DATA 0x288
604 #define A_TPI_CSR 0x28c
605 
606 #define S_TPIWR    0
607 #define V_TPIWR(x) ((x) << S_TPIWR)
608 #define F_TPIWR    V_TPIWR(1U)
609 
610 #define S_TPIRDY    1
611 #define V_TPIRDY(x) ((x) << S_TPIRDY)
612 #define F_TPIRDY    V_TPIRDY(1U)
613 
614 #define S_INT_DIR    31
615 #define V_INT_DIR(x) ((x) << S_INT_DIR)
616 #define F_INT_DIR    V_INT_DIR(1U)
617 
618 #define A_TPI_PAR 0x29c
619 
620 #define S_TPIPAR    0
621 #define M_TPIPAR    0x7f
622 #define V_TPIPAR(x) ((x) << S_TPIPAR)
623 #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
624 
625 
626 /* TP registers */
627 #define A_TP_IN_CONFIG 0x300
628 
629 #define S_TP_IN_CSPI_TUNNEL    0
630 #define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
631 #define F_TP_IN_CSPI_TUNNEL    V_TP_IN_CSPI_TUNNEL(1U)
632 
633 #define S_TP_IN_CSPI_ETHERNET    1
634 #define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
635 #define F_TP_IN_CSPI_ETHERNET    V_TP_IN_CSPI_ETHERNET(1U)
636 
637 #define S_TP_IN_CSPI_CPL    3
638 #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
639 #define F_TP_IN_CSPI_CPL    V_TP_IN_CSPI_CPL(1U)
640 
641 #define S_TP_IN_CSPI_POS    4
642 #define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
643 #define F_TP_IN_CSPI_POS    V_TP_IN_CSPI_POS(1U)
644 
645 #define S_TP_IN_CSPI_CHECK_IP_CSUM    5
646 #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
647 #define F_TP_IN_CSPI_CHECK_IP_CSUM    V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
648 
649 #define S_TP_IN_CSPI_CHECK_TCP_CSUM    6
650 #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
651 #define F_TP_IN_CSPI_CHECK_TCP_CSUM    V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
652 
653 #define S_TP_IN_ESPI_TUNNEL    7
654 #define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
655 #define F_TP_IN_ESPI_TUNNEL    V_TP_IN_ESPI_TUNNEL(1U)
656 
657 #define S_TP_IN_ESPI_ETHERNET    8
658 #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
659 #define F_TP_IN_ESPI_ETHERNET    V_TP_IN_ESPI_ETHERNET(1U)
660 
661 #define S_TP_IN_ESPI_CPL    10
662 #define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
663 #define F_TP_IN_ESPI_CPL    V_TP_IN_ESPI_CPL(1U)
664 
665 #define S_TP_IN_ESPI_POS    11
666 #define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
667 #define F_TP_IN_ESPI_POS    V_TP_IN_ESPI_POS(1U)
668 
669 #define S_TP_IN_ESPI_CHECK_IP_CSUM    12
670 #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
671 #define F_TP_IN_ESPI_CHECK_IP_CSUM    V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
672 
673 #define S_TP_IN_ESPI_CHECK_TCP_CSUM    13
674 #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
675 #define F_TP_IN_ESPI_CHECK_TCP_CSUM    V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
676 
677 #define S_OFFLOAD_DISABLE    14
678 #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
679 #define F_OFFLOAD_DISABLE    V_OFFLOAD_DISABLE(1U)
680 
681 #define A_TP_OUT_CONFIG 0x304
682 
683 #define S_TP_OUT_C_ETH    0
684 #define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
685 #define F_TP_OUT_C_ETH    V_TP_OUT_C_ETH(1U)
686 
687 #define S_TP_OUT_CSPI_CPL    2
688 #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
689 #define F_TP_OUT_CSPI_CPL    V_TP_OUT_CSPI_CPL(1U)
690 
691 #define S_TP_OUT_CSPI_POS    3
692 #define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
693 #define F_TP_OUT_CSPI_POS    V_TP_OUT_CSPI_POS(1U)
694 
695 #define S_TP_OUT_CSPI_GENERATE_IP_CSUM    4
696 #define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
697 #define F_TP_OUT_CSPI_GENERATE_IP_CSUM    V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
698 
699 #define S_TP_OUT_CSPI_GENERATE_TCP_CSUM    5
700 #define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
701 #define F_TP_OUT_CSPI_GENERATE_TCP_CSUM    V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
702 
703 #define S_TP_OUT_ESPI_ETHERNET    6
704 #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
705 #define F_TP_OUT_ESPI_ETHERNET    V_TP_OUT_ESPI_ETHERNET(1U)
706 
707 #define S_TP_OUT_ESPI_TAG_ETHERNET    7
708 #define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
709 #define F_TP_OUT_ESPI_TAG_ETHERNET    V_TP_OUT_ESPI_TAG_ETHERNET(1U)
710 
711 #define S_TP_OUT_ESPI_CPL    8
712 #define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
713 #define F_TP_OUT_ESPI_CPL    V_TP_OUT_ESPI_CPL(1U)
714 
715 #define S_TP_OUT_ESPI_POS    9
716 #define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
717 #define F_TP_OUT_ESPI_POS    V_TP_OUT_ESPI_POS(1U)
718 
719 #define S_TP_OUT_ESPI_GENERATE_IP_CSUM    10
720 #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
721 #define F_TP_OUT_ESPI_GENERATE_IP_CSUM    V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
722 
723 #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM    11
724 #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
725 #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM    V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
726 
727 #define A_TP_GLOBAL_CONFIG 0x308
728 
729 #define S_IP_TTL    0
730 #define M_IP_TTL    0xff
731 #define V_IP_TTL(x) ((x) << S_IP_TTL)
732 #define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
733 
734 #define S_TCAM_SERVER_REGION_USAGE    8
735 #define M_TCAM_SERVER_REGION_USAGE    0x3
736 #define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
737 #define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
738 
739 #define S_QOS_MAPPING    10
740 #define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
741 #define F_QOS_MAPPING    V_QOS_MAPPING(1U)
742 
743 #define S_TCP_CSUM    11
744 #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
745 #define F_TCP_CSUM    V_TCP_CSUM(1U)
746 
747 #define S_UDP_CSUM    12
748 #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
749 #define F_UDP_CSUM    V_UDP_CSUM(1U)
750 
751 #define S_IP_CSUM    13
752 #define V_IP_CSUM(x) ((x) << S_IP_CSUM)
753 #define F_IP_CSUM    V_IP_CSUM(1U)
754 
755 #define S_IP_ID_SPLIT    14
756 #define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
757 #define F_IP_ID_SPLIT    V_IP_ID_SPLIT(1U)
758 
759 #define S_PATH_MTU    15
760 #define V_PATH_MTU(x) ((x) << S_PATH_MTU)
761 #define F_PATH_MTU    V_PATH_MTU(1U)
762 
763 #define S_5TUPLE_LOOKUP    17
764 #define M_5TUPLE_LOOKUP    0x3
765 #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
766 #define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
767 
768 #define S_IP_FRAGMENT_DROP    19
769 #define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
770 #define F_IP_FRAGMENT_DROP    V_IP_FRAGMENT_DROP(1U)
771 
772 #define S_PING_DROP    20
773 #define V_PING_DROP(x) ((x) << S_PING_DROP)
774 #define F_PING_DROP    V_PING_DROP(1U)
775 
776 #define S_PROTECT_MODE    21
777 #define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
778 #define F_PROTECT_MODE    V_PROTECT_MODE(1U)
779 
780 #define S_SYN_COOKIE_ALGORITHM    22
781 #define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
782 #define F_SYN_COOKIE_ALGORITHM    V_SYN_COOKIE_ALGORITHM(1U)
783 
784 #define S_ATTACK_FILTER    23
785 #define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
786 #define F_ATTACK_FILTER    V_ATTACK_FILTER(1U)
787 
788 #define S_INTERFACE_TYPE    24
789 #define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
790 #define F_INTERFACE_TYPE    V_INTERFACE_TYPE(1U)
791 
792 #define S_DISABLE_RX_FLOW_CONTROL    25
793 #define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
794 #define F_DISABLE_RX_FLOW_CONTROL    V_DISABLE_RX_FLOW_CONTROL(1U)
795 
796 #define S_SYN_COOKIE_PARAMETER    26
797 #define M_SYN_COOKIE_PARAMETER    0x3f
798 #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
799 #define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
800 
801 #define A_TP_GLOBAL_RX_CREDITS 0x30c
802 #define A_TP_CM_SIZE 0x310
803 #define A_TP_CM_MM_BASE 0x314
804 
805 #define S_CM_MEMMGR_BASE    0
806 #define M_CM_MEMMGR_BASE    0xfffffff
807 #define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
808 #define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
809 
810 #define A_TP_CM_TIMER_BASE 0x318
811 
812 #define S_CM_TIMER_BASE    0
813 #define M_CM_TIMER_BASE    0xfffffff
814 #define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
815 #define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
816 
817 #define A_TP_PM_SIZE 0x31c
818 #define A_TP_PM_TX_BASE 0x320
819 #define A_TP_PM_DEFRAG_BASE 0x324
820 #define A_TP_PM_RX_BASE 0x328
821 #define A_TP_PM_RX_PG_SIZE 0x32c
822 #define A_TP_PM_RX_MAX_PGS 0x330
823 #define A_TP_PM_TX_PG_SIZE 0x334
824 #define A_TP_PM_TX_MAX_PGS 0x338
825 #define A_TP_TCP_OPTIONS 0x340
826 
827 #define S_TIMESTAMP    0
828 #define M_TIMESTAMP    0x3
829 #define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
830 #define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
831 
832 #define S_WINDOW_SCALE    2
833 #define M_WINDOW_SCALE    0x3
834 #define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
835 #define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
836 
837 #define S_SACK    4
838 #define M_SACK    0x3
839 #define V_SACK(x) ((x) << S_SACK)
840 #define G_SACK(x) (((x) >> S_SACK) & M_SACK)
841 
842 #define S_ECN    6
843 #define M_ECN    0x3
844 #define V_ECN(x) ((x) << S_ECN)
845 #define G_ECN(x) (((x) >> S_ECN) & M_ECN)
846 
847 #define S_SACK_ALGORITHM    8
848 #define M_SACK_ALGORITHM    0x3
849 #define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
850 #define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
851 
852 #define S_MSS    10
853 #define V_MSS(x) ((x) << S_MSS)
854 #define F_MSS    V_MSS(1U)
855 
856 #define S_DEFAULT_PEER_MSS    16
857 #define M_DEFAULT_PEER_MSS    0xffff
858 #define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
859 #define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
860 
861 #define A_TP_DACK_CONFIG 0x344
862 
863 #define S_DACK_MODE    0
864 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
865 #define F_DACK_MODE    V_DACK_MODE(1U)
866 
867 #define S_DACK_AUTO_MGMT    1
868 #define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
869 #define F_DACK_AUTO_MGMT    V_DACK_AUTO_MGMT(1U)
870 
871 #define S_DACK_AUTO_CAREFUL    2
872 #define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
873 #define F_DACK_AUTO_CAREFUL    V_DACK_AUTO_CAREFUL(1U)
874 
875 #define S_DACK_MSS_SELECTOR    3
876 #define M_DACK_MSS_SELECTOR    0x3
877 #define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
878 #define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
879 
880 #define S_DACK_BYTE_THRESHOLD    5
881 #define M_DACK_BYTE_THRESHOLD    0xfffff
882 #define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
883 #define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
884 
885 #define A_TP_PC_CONFIG 0x348
886 
887 #define S_TP_ACCESS_LATENCY    0
888 #define M_TP_ACCESS_LATENCY    0xf
889 #define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
890 #define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
891 
892 #define S_HELD_FIN_DISABLE    4
893 #define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
894 #define F_HELD_FIN_DISABLE    V_HELD_FIN_DISABLE(1U)
895 
896 #define S_DDP_FC_ENABLE    5
897 #define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
898 #define F_DDP_FC_ENABLE    V_DDP_FC_ENABLE(1U)
899 
900 #define S_RDMA_ERR_ENABLE    6
901 #define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
902 #define F_RDMA_ERR_ENABLE    V_RDMA_ERR_ENABLE(1U)
903 
904 #define S_FAST_PDU_DELIVERY    7
905 #define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
906 #define F_FAST_PDU_DELIVERY    V_FAST_PDU_DELIVERY(1U)
907 
908 #define S_CLEAR_FIN    8
909 #define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
910 #define F_CLEAR_FIN    V_CLEAR_FIN(1U)
911 
912 #define S_DIS_TX_FILL_WIN_PUSH	  12
913 #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
914 #define F_DIS_TX_FILL_WIN_PUSH	  V_DIS_TX_FILL_WIN_PUSH(1U)
915 
916 #define S_TP_PC_REV    30
917 #define M_TP_PC_REV    0x3
918 #define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
919 #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
920 
921 #define A_TP_BACKOFF0 0x350
922 
923 #define S_ELEMENT0    0
924 #define M_ELEMENT0    0xff
925 #define V_ELEMENT0(x) ((x) << S_ELEMENT0)
926 #define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
927 
928 #define S_ELEMENT1    8
929 #define M_ELEMENT1    0xff
930 #define V_ELEMENT1(x) ((x) << S_ELEMENT1)
931 #define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
932 
933 #define S_ELEMENT2    16
934 #define M_ELEMENT2    0xff
935 #define V_ELEMENT2(x) ((x) << S_ELEMENT2)
936 #define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
937 
938 #define S_ELEMENT3    24
939 #define M_ELEMENT3    0xff
940 #define V_ELEMENT3(x) ((x) << S_ELEMENT3)
941 #define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
942 
943 #define A_TP_BACKOFF1 0x354
944 #define A_TP_BACKOFF2 0x358
945 #define A_TP_BACKOFF3 0x35c
946 #define A_TP_PARA_REG0 0x360
947 
948 #define S_VAR_MULT    0
949 #define M_VAR_MULT    0xf
950 #define V_VAR_MULT(x) ((x) << S_VAR_MULT)
951 #define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
952 
953 #define S_VAR_GAIN    4
954 #define M_VAR_GAIN    0xf
955 #define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
956 #define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
957 
958 #define S_SRTT_GAIN    8
959 #define M_SRTT_GAIN    0xf
960 #define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
961 #define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
962 
963 #define S_RTTVAR_INIT    12
964 #define M_RTTVAR_INIT    0xf
965 #define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
966 #define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
967 
968 #define S_DUP_THRESH    20
969 #define M_DUP_THRESH    0xf
970 #define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
971 #define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
972 
973 #define S_INIT_CONG_WIN    24
974 #define M_INIT_CONG_WIN    0x7
975 #define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
976 #define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
977 
978 #define A_TP_PARA_REG1 0x364
979 
980 #define S_INITIAL_SLOW_START_THRESHOLD    0
981 #define M_INITIAL_SLOW_START_THRESHOLD    0xffff
982 #define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
983 #define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
984 
985 #define S_RECEIVE_BUFFER_SIZE    16
986 #define M_RECEIVE_BUFFER_SIZE    0xffff
987 #define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
988 #define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
989 
990 #define A_TP_PARA_REG2 0x368
991 
992 #define S_RX_COALESCE_SIZE    0
993 #define M_RX_COALESCE_SIZE    0xffff
994 #define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
995 #define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
996 
997 #define S_MAX_RX_SIZE    16
998 #define M_MAX_RX_SIZE    0xffff
999 #define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
1000 #define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
1001 
1002 #define A_TP_PARA_REG3 0x36c
1003 
1004 #define S_RX_COALESCING_PSH_DELIVER    0
1005 #define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1006 #define F_RX_COALESCING_PSH_DELIVER    V_RX_COALESCING_PSH_DELIVER(1U)
1007 
1008 #define S_RX_COALESCING_ENABLE    1
1009 #define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1010 #define F_RX_COALESCING_ENABLE    V_RX_COALESCING_ENABLE(1U)
1011 
1012 #define S_TAHOE_ENABLE    2
1013 #define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1014 #define F_TAHOE_ENABLE    V_TAHOE_ENABLE(1U)
1015 
1016 #define S_MAX_REORDER_FRAGMENTS    12
1017 #define M_MAX_REORDER_FRAGMENTS    0x7
1018 #define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1019 #define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1020 
1021 #define A_TP_TIMER_RESOLUTION 0x390
1022 
1023 #define S_DELAYED_ACK_TIMER_RESOLUTION    0
1024 #define M_DELAYED_ACK_TIMER_RESOLUTION    0x3f
1025 #define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1026 #define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1027 
1028 #define S_GENERIC_TIMER_RESOLUTION    16
1029 #define M_GENERIC_TIMER_RESOLUTION    0x3f
1030 #define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1031 #define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1032 
1033 #define A_TP_2MSL 0x394
1034 
1035 #define S_2MSL    0
1036 #define M_2MSL    0x3fffffff
1037 #define V_2MSL(x) ((x) << S_2MSL)
1038 #define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1039 
1040 #define A_TP_RXT_MIN 0x398
1041 
1042 #define S_RETRANSMIT_TIMER_MIN    0
1043 #define M_RETRANSMIT_TIMER_MIN    0xffff
1044 #define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1045 #define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1046 
1047 #define A_TP_RXT_MAX 0x39c
1048 
1049 #define S_RETRANSMIT_TIMER_MAX    0
1050 #define M_RETRANSMIT_TIMER_MAX    0x3fffffff
1051 #define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1052 #define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1053 
1054 #define A_TP_PERS_MIN 0x3a0
1055 
1056 #define S_PERSIST_TIMER_MIN    0
1057 #define M_PERSIST_TIMER_MIN    0xffff
1058 #define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1059 #define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1060 
1061 #define A_TP_PERS_MAX 0x3a4
1062 
1063 #define S_PERSIST_TIMER_MAX    0
1064 #define M_PERSIST_TIMER_MAX    0x3fffffff
1065 #define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1066 #define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1067 
1068 #define A_TP_KEEP_IDLE 0x3ac
1069 
1070 #define S_KEEP_ALIVE_IDLE_TIME    0
1071 #define M_KEEP_ALIVE_IDLE_TIME    0x3fffffff
1072 #define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1073 #define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1074 
1075 #define A_TP_KEEP_INTVL 0x3b0
1076 
1077 #define S_KEEP_ALIVE_INTERVAL_TIME    0
1078 #define M_KEEP_ALIVE_INTERVAL_TIME    0x3fffffff
1079 #define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1080 #define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1081 
1082 #define A_TP_INIT_SRTT 0x3b4
1083 
1084 #define S_INITIAL_SRTT    0
1085 #define M_INITIAL_SRTT    0xffff
1086 #define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1087 #define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1088 
1089 #define A_TP_DACK_TIME 0x3b8
1090 
1091 #define S_DELAYED_ACK_TIME    0
1092 #define M_DELAYED_ACK_TIME    0x7ff
1093 #define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1094 #define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1095 
1096 #define A_TP_FINWAIT2_TIME 0x3bc
1097 
1098 #define S_FINWAIT2_TIME    0
1099 #define M_FINWAIT2_TIME    0x3fffffff
1100 #define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1101 #define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1102 
1103 #define A_TP_FAST_FINWAIT2_TIME 0x3c0
1104 
1105 #define S_FAST_FINWAIT2_TIME    0
1106 #define M_FAST_FINWAIT2_TIME    0x3fffffff
1107 #define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1108 #define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1109 
1110 #define A_TP_SHIFT_CNT 0x3c4
1111 
1112 #define S_KEEPALIVE_MAX    0
1113 #define M_KEEPALIVE_MAX    0xff
1114 #define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1115 #define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1116 
1117 #define S_WINDOWPROBE_MAX    8
1118 #define M_WINDOWPROBE_MAX    0xff
1119 #define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1120 #define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1121 
1122 #define S_RETRANSMISSION_MAX    16
1123 #define M_RETRANSMISSION_MAX    0xff
1124 #define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1125 #define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1126 
1127 #define S_SYN_MAX    24
1128 #define M_SYN_MAX    0xff
1129 #define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1130 #define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1131 
1132 #define A_TP_QOS_REG0 0x3e0
1133 
1134 #define S_L3_VALUE    0
1135 #define M_L3_VALUE    0x3f
1136 #define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1137 #define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1138 
1139 #define A_TP_QOS_REG1 0x3e4
1140 #define A_TP_QOS_REG2 0x3e8
1141 #define A_TP_QOS_REG3 0x3ec
1142 #define A_TP_QOS_REG4 0x3f0
1143 #define A_TP_QOS_REG5 0x3f4
1144 #define A_TP_QOS_REG6 0x3f8
1145 #define A_TP_QOS_REG7 0x3fc
1146 #define A_TP_MTU_REG0 0x404
1147 #define A_TP_MTU_REG1 0x408
1148 #define A_TP_MTU_REG2 0x40c
1149 #define A_TP_MTU_REG3 0x410
1150 #define A_TP_MTU_REG4 0x414
1151 #define A_TP_MTU_REG5 0x418
1152 #define A_TP_MTU_REG6 0x41c
1153 #define A_TP_MTU_REG7 0x420
1154 #define A_TP_RESET 0x44c
1155 
1156 #define S_TP_RESET    0
1157 #define V_TP_RESET(x) ((x) << S_TP_RESET)
1158 #define F_TP_RESET    V_TP_RESET(1U)
1159 
1160 #define S_CM_MEMMGR_INIT    1
1161 #define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1162 #define F_CM_MEMMGR_INIT    V_CM_MEMMGR_INIT(1U)
1163 
1164 #define A_TP_MIB_INDEX 0x450
1165 #define A_TP_MIB_DATA 0x454
1166 #define A_TP_SYNC_TIME_HI 0x458
1167 #define A_TP_SYNC_TIME_LO 0x45c
1168 #define A_TP_CM_MM_RX_FLST_BASE 0x460
1169 
1170 #define S_CM_MEMMGR_RX_FREE_LIST_BASE    0
1171 #define M_CM_MEMMGR_RX_FREE_LIST_BASE    0xfffffff
1172 #define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1173 #define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1174 
1175 #define A_TP_CM_MM_TX_FLST_BASE 0x464
1176 
1177 #define S_CM_MEMMGR_TX_FREE_LIST_BASE    0
1178 #define M_CM_MEMMGR_TX_FREE_LIST_BASE    0xfffffff
1179 #define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1180 #define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1181 
1182 #define A_TP_CM_MM_P_FLST_BASE 0x468
1183 
1184 #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE    0
1185 #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE    0xfffffff
1186 #define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1187 #define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1188 
1189 #define A_TP_CM_MM_MAX_P 0x46c
1190 
1191 #define S_CM_MEMMGR_MAX_PSTRUCT    0
1192 #define M_CM_MEMMGR_MAX_PSTRUCT    0xfffffff
1193 #define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1194 #define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1195 
1196 #define A_TP_INT_ENABLE 0x470
1197 
1198 #define S_TX_FREE_LIST_EMPTY    0
1199 #define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1200 #define F_TX_FREE_LIST_EMPTY    V_TX_FREE_LIST_EMPTY(1U)
1201 
1202 #define S_RX_FREE_LIST_EMPTY    1
1203 #define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1204 #define F_RX_FREE_LIST_EMPTY    V_RX_FREE_LIST_EMPTY(1U)
1205 
1206 #define A_TP_INT_CAUSE 0x474
1207 #define A_TP_TIMER_SEPARATOR 0x4a4
1208 
1209 #define S_DISABLE_PAST_TIMER_INSERTION    0
1210 #define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1211 #define F_DISABLE_PAST_TIMER_INSERTION    V_DISABLE_PAST_TIMER_INSERTION(1U)
1212 
1213 #define S_MODULATION_TIMER_SEPARATOR    1
1214 #define M_MODULATION_TIMER_SEPARATOR    0x7fff
1215 #define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1216 #define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1217 
1218 #define S_GLOBAL_TIMER_SEPARATOR    16
1219 #define M_GLOBAL_TIMER_SEPARATOR    0xffff
1220 #define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1221 #define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1222 
1223 #define A_TP_CM_FC_MODE 0x4b0
1224 #define A_TP_PC_CONGESTION_CNTL 0x4b4
1225 #define A_TP_TX_DROP_CONFIG 0x4b8
1226 
1227 #define S_ENABLE_TX_DROP    31
1228 #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
1229 #define F_ENABLE_TX_DROP    V_ENABLE_TX_DROP(1U)
1230 
1231 #define S_ENABLE_TX_ERROR    30
1232 #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
1233 #define F_ENABLE_TX_ERROR    V_ENABLE_TX_ERROR(1U)
1234 
1235 #define S_DROP_TICKS_CNT    4
1236 #define M_DROP_TICKS_CNT    0x3ffffff
1237 #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1238 #define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
1239 
1240 #define S_NUM_PKTS_DROPPED    0
1241 #define M_NUM_PKTS_DROPPED    0xf
1242 #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1243 #define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1244 
1245 #define A_TP_TX_DROP_COUNT 0x4bc
1246 
1247 /* RAT registers */
1248 #define A_RAT_ROUTE_CONTROL 0x580
1249 
1250 #define S_USE_ROUTE_TABLE    0
1251 #define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1252 #define F_USE_ROUTE_TABLE    V_USE_ROUTE_TABLE(1U)
1253 
1254 #define S_ENABLE_CSPI    1
1255 #define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1256 #define F_ENABLE_CSPI    V_ENABLE_CSPI(1U)
1257 
1258 #define S_ENABLE_PCIX    2
1259 #define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1260 #define F_ENABLE_PCIX    V_ENABLE_PCIX(1U)
1261 
1262 #define A_RAT_ROUTE_TABLE_INDEX 0x584
1263 
1264 #define S_ROUTE_TABLE_INDEX    0
1265 #define M_ROUTE_TABLE_INDEX    0xf
1266 #define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1267 #define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1268 
1269 #define A_RAT_ROUTE_TABLE_DATA 0x588
1270 #define A_RAT_NO_ROUTE 0x58c
1271 
1272 #define S_CPL_OPCODE    0
1273 #define M_CPL_OPCODE    0xff
1274 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1275 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1276 
1277 #define A_RAT_INTR_ENABLE 0x590
1278 
1279 #define S_ZEROROUTEERROR    0
1280 #define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1281 #define F_ZEROROUTEERROR    V_ZEROROUTEERROR(1U)
1282 
1283 #define S_CSPIFRAMINGERROR    1
1284 #define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1285 #define F_CSPIFRAMINGERROR    V_CSPIFRAMINGERROR(1U)
1286 
1287 #define S_SGEFRAMINGERROR    2
1288 #define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1289 #define F_SGEFRAMINGERROR    V_SGEFRAMINGERROR(1U)
1290 
1291 #define S_TPFRAMINGERROR    3
1292 #define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1293 #define F_TPFRAMINGERROR    V_TPFRAMINGERROR(1U)
1294 
1295 #define A_RAT_INTR_CAUSE 0x594
1296 
1297 /* CSPI registers */
1298 #define A_CSPI_RX_AE_WM 0x810
1299 #define A_CSPI_RX_AF_WM 0x814
1300 #define A_CSPI_CALENDAR_LEN 0x818
1301 
1302 #define S_CALENDARLENGTH    0
1303 #define M_CALENDARLENGTH    0xffff
1304 #define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1305 #define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1306 
1307 #define A_CSPI_FIFO_STATUS_ENABLE 0x820
1308 
1309 #define S_FIFOSTATUSENABLE    0
1310 #define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1311 #define F_FIFOSTATUSENABLE    V_FIFOSTATUSENABLE(1U)
1312 
1313 #define A_CSPI_MAXBURST1_MAXBURST2 0x828
1314 
1315 #define S_MAXBURST1    0
1316 #define M_MAXBURST1    0xffff
1317 #define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1318 #define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1319 
1320 #define S_MAXBURST2    16
1321 #define M_MAXBURST2    0xffff
1322 #define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1323 #define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1324 
1325 #define A_CSPI_TRAIN 0x82c
1326 
1327 #define S_CSPI_TRAIN_ALPHA    0
1328 #define M_CSPI_TRAIN_ALPHA    0xffff
1329 #define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1330 #define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1331 
1332 #define S_CSPI_TRAIN_DATA_MAXT    16
1333 #define M_CSPI_TRAIN_DATA_MAXT    0xffff
1334 #define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1335 #define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1336 
1337 #define A_CSPI_INTR_STATUS 0x848
1338 
1339 #define S_DIP4ERR    0
1340 #define V_DIP4ERR(x) ((x) << S_DIP4ERR)
1341 #define F_DIP4ERR    V_DIP4ERR(1U)
1342 
1343 #define S_RXDROP    1
1344 #define V_RXDROP(x) ((x) << S_RXDROP)
1345 #define F_RXDROP    V_RXDROP(1U)
1346 
1347 #define S_TXDROP    2
1348 #define V_TXDROP(x) ((x) << S_TXDROP)
1349 #define F_TXDROP    V_TXDROP(1U)
1350 
1351 #define S_RXOVERFLOW    3
1352 #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
1353 #define F_RXOVERFLOW    V_RXOVERFLOW(1U)
1354 
1355 #define S_RAMPARITYERR    4
1356 #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
1357 #define F_RAMPARITYERR    V_RAMPARITYERR(1U)
1358 
1359 #define A_CSPI_INTR_ENABLE 0x84c
1360 
1361 /* ESPI registers */
1362 #define A_ESPI_SCH_TOKEN0 0x880
1363 
1364 #define S_SCHTOKEN0    0
1365 #define M_SCHTOKEN0    0xffff
1366 #define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1367 #define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1368 
1369 #define A_ESPI_SCH_TOKEN1 0x884
1370 
1371 #define S_SCHTOKEN1    0
1372 #define M_SCHTOKEN1    0xffff
1373 #define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1374 #define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1375 
1376 #define A_ESPI_SCH_TOKEN2 0x888
1377 
1378 #define S_SCHTOKEN2    0
1379 #define M_SCHTOKEN2    0xffff
1380 #define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1381 #define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1382 
1383 #define A_ESPI_SCH_TOKEN3 0x88c
1384 
1385 #define S_SCHTOKEN3    0
1386 #define M_SCHTOKEN3    0xffff
1387 #define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1388 #define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1389 
1390 #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1391 
1392 #define S_ALMOSTEMPTY    0
1393 #define M_ALMOSTEMPTY    0xffff
1394 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1395 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1396 
1397 #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1398 
1399 #define S_ALMOSTFULL    0
1400 #define M_ALMOSTFULL    0xffff
1401 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1402 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1403 
1404 #define A_ESPI_CALENDAR_LENGTH 0x898
1405 #define A_PORT_CONFIG 0x89c
1406 
1407 #define S_RX_NPORTS    0
1408 #define M_RX_NPORTS    0xff
1409 #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1410 #define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
1411 
1412 #define S_TX_NPORTS    8
1413 #define M_TX_NPORTS    0xff
1414 #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1415 #define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
1416 
1417 #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
1418 
1419 #define S_RXSTATUSENABLE    0
1420 #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
1421 #define F_RXSTATUSENABLE    V_RXSTATUSENABLE(1U)
1422 
1423 #define S_TXDROPENABLE    1
1424 #define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1425 #define F_TXDROPENABLE    V_TXDROPENABLE(1U)
1426 
1427 #define S_RXENDIANMODE    2
1428 #define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1429 #define F_RXENDIANMODE    V_RXENDIANMODE(1U)
1430 
1431 #define S_TXENDIANMODE    3
1432 #define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)
1433 #define F_TXENDIANMODE    V_TXENDIANMODE(1U)
1434 
1435 #define S_INTEL1010MODE    4
1436 #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
1437 #define F_INTEL1010MODE    V_INTEL1010MODE(1U)
1438 
1439 #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
1440 #define A_ESPI_TRAIN 0x8ac
1441 
1442 #define S_MAXTRAINALPHA    0
1443 #define M_MAXTRAINALPHA    0xffff
1444 #define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)
1445 #define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)
1446 
1447 #define S_MAXTRAINDATA    16
1448 #define M_MAXTRAINDATA    0xffff
1449 #define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)
1450 #define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)
1451 
1452 #define A_RAM_STATUS 0x8b0
1453 
1454 #define S_RXFIFOPARITYERROR    0
1455 #define M_RXFIFOPARITYERROR    0x3ff
1456 #define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)
1457 #define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)
1458 
1459 #define S_TXFIFOPARITYERROR    10
1460 #define M_TXFIFOPARITYERROR    0x3ff
1461 #define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)
1462 #define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)
1463 
1464 #define S_RXFIFOOVERFLOW    20
1465 #define M_RXFIFOOVERFLOW    0x3ff
1466 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
1467 #define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)
1468 
1469 #define A_TX_DROP_COUNT0 0x8b4
1470 
1471 #define S_TXPORT0DROPCNT    0
1472 #define M_TXPORT0DROPCNT    0xffff
1473 #define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)
1474 #define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)
1475 
1476 #define S_TXPORT1DROPCNT    16
1477 #define M_TXPORT1DROPCNT    0xffff
1478 #define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)
1479 #define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)
1480 
1481 #define A_TX_DROP_COUNT1 0x8b8
1482 
1483 #define S_TXPORT2DROPCNT    0
1484 #define M_TXPORT2DROPCNT    0xffff
1485 #define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)
1486 #define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)
1487 
1488 #define S_TXPORT3DROPCNT    16
1489 #define M_TXPORT3DROPCNT    0xffff
1490 #define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)
1491 #define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)
1492 
1493 #define A_RX_DROP_COUNT0 0x8bc
1494 
1495 #define S_RXPORT0DROPCNT    0
1496 #define M_RXPORT0DROPCNT    0xffff
1497 #define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)
1498 #define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)
1499 
1500 #define S_RXPORT1DROPCNT    16
1501 #define M_RXPORT1DROPCNT    0xffff
1502 #define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)
1503 #define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)
1504 
1505 #define A_RX_DROP_COUNT1 0x8c0
1506 
1507 #define S_RXPORT2DROPCNT    0
1508 #define M_RXPORT2DROPCNT    0xffff
1509 #define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)
1510 #define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)
1511 
1512 #define S_RXPORT3DROPCNT    16
1513 #define M_RXPORT3DROPCNT    0xffff
1514 #define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)
1515 #define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)
1516 
1517 #define A_DIP4_ERROR_COUNT 0x8c4
1518 
1519 #define S_DIP4ERRORCNT    0
1520 #define M_DIP4ERRORCNT    0xfff
1521 #define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)
1522 #define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)
1523 
1524 #define S_DIP4ERRORCNTSHADOW    12
1525 #define M_DIP4ERRORCNTSHADOW    0xfff
1526 #define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)
1527 #define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)
1528 
1529 #define S_TRICN_RX_TRAIN_ERR    24
1530 #define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)
1531 #define F_TRICN_RX_TRAIN_ERR    V_TRICN_RX_TRAIN_ERR(1U)
1532 
1533 #define S_TRICN_RX_TRAINING    25
1534 #define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)
1535 #define F_TRICN_RX_TRAINING    V_TRICN_RX_TRAINING(1U)
1536 
1537 #define S_TRICN_RX_TRAIN_OK    26
1538 #define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)
1539 #define F_TRICN_RX_TRAIN_OK    V_TRICN_RX_TRAIN_OK(1U)
1540 
1541 #define A_ESPI_INTR_STATUS 0x8c8
1542 
1543 #define S_DIP2PARITYERR    5
1544 #define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
1545 #define F_DIP2PARITYERR    V_DIP2PARITYERR(1U)
1546 
1547 #define A_ESPI_INTR_ENABLE 0x8cc
1548 #define A_RX_DROP_THRESHOLD 0x8d0
1549 #define A_ESPI_RX_RESET 0x8ec
1550 
1551 #define S_ESPI_RX_LNK_RST    0
1552 #define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)
1553 #define F_ESPI_RX_LNK_RST    V_ESPI_RX_LNK_RST(1U)
1554 
1555 #define S_ESPI_RX_CORE_RST    1
1556 #define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)
1557 #define F_ESPI_RX_CORE_RST    V_ESPI_RX_CORE_RST(1U)
1558 
1559 #define S_RX_CLK_STATUS	   2
1560 #define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)
1561 #define F_RX_CLK_STATUS	   V_RX_CLK_STATUS(1U)
1562 
1563 #define A_ESPI_MISC_CONTROL 0x8f0
1564 
1565 #define S_OUT_OF_SYNC_COUNT    0
1566 #define M_OUT_OF_SYNC_COUNT    0xf
1567 #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
1568 #define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)
1569 
1570 #define S_DIP2_COUNT_MODE_ENABLE    4
1571 #define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)
1572 #define F_DIP2_COUNT_MODE_ENABLE    V_DIP2_COUNT_MODE_ENABLE(1U)
1573 
1574 #define S_DIP2_PARITY_ERR_THRES    5
1575 #define M_DIP2_PARITY_ERR_THRES    0xf
1576 #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
1577 #define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)
1578 
1579 #define S_DIP4_THRES    9
1580 #define M_DIP4_THRES    0xfff
1581 #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
1582 #define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)
1583 
1584 #define S_DIP4_THRES_ENABLE    21
1585 #define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)
1586 #define F_DIP4_THRES_ENABLE    V_DIP4_THRES_ENABLE(1U)
1587 
1588 #define S_FORCE_DISABLE_STATUS    22
1589 #define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)
1590 #define F_FORCE_DISABLE_STATUS    V_FORCE_DISABLE_STATUS(1U)
1591 
1592 #define S_DYNAMIC_DESKEW    23
1593 #define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)
1594 #define F_DYNAMIC_DESKEW    V_DYNAMIC_DESKEW(1U)
1595 
1596 #define S_MONITORED_PORT_NUM    25
1597 #define M_MONITORED_PORT_NUM    0x3
1598 #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
1599 #define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)
1600 
1601 #define S_MONITORED_DIRECTION    27
1602 #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
1603 #define F_MONITORED_DIRECTION    V_MONITORED_DIRECTION(1U)
1604 
1605 #define S_MONITORED_INTERFACE    28
1606 #define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
1607 #define F_MONITORED_INTERFACE    V_MONITORED_INTERFACE(1U)
1608 
1609 #define A_ESPI_DIP2_ERR_COUNT 0x8f4
1610 
1611 #define S_DIP2_ERR_CNT    0
1612 #define M_DIP2_ERR_CNT    0xf
1613 #define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)
1614 #define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)
1615 
1616 #define A_ESPI_CMD_ADDR 0x8f8
1617 
1618 #define S_WRITE_DATA    0
1619 #define M_WRITE_DATA    0xff
1620 #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
1621 #define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)
1622 
1623 #define S_REGISTER_OFFSET    8
1624 #define M_REGISTER_OFFSET    0xf
1625 #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
1626 #define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)
1627 
1628 #define S_CHANNEL_ADDR    12
1629 #define M_CHANNEL_ADDR    0xf
1630 #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
1631 #define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)
1632 
1633 #define S_MODULE_ADDR    16
1634 #define M_MODULE_ADDR    0x3
1635 #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
1636 #define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)
1637 
1638 #define S_BUNDLE_ADDR    20
1639 #define M_BUNDLE_ADDR    0x3
1640 #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
1641 #define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)
1642 
1643 #define S_SPI4_COMMAND    24
1644 #define M_SPI4_COMMAND    0xff
1645 #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
1646 #define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)
1647 
1648 #define A_ESPI_GOSTAT 0x8fc
1649 
1650 #define S_READ_DATA    0
1651 #define M_READ_DATA    0xff
1652 #define V_READ_DATA(x) ((x) << S_READ_DATA)
1653 #define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)
1654 
1655 #define S_ESPI_CMD_BUSY    8
1656 #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
1657 #define F_ESPI_CMD_BUSY    V_ESPI_CMD_BUSY(1U)
1658 
1659 #define S_ERROR_ACK    9
1660 #define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)
1661 #define F_ERROR_ACK    V_ERROR_ACK(1U)
1662 
1663 #define S_UNMAPPED_ERR    10
1664 #define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)
1665 #define F_UNMAPPED_ERR    V_UNMAPPED_ERR(1U)
1666 
1667 #define S_TRANSACTION_TIMER    16
1668 #define M_TRANSACTION_TIMER    0xff
1669 #define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)
1670 #define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)
1671 
1672 
1673 /* ULP registers */
1674 #define A_ULP_ULIMIT 0x980
1675 #define A_ULP_TAGMASK 0x984
1676 #define A_ULP_HREG_INDEX 0x988
1677 #define A_ULP_HREG_DATA 0x98c
1678 #define A_ULP_INT_ENABLE 0x990
1679 #define A_ULP_INT_CAUSE 0x994
1680 
1681 #define S_HREG_PAR_ERR    0
1682 #define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)
1683 #define F_HREG_PAR_ERR    V_HREG_PAR_ERR(1U)
1684 
1685 #define S_EGRS_DATA_PAR_ERR    1
1686 #define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)
1687 #define F_EGRS_DATA_PAR_ERR    V_EGRS_DATA_PAR_ERR(1U)
1688 
1689 #define S_INGRS_DATA_PAR_ERR    2
1690 #define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)
1691 #define F_INGRS_DATA_PAR_ERR    V_INGRS_DATA_PAR_ERR(1U)
1692 
1693 #define S_PM_INTR    3
1694 #define V_PM_INTR(x) ((x) << S_PM_INTR)
1695 #define F_PM_INTR    V_PM_INTR(1U)
1696 
1697 #define S_PM_E2C_SYNC_ERR    4
1698 #define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)
1699 #define F_PM_E2C_SYNC_ERR    V_PM_E2C_SYNC_ERR(1U)
1700 
1701 #define S_PM_C2E_SYNC_ERR    5
1702 #define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)
1703 #define F_PM_C2E_SYNC_ERR    V_PM_C2E_SYNC_ERR(1U)
1704 
1705 #define S_PM_E2C_EMPTY_ERR    6
1706 #define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)
1707 #define F_PM_E2C_EMPTY_ERR    V_PM_E2C_EMPTY_ERR(1U)
1708 
1709 #define S_PM_C2E_EMPTY_ERR    7
1710 #define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)
1711 #define F_PM_C2E_EMPTY_ERR    V_PM_C2E_EMPTY_ERR(1U)
1712 
1713 #define S_PM_PAR_ERR    8
1714 #define M_PM_PAR_ERR    0xffff
1715 #define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)
1716 #define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)
1717 
1718 #define S_PM_E2C_WRT_FULL    24
1719 #define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)
1720 #define F_PM_E2C_WRT_FULL    V_PM_E2C_WRT_FULL(1U)
1721 
1722 #define S_PM_C2E_WRT_FULL    25
1723 #define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)
1724 #define F_PM_C2E_WRT_FULL    V_PM_C2E_WRT_FULL(1U)
1725 
1726 #define A_ULP_PIO_CTRL 0x998
1727 
1728 /* PL registers */
1729 #define A_PL_ENABLE 0xa00
1730 
1731 #define S_PL_INTR_SGE_ERR    0
1732 #define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
1733 #define F_PL_INTR_SGE_ERR    V_PL_INTR_SGE_ERR(1U)
1734 
1735 #define S_PL_INTR_SGE_DATA    1
1736 #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
1737 #define F_PL_INTR_SGE_DATA    V_PL_INTR_SGE_DATA(1U)
1738 
1739 #define S_PL_INTR_MC3    2
1740 #define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)
1741 #define F_PL_INTR_MC3    V_PL_INTR_MC3(1U)
1742 
1743 #define S_PL_INTR_MC4    3
1744 #define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)
1745 #define F_PL_INTR_MC4    V_PL_INTR_MC4(1U)
1746 
1747 #define S_PL_INTR_MC5    4
1748 #define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)
1749 #define F_PL_INTR_MC5    V_PL_INTR_MC5(1U)
1750 
1751 #define S_PL_INTR_RAT    5
1752 #define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)
1753 #define F_PL_INTR_RAT    V_PL_INTR_RAT(1U)
1754 
1755 #define S_PL_INTR_TP    6
1756 #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
1757 #define F_PL_INTR_TP    V_PL_INTR_TP(1U)
1758 
1759 #define S_PL_INTR_ULP    7
1760 #define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)
1761 #define F_PL_INTR_ULP    V_PL_INTR_ULP(1U)
1762 
1763 #define S_PL_INTR_ESPI    8
1764 #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
1765 #define F_PL_INTR_ESPI    V_PL_INTR_ESPI(1U)
1766 
1767 #define S_PL_INTR_CSPI    9
1768 #define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)
1769 #define F_PL_INTR_CSPI    V_PL_INTR_CSPI(1U)
1770 
1771 #define S_PL_INTR_PCIX    10
1772 #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
1773 #define F_PL_INTR_PCIX    V_PL_INTR_PCIX(1U)
1774 
1775 #define S_PL_INTR_EXT    11
1776 #define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
1777 #define F_PL_INTR_EXT    V_PL_INTR_EXT(1U)
1778 
1779 #define A_PL_CAUSE 0xa04
1780 
1781 /* MC5 registers */
1782 #define A_MC5_CONFIG 0xc04
1783 
1784 #define S_MODE    0
1785 #define V_MODE(x) ((x) << S_MODE)
1786 #define F_MODE    V_MODE(1U)
1787 
1788 #define S_TCAM_RESET    1
1789 #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
1790 #define F_TCAM_RESET    V_TCAM_RESET(1U)
1791 
1792 #define S_TCAM_READY    2
1793 #define V_TCAM_READY(x) ((x) << S_TCAM_READY)
1794 #define F_TCAM_READY    V_TCAM_READY(1U)
1795 
1796 #define S_DBGI_ENABLE    4
1797 #define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)
1798 #define F_DBGI_ENABLE    V_DBGI_ENABLE(1U)
1799 
1800 #define S_M_BUS_ENABLE    5
1801 #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
1802 #define F_M_BUS_ENABLE    V_M_BUS_ENABLE(1U)
1803 
1804 #define S_PARITY_ENABLE    6
1805 #define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)
1806 #define F_PARITY_ENABLE    V_PARITY_ENABLE(1U)
1807 
1808 #define S_SYN_ISSUE_MODE    7
1809 #define M_SYN_ISSUE_MODE    0x3
1810 #define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)
1811 #define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)
1812 
1813 #define S_BUILD    16
1814 #define V_BUILD(x) ((x) << S_BUILD)
1815 #define F_BUILD    V_BUILD(1U)
1816 
1817 #define S_COMPRESSION_ENABLE    17
1818 #define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)
1819 #define F_COMPRESSION_ENABLE    V_COMPRESSION_ENABLE(1U)
1820 
1821 #define S_NUM_LIP    18
1822 #define M_NUM_LIP    0x3f
1823 #define V_NUM_LIP(x) ((x) << S_NUM_LIP)
1824 #define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)
1825 
1826 #define S_TCAM_PART_CNT    24
1827 #define M_TCAM_PART_CNT    0x3
1828 #define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)
1829 #define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)
1830 
1831 #define S_TCAM_PART_TYPE    26
1832 #define M_TCAM_PART_TYPE    0x3
1833 #define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)
1834 #define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)
1835 
1836 #define S_TCAM_PART_SIZE    28
1837 #define M_TCAM_PART_SIZE    0x3
1838 #define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)
1839 #define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)
1840 
1841 #define S_TCAM_PART_TYPE_HI    30
1842 #define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)
1843 #define F_TCAM_PART_TYPE_HI    V_TCAM_PART_TYPE_HI(1U)
1844 
1845 #define A_MC5_SIZE 0xc08
1846 
1847 #define S_SIZE    0
1848 #define M_SIZE    0x3fffff
1849 #define V_SIZE(x) ((x) << S_SIZE)
1850 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1851 
1852 #define A_MC5_ROUTING_TABLE_INDEX 0xc0c
1853 
1854 #define S_START_OF_ROUTING_TABLE    0
1855 #define M_START_OF_ROUTING_TABLE    0x3fffff
1856 #define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)
1857 #define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)
1858 
1859 #define A_MC5_SERVER_INDEX 0xc14
1860 
1861 #define S_START_OF_SERVER_INDEX    0
1862 #define M_START_OF_SERVER_INDEX    0x3fffff
1863 #define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)
1864 #define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)
1865 
1866 #define A_MC5_LIP_RAM_ADDR 0xc18
1867 
1868 #define S_LOCAL_IP_RAM_ADDR    0
1869 #define M_LOCAL_IP_RAM_ADDR    0x3f
1870 #define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)
1871 #define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)
1872 
1873 #define S_RAM_WRITE_ENABLE    8
1874 #define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)
1875 #define F_RAM_WRITE_ENABLE    V_RAM_WRITE_ENABLE(1U)
1876 
1877 #define A_MC5_LIP_RAM_DATA 0xc1c
1878 #define A_MC5_RSP_LATENCY 0xc20
1879 
1880 #define S_SEARCH_RESPONSE_LATENCY    0
1881 #define M_SEARCH_RESPONSE_LATENCY    0x1f
1882 #define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)
1883 #define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
1884 
1885 #define S_LEARN_RESPONSE_LATENCY    8
1886 #define M_LEARN_RESPONSE_LATENCY    0x1f
1887 #define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)
1888 #define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)
1889 
1890 #define A_MC5_PARITY_LATENCY 0xc24
1891 
1892 #define S_SRCHLAT    0
1893 #define M_SRCHLAT    0x1f
1894 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1895 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
1896 
1897 #define S_PARLAT    8
1898 #define M_PARLAT    0x1f
1899 #define V_PARLAT(x) ((x) << S_PARLAT)
1900 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
1901 
1902 #define A_MC5_WR_LRN_VERIFY 0xc28
1903 
1904 #define S_POVEREN    0
1905 #define V_POVEREN(x) ((x) << S_POVEREN)
1906 #define F_POVEREN    V_POVEREN(1U)
1907 
1908 #define S_LRNVEREN    1
1909 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
1910 #define F_LRNVEREN    V_LRNVEREN(1U)
1911 
1912 #define S_VWVEREN    2
1913 #define V_VWVEREN(x) ((x) << S_VWVEREN)
1914 #define F_VWVEREN    V_VWVEREN(1U)
1915 
1916 #define A_MC5_PART_ID_INDEX 0xc2c
1917 
1918 #define S_IDINDEX    0
1919 #define M_IDINDEX    0xf
1920 #define V_IDINDEX(x) ((x) << S_IDINDEX)
1921 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
1922 
1923 #define A_MC5_RESET_MAX 0xc30
1924 
1925 #define S_RSTMAX    0
1926 #define M_RSTMAX    0x1ff
1927 #define V_RSTMAX(x) ((x) << S_RSTMAX)
1928 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
1929 
1930 #define A_MC5_INT_ENABLE 0xc40
1931 
1932 #define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR    0
1933 #define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)
1934 #define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR    V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)
1935 
1936 #define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR    1
1937 #define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)
1938 #define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR    V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)
1939 
1940 #define S_MC5_INT_HIT_IN_RT_REGION_ERR    2
1941 #define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)
1942 #define F_MC5_INT_HIT_IN_RT_REGION_ERR    V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)
1943 
1944 #define S_MC5_INT_MISS_ERR    3
1945 #define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)
1946 #define F_MC5_INT_MISS_ERR    V_MC5_INT_MISS_ERR(1U)
1947 
1948 #define S_MC5_INT_LIP0_ERR    4
1949 #define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)
1950 #define F_MC5_INT_LIP0_ERR    V_MC5_INT_LIP0_ERR(1U)
1951 
1952 #define S_MC5_INT_LIP_MISS_ERR    5
1953 #define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)
1954 #define F_MC5_INT_LIP_MISS_ERR    V_MC5_INT_LIP_MISS_ERR(1U)
1955 
1956 #define S_MC5_INT_PARITY_ERR    6
1957 #define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)
1958 #define F_MC5_INT_PARITY_ERR    V_MC5_INT_PARITY_ERR(1U)
1959 
1960 #define S_MC5_INT_ACTIVE_REGION_FULL    7
1961 #define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)
1962 #define F_MC5_INT_ACTIVE_REGION_FULL    V_MC5_INT_ACTIVE_REGION_FULL(1U)
1963 
1964 #define S_MC5_INT_NFA_SRCH_ERR    8
1965 #define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)
1966 #define F_MC5_INT_NFA_SRCH_ERR    V_MC5_INT_NFA_SRCH_ERR(1U)
1967 
1968 #define S_MC5_INT_SYN_COOKIE    9
1969 #define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)
1970 #define F_MC5_INT_SYN_COOKIE    V_MC5_INT_SYN_COOKIE(1U)
1971 
1972 #define S_MC5_INT_SYN_COOKIE_BAD    10
1973 #define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)
1974 #define F_MC5_INT_SYN_COOKIE_BAD    V_MC5_INT_SYN_COOKIE_BAD(1U)
1975 
1976 #define S_MC5_INT_SYN_COOKIE_OFF    11
1977 #define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)
1978 #define F_MC5_INT_SYN_COOKIE_OFF    V_MC5_INT_SYN_COOKIE_OFF(1U)
1979 
1980 #define S_MC5_INT_UNKNOWN_CMD    15
1981 #define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)
1982 #define F_MC5_INT_UNKNOWN_CMD    V_MC5_INT_UNKNOWN_CMD(1U)
1983 
1984 #define S_MC5_INT_REQUESTQ_PARITY_ERR    16
1985 #define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)
1986 #define F_MC5_INT_REQUESTQ_PARITY_ERR    V_MC5_INT_REQUESTQ_PARITY_ERR(1U)
1987 
1988 #define S_MC5_INT_DISPATCHQ_PARITY_ERR    17
1989 #define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)
1990 #define F_MC5_INT_DISPATCHQ_PARITY_ERR    V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)
1991 
1992 #define S_MC5_INT_DEL_ACT_EMPTY    18
1993 #define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)
1994 #define F_MC5_INT_DEL_ACT_EMPTY    V_MC5_INT_DEL_ACT_EMPTY(1U)
1995 
1996 #define A_MC5_INT_CAUSE 0xc44
1997 #define A_MC5_INT_TID 0xc48
1998 #define A_MC5_INT_PTID 0xc4c
1999 #define A_MC5_DBGI_CONFIG 0xc74
2000 #define A_MC5_DBGI_REQ_CMD 0xc78
2001 
2002 #define S_CMDMODE    0
2003 #define M_CMDMODE    0x7
2004 #define V_CMDMODE(x) ((x) << S_CMDMODE)
2005 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
2006 
2007 #define S_SADRSEL    4
2008 #define V_SADRSEL(x) ((x) << S_SADRSEL)
2009 #define F_SADRSEL    V_SADRSEL(1U)
2010 
2011 #define S_WRITE_BURST_SIZE    22
2012 #define M_WRITE_BURST_SIZE    0x3ff
2013 #define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)
2014 #define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)
2015 
2016 #define A_MC5_DBGI_REQ_ADDR0 0xc7c
2017 #define A_MC5_DBGI_REQ_ADDR1 0xc80
2018 #define A_MC5_DBGI_REQ_ADDR2 0xc84
2019 #define A_MC5_DBGI_REQ_DATA0 0xc88
2020 #define A_MC5_DBGI_REQ_DATA1 0xc8c
2021 #define A_MC5_DBGI_REQ_DATA2 0xc90
2022 #define A_MC5_DBGI_REQ_DATA3 0xc94
2023 #define A_MC5_DBGI_REQ_DATA4 0xc98
2024 #define A_MC5_DBGI_REQ_MASK0 0xc9c
2025 #define A_MC5_DBGI_REQ_MASK1 0xca0
2026 #define A_MC5_DBGI_REQ_MASK2 0xca4
2027 #define A_MC5_DBGI_REQ_MASK3 0xca8
2028 #define A_MC5_DBGI_REQ_MASK4 0xcac
2029 #define A_MC5_DBGI_RSP_STATUS 0xcb0
2030 
2031 #define S_DBGI_RSP_VALID    0
2032 #define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)
2033 #define F_DBGI_RSP_VALID    V_DBGI_RSP_VALID(1U)
2034 
2035 #define S_DBGI_RSP_HIT    1
2036 #define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)
2037 #define F_DBGI_RSP_HIT    V_DBGI_RSP_HIT(1U)
2038 
2039 #define S_DBGI_RSP_ERR    2
2040 #define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)
2041 #define F_DBGI_RSP_ERR    V_DBGI_RSP_ERR(1U)
2042 
2043 #define S_DBGI_RSP_ERR_REASON    8
2044 #define M_DBGI_RSP_ERR_REASON    0x7
2045 #define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)
2046 #define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)
2047 
2048 #define A_MC5_DBGI_RSP_DATA0 0xcb4
2049 #define A_MC5_DBGI_RSP_DATA1 0xcb8
2050 #define A_MC5_DBGI_RSP_DATA2 0xcbc
2051 #define A_MC5_DBGI_RSP_DATA3 0xcc0
2052 #define A_MC5_DBGI_RSP_DATA4 0xcc4
2053 #define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2054 #define A_MC5_POPEN_DATA_WR_CMD 0xccc
2055 #define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2056 #define A_MC5_AOPEN_SRCH_CMD 0xcd4
2057 #define A_MC5_AOPEN_LRN_CMD 0xcd8
2058 #define A_MC5_SYN_SRCH_CMD 0xcdc
2059 #define A_MC5_SYN_LRN_CMD 0xce0
2060 #define A_MC5_ACK_SRCH_CMD 0xce4
2061 #define A_MC5_ACK_LRN_CMD 0xce8
2062 #define A_MC5_ILOOKUP_CMD 0xcec
2063 #define A_MC5_ELOOKUP_CMD 0xcf0
2064 #define A_MC5_DATA_WRITE_CMD 0xcf4
2065 #define A_MC5_DATA_READ_CMD 0xcf8
2066 #define A_MC5_MASK_WRITE_CMD 0xcfc
2067 
2068 /* PCICFG registers */
2069 #define A_PCICFG_PM_CSR 0x44
2070 #define A_PCICFG_VPD_ADDR 0x4a
2071 
2072 #define S_VPD_ADDR    0
2073 #define M_VPD_ADDR    0x7fff
2074 #define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)
2075 #define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)
2076 
2077 #define S_VPD_OP_FLAG    15
2078 #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
2079 #define F_VPD_OP_FLAG    V_VPD_OP_FLAG(1U)
2080 
2081 #define A_PCICFG_VPD_DATA 0x4c
2082 #define A_PCICFG_PCIX_CMD 0x60
2083 #define A_PCICFG_INTR_ENABLE 0xf4
2084 
2085 #define S_MASTER_PARITY_ERR    0
2086 #define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)
2087 #define F_MASTER_PARITY_ERR    V_MASTER_PARITY_ERR(1U)
2088 
2089 #define S_SIG_TARGET_ABORT    1
2090 #define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)
2091 #define F_SIG_TARGET_ABORT    V_SIG_TARGET_ABORT(1U)
2092 
2093 #define S_RCV_TARGET_ABORT    2
2094 #define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)
2095 #define F_RCV_TARGET_ABORT    V_RCV_TARGET_ABORT(1U)
2096 
2097 #define S_RCV_MASTER_ABORT    3
2098 #define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)
2099 #define F_RCV_MASTER_ABORT    V_RCV_MASTER_ABORT(1U)
2100 
2101 #define S_SIG_SYS_ERR    4
2102 #define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)
2103 #define F_SIG_SYS_ERR    V_SIG_SYS_ERR(1U)
2104 
2105 #define S_DET_PARITY_ERR    5
2106 #define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)
2107 #define F_DET_PARITY_ERR    V_DET_PARITY_ERR(1U)
2108 
2109 #define S_PIO_PARITY_ERR    6
2110 #define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)
2111 #define F_PIO_PARITY_ERR    V_PIO_PARITY_ERR(1U)
2112 
2113 #define S_WF_PARITY_ERR    7
2114 #define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)
2115 #define F_WF_PARITY_ERR    V_WF_PARITY_ERR(1U)
2116 
2117 #define S_RF_PARITY_ERR    8
2118 #define M_RF_PARITY_ERR    0x3
2119 #define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)
2120 #define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)
2121 
2122 #define S_CF_PARITY_ERR    10
2123 #define M_CF_PARITY_ERR    0x3
2124 #define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)
2125 #define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)
2126 
2127 #define A_PCICFG_INTR_CAUSE 0xf8
2128 #define A_PCICFG_MODE 0xfc
2129 
2130 #define S_PCI_MODE_64BIT    0
2131 #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
2132 #define F_PCI_MODE_64BIT    V_PCI_MODE_64BIT(1U)
2133 
2134 #define S_PCI_MODE_66MHZ    1
2135 #define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)
2136 #define F_PCI_MODE_66MHZ    V_PCI_MODE_66MHZ(1U)
2137 
2138 #define S_PCI_MODE_PCIX_INITPAT    2
2139 #define M_PCI_MODE_PCIX_INITPAT    0x7
2140 #define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)
2141 #define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)
2142 
2143 #define S_PCI_MODE_PCIX    5
2144 #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
2145 #define F_PCI_MODE_PCIX    V_PCI_MODE_PCIX(1U)
2146 
2147 #define S_PCI_MODE_CLK    6
2148 #define M_PCI_MODE_CLK    0x3
2149 #define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)
2150 #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
2151 
2152