xref: /illumos-gate/usr/src/uts/common/io/chxge/com/elmer0.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24  */
25 
26 #ifndef CHELSIO_ELMER0_H
27 #define CHELSIO_ELMER0_H
28 
29 /* ELMER0 flavors */
30 enum {
31 	ELMER0_XC2S300E_6FT256_C,
32 	ELMER0_XC2S100E_6TQ144_C
33 };
34 
35 /* ELMER0 registers */
36 #define A_ELMER0_VERSION 0x100000
37 #define A_ELMER0_PHY_CFG 0x100004
38 #define A_ELMER0_INT_ENABLE 0x100008
39 #define A_ELMER0_INT_CAUSE 0x10000c
40 #define A_ELMER0_GPI_CFG 0x100010
41 #define A_ELMER0_GPI_STAT 0x100014
42 #define A_ELMER0_GPO 0x100018
43 #define A_ELMER0_PORT0_MI1_CFG 0x400000
44 
45 #define S_MI1_MDI_ENABLE    0
46 #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
47 #define F_MI1_MDI_ENABLE    V_MI1_MDI_ENABLE(1U)
48 
49 #define S_MI1_MDI_INVERT    1
50 #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
51 #define F_MI1_MDI_INVERT    V_MI1_MDI_INVERT(1U)
52 
53 #define S_MI1_PREAMBLE_ENABLE    2
54 #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
55 #define F_MI1_PREAMBLE_ENABLE    V_MI1_PREAMBLE_ENABLE(1U)
56 
57 #define S_MI1_SOF    3
58 #define M_MI1_SOF    0x3
59 #define V_MI1_SOF(x) ((x) << S_MI1_SOF)
60 #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
61 
62 #define S_MI1_CLK_DIV    5
63 #define M_MI1_CLK_DIV    0xff
64 #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
65 #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
66 
67 #define A_ELMER0_PORT0_MI1_ADDR 0x400004
68 
69 #define S_MI1_REG_ADDR    0
70 #define M_MI1_REG_ADDR    0x1f
71 #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
72 #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
73 
74 #define S_MI1_PHY_ADDR    5
75 #define M_MI1_PHY_ADDR    0x1f
76 #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
77 #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
78 
79 #define A_ELMER0_PORT0_MI1_DATA 0x400008
80 
81 #define S_MI1_DATA    0
82 #define M_MI1_DATA    0xffff
83 #define V_MI1_DATA(x) ((x) << S_MI1_DATA)
84 #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
85 
86 #define A_ELMER0_PORT0_MI1_OP 0x40000c
87 
88 #define S_MI1_OP    0
89 #define M_MI1_OP    0x3
90 #define V_MI1_OP(x) ((x) << S_MI1_OP)
91 #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
92 
93 #define S_MI1_ADDR_AUTOINC    2
94 #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
95 #define F_MI1_ADDR_AUTOINC    V_MI1_ADDR_AUTOINC(1U)
96 
97 #define S_MI1_OP_BUSY    31
98 #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
99 #define F_MI1_OP_BUSY    V_MI1_OP_BUSY(1U)
100 
101 #define A_ELMER0_PORT1_MI1_CFG 0x500000
102 #define A_ELMER0_PORT1_MI1_ADDR 0x500004
103 #define A_ELMER0_PORT1_MI1_DATA 0x500008
104 #define A_ELMER0_PORT1_MI1_OP 0x50000c
105 #define A_ELMER0_PORT2_MI1_CFG 0x600000
106 #define A_ELMER0_PORT2_MI1_ADDR 0x600004
107 #define A_ELMER0_PORT2_MI1_DATA 0x600008
108 #define A_ELMER0_PORT2_MI1_OP 0x60000c
109 #define A_ELMER0_PORT3_MI1_CFG 0x700000
110 #define A_ELMER0_PORT3_MI1_ADDR 0x700004
111 #define A_ELMER0_PORT3_MI1_DATA 0x700008
112 #define A_ELMER0_PORT3_MI1_OP 0x70000c
113 
114 /* Simple bit definition for GPI and GP0 registers. */
115 #define     ELMER0_GP_BIT0              0x0001
116 #define     ELMER0_GP_BIT1              0x0002
117 #define     ELMER0_GP_BIT2              0x0004
118 #define     ELMER0_GP_BIT3              0x0008
119 #define     ELMER0_GP_BIT4              0x0010
120 #define     ELMER0_GP_BIT5              0x0020
121 #define     ELMER0_GP_BIT6              0x0040
122 #define     ELMER0_GP_BIT7              0x0080
123 #define     ELMER0_GP_BIT8              0x0100
124 #define     ELMER0_GP_BIT9              0x0200
125 #define     ELMER0_GP_BIT10             0x0400
126 #define     ELMER0_GP_BIT11             0x0800
127 #define     ELMER0_GP_BIT12             0x1000
128 #define     ELMER0_GP_BIT13             0x2000
129 #define     ELMER0_GP_BIT14             0x4000
130 #define     ELMER0_GP_BIT15             0x8000
131 #define     ELMER0_GP_BIT16             0x10000
132 #define     ELMER0_GP_BIT17             0x20000
133 #define     ELMER0_GP_BIT18             0x40000
134 #define     ELMER0_GP_BIT19             0x80000
135 
136 #define MI1_OP_DIRECT_WRITE 1
137 #define MI1_OP_DIRECT_READ  2
138 
139 #define MI1_OP_INDIRECT_ADDRESS  0
140 #define MI1_OP_INDIRECT_WRITE    1
141 #define MI1_OP_INDIRECT_READ_INC 2
142 #define MI1_OP_INDIRECT_READ     3
143 
144 #endif
145