1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Perf support for the Statistical Profiling Extension, introduced as
4 * part of ARMv8.2.
5 *
6 * Copyright (C) 2016 ARM Limited
7 *
8 * Author: Will Deacon <will.deacon@arm.com>
9 */
10
11 #define PMUNAME "arm_spe"
12 #define DRVNAME PMUNAME "_pmu"
13 #define pr_fmt(fmt) DRVNAME ": " fmt
14
15 #include <linux/bitfield.h>
16 #include <linux/bitops.h>
17 #include <linux/bug.h>
18 #include <linux/capability.h>
19 #include <linux/cpuhotplug.h>
20 #include <linux/cpumask.h>
21 #include <linux/device.h>
22 #include <linux/errno.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/perf_event.h>
30 #include <linux/perf/arm_pmu.h>
31 #include <linux/platform_device.h>
32 #include <linux/printk.h>
33 #include <linux/slab.h>
34 #include <linux/smp.h>
35 #include <linux/vmalloc.h>
36
37 #include <asm/barrier.h>
38 #include <asm/cpufeature.h>
39 #include <asm/mmu.h>
40 #include <asm/sysreg.h>
41
42 /*
43 * Cache if the event is allowed to trace Context information.
44 * This allows us to perform the check, i.e, perf_allow_kernel(),
45 * in the context of the event owner, once, during the event_init().
46 */
47 #define SPE_PMU_HW_FLAGS_CX 0x00001
48
49 static_assert((PERF_EVENT_FLAG_ARCH & SPE_PMU_HW_FLAGS_CX) == SPE_PMU_HW_FLAGS_CX);
50
set_spe_event_has_cx(struct perf_event * event)51 static void set_spe_event_has_cx(struct perf_event *event)
52 {
53 if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && !perf_allow_kernel())
54 event->hw.flags |= SPE_PMU_HW_FLAGS_CX;
55 }
56
get_spe_event_has_cx(struct perf_event * event)57 static bool get_spe_event_has_cx(struct perf_event *event)
58 {
59 return !!(event->hw.flags & SPE_PMU_HW_FLAGS_CX);
60 }
61
62 #define ARM_SPE_BUF_PAD_BYTE 0
63
64 struct arm_spe_pmu_buf {
65 int nr_pages;
66 bool snapshot;
67 void *base;
68 };
69
70 struct arm_spe_pmu {
71 struct pmu pmu;
72 struct platform_device *pdev;
73 cpumask_t supported_cpus;
74 struct hlist_node hotplug_node;
75
76 int irq; /* PPI */
77 u16 pmsver;
78 u16 min_period;
79 u16 counter_sz;
80
81 #define SPE_PMU_FEAT_FILT_EVT (1UL << 0)
82 #define SPE_PMU_FEAT_FILT_TYP (1UL << 1)
83 #define SPE_PMU_FEAT_FILT_LAT (1UL << 2)
84 #define SPE_PMU_FEAT_ARCH_INST (1UL << 3)
85 #define SPE_PMU_FEAT_LDS (1UL << 4)
86 #define SPE_PMU_FEAT_ERND (1UL << 5)
87 #define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6)
88 #define SPE_PMU_FEAT_DISCARD (1UL << 7)
89 #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63)
90 u64 features;
91
92 u16 max_record_sz;
93 u16 align;
94 struct perf_output_handle __percpu *handle;
95 };
96
97 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
98
99 /* Convert a free-running index from perf into an SPE buffer offset */
100 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
101
102 /* Keep track of our dynamic hotplug state */
103 static enum cpuhp_state arm_spe_pmu_online;
104
105 enum arm_spe_pmu_buf_fault_action {
106 SPE_PMU_BUF_FAULT_ACT_SPURIOUS,
107 SPE_PMU_BUF_FAULT_ACT_FATAL,
108 SPE_PMU_BUF_FAULT_ACT_OK,
109 };
110
111 /* This sysfs gunk was really good fun to write. */
112 enum arm_spe_pmu_capabilities {
113 SPE_PMU_CAP_ARCH_INST = 0,
114 SPE_PMU_CAP_ERND,
115 SPE_PMU_CAP_FEAT_MAX,
116 SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX,
117 SPE_PMU_CAP_MIN_IVAL,
118 };
119
120 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = {
121 [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST,
122 [SPE_PMU_CAP_ERND] = SPE_PMU_FEAT_ERND,
123 };
124
arm_spe_pmu_cap_get(struct arm_spe_pmu * spe_pmu,int cap)125 static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap)
126 {
127 if (cap < SPE_PMU_CAP_FEAT_MAX)
128 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]);
129
130 switch (cap) {
131 case SPE_PMU_CAP_CNT_SZ:
132 return spe_pmu->counter_sz;
133 case SPE_PMU_CAP_MIN_IVAL:
134 return spe_pmu->min_period;
135 default:
136 WARN(1, "unknown cap %d\n", cap);
137 }
138
139 return 0;
140 }
141
arm_spe_pmu_cap_show(struct device * dev,struct device_attribute * attr,char * buf)142 static ssize_t arm_spe_pmu_cap_show(struct device *dev,
143 struct device_attribute *attr,
144 char *buf)
145 {
146 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
147 struct dev_ext_attribute *ea =
148 container_of(attr, struct dev_ext_attribute, attr);
149 int cap = (long)ea->var;
150
151 return sysfs_emit(buf, "%u\n", arm_spe_pmu_cap_get(spe_pmu, cap));
152 }
153
154 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var) \
155 &((struct dev_ext_attribute[]) { \
156 { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var } \
157 })[0].attr.attr
158
159 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var) \
160 SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var)
161
162 static struct attribute *arm_spe_pmu_cap_attr[] = {
163 SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST),
164 SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND),
165 SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ),
166 SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL),
167 NULL,
168 };
169
170 static const struct attribute_group arm_spe_pmu_cap_group = {
171 .name = "caps",
172 .attrs = arm_spe_pmu_cap_attr,
173 };
174
175 /* User ABI */
176 #define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */
177 #define ATTR_CFG_FLD_ts_enable_LO 0
178 #define ATTR_CFG_FLD_ts_enable_HI 0
179 #define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */
180 #define ATTR_CFG_FLD_pa_enable_LO 1
181 #define ATTR_CFG_FLD_pa_enable_HI 1
182 #define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */
183 #define ATTR_CFG_FLD_pct_enable_LO 2
184 #define ATTR_CFG_FLD_pct_enable_HI 2
185 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */
186 #define ATTR_CFG_FLD_jitter_LO 16
187 #define ATTR_CFG_FLD_jitter_HI 16
188 #define ATTR_CFG_FLD_branch_filter_CFG config /* PMSFCR_EL1.B */
189 #define ATTR_CFG_FLD_branch_filter_LO 32
190 #define ATTR_CFG_FLD_branch_filter_HI 32
191 #define ATTR_CFG_FLD_load_filter_CFG config /* PMSFCR_EL1.LD */
192 #define ATTR_CFG_FLD_load_filter_LO 33
193 #define ATTR_CFG_FLD_load_filter_HI 33
194 #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */
195 #define ATTR_CFG_FLD_store_filter_LO 34
196 #define ATTR_CFG_FLD_store_filter_HI 34
197 #define ATTR_CFG_FLD_discard_CFG config /* PMBLIMITR_EL1.FM = DISCARD */
198 #define ATTR_CFG_FLD_discard_LO 35
199 #define ATTR_CFG_FLD_discard_HI 35
200
201 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */
202 #define ATTR_CFG_FLD_event_filter_LO 0
203 #define ATTR_CFG_FLD_event_filter_HI 63
204
205 #define ATTR_CFG_FLD_min_latency_CFG config2 /* PMSLATFR_EL1.MINLAT */
206 #define ATTR_CFG_FLD_min_latency_LO 0
207 #define ATTR_CFG_FLD_min_latency_HI 11
208
209 #define ATTR_CFG_FLD_inv_event_filter_CFG config3 /* PMSNEVFR_EL1 */
210 #define ATTR_CFG_FLD_inv_event_filter_LO 0
211 #define ATTR_CFG_FLD_inv_event_filter_HI 63
212
213 GEN_PMU_FORMAT_ATTR(ts_enable);
214 GEN_PMU_FORMAT_ATTR(pa_enable);
215 GEN_PMU_FORMAT_ATTR(pct_enable);
216 GEN_PMU_FORMAT_ATTR(jitter);
217 GEN_PMU_FORMAT_ATTR(branch_filter);
218 GEN_PMU_FORMAT_ATTR(load_filter);
219 GEN_PMU_FORMAT_ATTR(store_filter);
220 GEN_PMU_FORMAT_ATTR(event_filter);
221 GEN_PMU_FORMAT_ATTR(inv_event_filter);
222 GEN_PMU_FORMAT_ATTR(min_latency);
223 GEN_PMU_FORMAT_ATTR(discard);
224
225 static struct attribute *arm_spe_pmu_formats_attr[] = {
226 &format_attr_ts_enable.attr,
227 &format_attr_pa_enable.attr,
228 &format_attr_pct_enable.attr,
229 &format_attr_jitter.attr,
230 &format_attr_branch_filter.attr,
231 &format_attr_load_filter.attr,
232 &format_attr_store_filter.attr,
233 &format_attr_event_filter.attr,
234 &format_attr_inv_event_filter.attr,
235 &format_attr_min_latency.attr,
236 &format_attr_discard.attr,
237 NULL,
238 };
239
arm_spe_pmu_format_attr_is_visible(struct kobject * kobj,struct attribute * attr,int unused)240 static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj,
241 struct attribute *attr,
242 int unused)
243 {
244 struct device *dev = kobj_to_dev(kobj);
245 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
246
247 if (attr == &format_attr_discard.attr && !(spe_pmu->features & SPE_PMU_FEAT_DISCARD))
248 return 0;
249
250 if (attr == &format_attr_inv_event_filter.attr && !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT))
251 return 0;
252
253 return attr->mode;
254 }
255
256 static const struct attribute_group arm_spe_pmu_format_group = {
257 .name = "format",
258 .is_visible = arm_spe_pmu_format_attr_is_visible,
259 .attrs = arm_spe_pmu_formats_attr,
260 };
261
cpumask_show(struct device * dev,struct device_attribute * attr,char * buf)262 static ssize_t cpumask_show(struct device *dev,
263 struct device_attribute *attr, char *buf)
264 {
265 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
266
267 return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus);
268 }
269 static DEVICE_ATTR_RO(cpumask);
270
271 static struct attribute *arm_spe_pmu_attrs[] = {
272 &dev_attr_cpumask.attr,
273 NULL,
274 };
275
276 static const struct attribute_group arm_spe_pmu_group = {
277 .attrs = arm_spe_pmu_attrs,
278 };
279
280 static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
281 &arm_spe_pmu_group,
282 &arm_spe_pmu_cap_group,
283 &arm_spe_pmu_format_group,
284 NULL,
285 };
286
287 /* Convert between user ABI and register values */
arm_spe_event_to_pmscr(struct perf_event * event)288 static u64 arm_spe_event_to_pmscr(struct perf_event *event)
289 {
290 struct perf_event_attr *attr = &event->attr;
291 u64 reg = 0;
292
293 reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable));
294 reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable));
295 reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable));
296
297 if (!attr->exclude_user)
298 reg |= PMSCR_EL1_E0SPE;
299
300 if (!attr->exclude_kernel)
301 reg |= PMSCR_EL1_E1SPE;
302
303 if (get_spe_event_has_cx(event))
304 reg |= PMSCR_EL1_CX;
305
306 return reg;
307 }
308
arm_spe_event_sanitise_period(struct perf_event * event)309 static void arm_spe_event_sanitise_period(struct perf_event *event)
310 {
311 u64 period = event->hw.sample_period;
312 u64 max_period = PMSIRR_EL1_INTERVAL_MASK;
313
314 /*
315 * The PMSIDR_EL1.Interval field (stored in spe_pmu->min_period) is a
316 * recommendation for the minimum interval, not a hardware limitation.
317 *
318 * According to the Arm ARM (DDI 0487 L.a), section D24.7.12 PMSIRR_EL1,
319 * Sampling Interval Reload Register, the INTERVAL field (bits [31:8])
320 * states: "Software must set this to a nonzero value". Use 1 as the
321 * minimum value.
322 */
323 u64 min_period = FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1);
324
325 period = clamp_t(u64, period, min_period, max_period) & max_period;
326 event->hw.sample_period = period;
327 }
328
arm_spe_event_to_pmsirr(struct perf_event * event)329 static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
330 {
331 struct perf_event_attr *attr = &event->attr;
332 u64 reg = 0;
333
334 arm_spe_event_sanitise_period(event);
335
336 reg |= FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter));
337 reg |= event->hw.sample_period;
338
339 return reg;
340 }
341
arm_spe_event_to_pmsfcr(struct perf_event * event)342 static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
343 {
344 struct perf_event_attr *attr = &event->attr;
345 u64 reg = 0;
346
347 reg |= FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter));
348 reg |= FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter));
349 reg |= FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter));
350
351 if (reg)
352 reg |= PMSFCR_EL1_FT;
353
354 if (ATTR_CFG_GET_FLD(attr, event_filter))
355 reg |= PMSFCR_EL1_FE;
356
357 if (ATTR_CFG_GET_FLD(attr, inv_event_filter))
358 reg |= PMSFCR_EL1_FnE;
359
360 if (ATTR_CFG_GET_FLD(attr, min_latency))
361 reg |= PMSFCR_EL1_FL;
362
363 return reg;
364 }
365
arm_spe_event_to_pmsevfr(struct perf_event * event)366 static u64 arm_spe_event_to_pmsevfr(struct perf_event *event)
367 {
368 struct perf_event_attr *attr = &event->attr;
369 return ATTR_CFG_GET_FLD(attr, event_filter);
370 }
371
arm_spe_event_to_pmsnevfr(struct perf_event * event)372 static u64 arm_spe_event_to_pmsnevfr(struct perf_event *event)
373 {
374 struct perf_event_attr *attr = &event->attr;
375 return ATTR_CFG_GET_FLD(attr, inv_event_filter);
376 }
377
arm_spe_event_to_pmslatfr(struct perf_event * event)378 static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
379 {
380 struct perf_event_attr *attr = &event->attr;
381 return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency));
382 }
383
arm_spe_pmu_pad_buf(struct perf_output_handle * handle,int len)384 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
385 {
386 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
387 u64 head = PERF_IDX2OFF(handle->head, buf);
388
389 memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len);
390 if (!buf->snapshot)
391 perf_aux_output_skip(handle, len);
392 }
393
arm_spe_pmu_next_snapshot_off(struct perf_output_handle * handle)394 static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle)
395 {
396 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
397 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
398 u64 head = PERF_IDX2OFF(handle->head, buf);
399 u64 limit = buf->nr_pages * PAGE_SIZE;
400
401 /*
402 * The trace format isn't parseable in reverse, so clamp
403 * the limit to half of the buffer size in snapshot mode
404 * so that the worst case is half a buffer of records, as
405 * opposed to a single record.
406 */
407 if (head < limit >> 1)
408 limit >>= 1;
409
410 /*
411 * If we're within max_record_sz of the limit, we must
412 * pad, move the head index and recompute the limit.
413 */
414 if (limit - head < spe_pmu->max_record_sz) {
415 arm_spe_pmu_pad_buf(handle, limit - head);
416 handle->head = PERF_IDX2OFF(limit, buf);
417 limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head;
418 }
419
420 return limit;
421 }
422
__arm_spe_pmu_next_off(struct perf_output_handle * handle)423 static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle)
424 {
425 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
426 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
427 const u64 bufsize = buf->nr_pages * PAGE_SIZE;
428 u64 limit = bufsize;
429 u64 head, tail, wakeup;
430
431 /*
432 * The head can be misaligned for two reasons:
433 *
434 * 1. The hardware left PMBPTR pointing to the first byte after
435 * a record when generating a buffer management event.
436 *
437 * 2. We used perf_aux_output_skip to consume handle->size bytes
438 * and CIRC_SPACE was used to compute the size, which always
439 * leaves one entry free.
440 *
441 * Deal with this by padding to the next alignment boundary and
442 * moving the head index. If we run out of buffer space, we'll
443 * reduce handle->size to zero and end up reporting truncation.
444 */
445 head = PERF_IDX2OFF(handle->head, buf);
446 if (!IS_ALIGNED(head, spe_pmu->align)) {
447 unsigned long delta = roundup(head, spe_pmu->align) - head;
448
449 delta = min(delta, handle->size);
450 arm_spe_pmu_pad_buf(handle, delta);
451 head = PERF_IDX2OFF(handle->head, buf);
452 }
453
454 /* If we've run out of free space, then nothing more to do */
455 if (!handle->size)
456 goto no_space;
457
458 /* Compute the tail and wakeup indices now that we've aligned head */
459 tail = PERF_IDX2OFF(handle->head + handle->size, buf);
460 wakeup = PERF_IDX2OFF(handle->wakeup, buf);
461
462 /*
463 * Avoid clobbering unconsumed data. We know we have space, so
464 * if we see head == tail we know that the buffer is empty. If
465 * head > tail, then there's nothing to clobber prior to
466 * wrapping.
467 */
468 if (head < tail)
469 limit = round_down(tail, PAGE_SIZE);
470
471 /*
472 * Wakeup may be arbitrarily far into the future. If it's not in
473 * the current generation, either we'll wrap before hitting it,
474 * or it's in the past and has been handled already.
475 *
476 * If there's a wakeup before we wrap, arrange to be woken up by
477 * the page boundary following it. Keep the tail boundary if
478 * that's lower.
479 */
480 if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
481 limit = min(limit, round_up(wakeup, PAGE_SIZE));
482
483 if (limit > head)
484 return limit;
485
486 arm_spe_pmu_pad_buf(handle, handle->size);
487 no_space:
488 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
489 perf_aux_output_end(handle, 0);
490 return 0;
491 }
492
arm_spe_pmu_next_off(struct perf_output_handle * handle)493 static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle)
494 {
495 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
496 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
497 u64 limit = __arm_spe_pmu_next_off(handle);
498 u64 head = PERF_IDX2OFF(handle->head, buf);
499
500 /*
501 * If the head has come too close to the end of the buffer,
502 * then pad to the end and recompute the limit.
503 */
504 if (limit && (limit - head < spe_pmu->max_record_sz)) {
505 arm_spe_pmu_pad_buf(handle, limit - head);
506 limit = __arm_spe_pmu_next_off(handle);
507 }
508
509 return limit;
510 }
511
arm_spe_perf_aux_output_begin(struct perf_output_handle * handle,struct perf_event * event)512 static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle,
513 struct perf_event *event)
514 {
515 u64 base, limit;
516 struct arm_spe_pmu_buf *buf;
517
518 if (ATTR_CFG_GET_FLD(&event->attr, discard)) {
519 limit = FIELD_PREP(PMBLIMITR_EL1_FM, PMBLIMITR_EL1_FM_DISCARD);
520 limit |= PMBLIMITR_EL1_E;
521 goto out_write_limit;
522 }
523
524 /* Start a new aux session */
525 buf = perf_aux_output_begin(handle, event);
526 if (!buf) {
527 event->hw.state |= PERF_HES_STOPPED;
528 /*
529 * We still need to clear the limit pointer, since the
530 * profiler might only be disabled by virtue of a fault.
531 */
532 limit = 0;
533 goto out_write_limit;
534 }
535
536 limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle)
537 : arm_spe_pmu_next_off(handle);
538 if (limit)
539 limit |= PMBLIMITR_EL1_E;
540
541 limit += (u64)buf->base;
542 base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf);
543 write_sysreg_s(base, SYS_PMBPTR_EL1);
544
545 out_write_limit:
546 write_sysreg_s(limit, SYS_PMBLIMITR_EL1);
547 }
548
arm_spe_perf_aux_output_end(struct perf_output_handle * handle)549 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
550 {
551 struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
552 u64 offset, size;
553
554 offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base;
555 size = offset - PERF_IDX2OFF(handle->head, buf);
556
557 if (buf->snapshot)
558 handle->head = offset;
559
560 perf_aux_output_end(handle, size);
561 }
562
arm_spe_pmu_disable_and_drain_local(void)563 static void arm_spe_pmu_disable_and_drain_local(void)
564 {
565 /* Disable profiling at EL0 and EL1 */
566 write_sysreg_s(0, SYS_PMSCR_EL1);
567 isb();
568
569 /* Drain any buffered data */
570 psb_csync();
571 dsb(nsh);
572
573 /* Disable the profiling buffer */
574 write_sysreg_s(0, SYS_PMBLIMITR_EL1);
575 isb();
576 }
577
578 /* IRQ handling */
579 static enum arm_spe_pmu_buf_fault_action
arm_spe_pmu_buf_get_fault_act(struct perf_output_handle * handle)580 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle)
581 {
582 const char *err_str;
583 u64 pmbsr;
584 enum arm_spe_pmu_buf_fault_action ret;
585
586 /*
587 * Ensure new profiling data is visible to the CPU and any external
588 * aborts have been resolved.
589 */
590 psb_csync();
591 dsb(nsh);
592
593 /* Ensure hardware updates to PMBPTR_EL1 are visible */
594 isb();
595
596 /* Service required? */
597 pmbsr = read_sysreg_s(SYS_PMBSR_EL1);
598 if (!FIELD_GET(PMBSR_EL1_S, pmbsr))
599 return SPE_PMU_BUF_FAULT_ACT_SPURIOUS;
600
601 /*
602 * If we've lost data, disable profiling and also set the PARTIAL
603 * flag to indicate that the last record is corrupted.
604 */
605 if (FIELD_GET(PMBSR_EL1_DL, pmbsr))
606 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED |
607 PERF_AUX_FLAG_PARTIAL);
608
609 /* Report collisions to userspace so that it can up the period */
610 if (FIELD_GET(PMBSR_EL1_COLL, pmbsr))
611 perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
612
613 /* We only expect buffer management events */
614 switch (FIELD_GET(PMBSR_EL1_EC, pmbsr)) {
615 case PMBSR_EL1_EC_BUF:
616 /* Handled below */
617 break;
618 case PMBSR_EL1_EC_FAULT_S1:
619 case PMBSR_EL1_EC_FAULT_S2:
620 err_str = "Unexpected buffer fault";
621 goto out_err;
622 default:
623 err_str = "Unknown error code";
624 goto out_err;
625 }
626
627 /* Buffer management event */
628 switch (FIELD_GET(PMBSR_EL1_BUF_BSC_MASK, pmbsr)) {
629 case PMBSR_EL1_BUF_BSC_FULL:
630 ret = SPE_PMU_BUF_FAULT_ACT_OK;
631 goto out_stop;
632 default:
633 err_str = "Unknown buffer status code";
634 }
635
636 out_err:
637 pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n",
638 err_str, smp_processor_id(), pmbsr,
639 read_sysreg_s(SYS_PMBPTR_EL1),
640 read_sysreg_s(SYS_PMBLIMITR_EL1));
641 ret = SPE_PMU_BUF_FAULT_ACT_FATAL;
642
643 out_stop:
644 arm_spe_perf_aux_output_end(handle);
645 return ret;
646 }
647
arm_spe_pmu_irq_handler(int irq,void * dev)648 static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
649 {
650 struct perf_output_handle *handle = dev;
651 struct perf_event *event = handle->event;
652 enum arm_spe_pmu_buf_fault_action act;
653
654 if (!perf_get_aux(handle))
655 return IRQ_NONE;
656
657 act = arm_spe_pmu_buf_get_fault_act(handle);
658 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
659 return IRQ_NONE;
660
661 /*
662 * Ensure perf callbacks have completed, which may disable the
663 * profiling buffer in response to a TRUNCATION flag.
664 */
665 irq_work_run();
666
667 switch (act) {
668 case SPE_PMU_BUF_FAULT_ACT_FATAL:
669 /*
670 * If a fatal exception occurred then leaving the profiling
671 * buffer enabled is a recipe waiting to happen. Since
672 * fatal faults don't always imply truncation, make sure
673 * that the profiling buffer is disabled explicitly before
674 * clearing the syndrome register.
675 */
676 arm_spe_pmu_disable_and_drain_local();
677 break;
678 case SPE_PMU_BUF_FAULT_ACT_OK:
679 /*
680 * We handled the fault (the buffer was full), so resume
681 * profiling as long as we didn't detect truncation.
682 * PMBPTR might be misaligned, but we'll burn that bridge
683 * when we get to it.
684 */
685 if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) {
686 arm_spe_perf_aux_output_begin(handle, event);
687 isb();
688 }
689 break;
690 case SPE_PMU_BUF_FAULT_ACT_SPURIOUS:
691 /* We've seen you before, but GCC has the memory of a sieve. */
692 break;
693 }
694
695 /* The buffer pointers are now sane, so resume profiling. */
696 write_sysreg_s(0, SYS_PMBSR_EL1);
697 return IRQ_HANDLED;
698 }
699
arm_spe_pmsevfr_res0(u16 pmsver)700 static u64 arm_spe_pmsevfr_res0(u16 pmsver)
701 {
702 switch (pmsver) {
703 case ID_AA64DFR0_EL1_PMSVer_IMP:
704 return PMSEVFR_EL1_RES0_IMP;
705 case ID_AA64DFR0_EL1_PMSVer_V1P1:
706 return PMSEVFR_EL1_RES0_V1P1;
707 case ID_AA64DFR0_EL1_PMSVer_V1P2:
708 /* Return the highest version we support in default */
709 default:
710 return PMSEVFR_EL1_RES0_V1P2;
711 }
712 }
713
714 /* Perf callbacks */
arm_spe_pmu_event_init(struct perf_event * event)715 static int arm_spe_pmu_event_init(struct perf_event *event)
716 {
717 u64 reg;
718 struct perf_event_attr *attr = &event->attr;
719 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
720
721 /* This is, of course, deeply driver-specific */
722 if (attr->type != event->pmu->type)
723 return -ENOENT;
724
725 if (event->cpu >= 0 &&
726 !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
727 return -ENOENT;
728
729 if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
730 return -EOPNOTSUPP;
731
732 if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
733 return -EOPNOTSUPP;
734
735 if (attr->exclude_idle)
736 return -EOPNOTSUPP;
737
738 /*
739 * Feedback-directed frequency throttling doesn't work when we
740 * have a buffer of samples. We'd need to manually count the
741 * samples in the buffer when it fills up and adjust the event
742 * count to reflect that. Instead, just force the user to specify
743 * a sample period.
744 */
745 if (attr->freq)
746 return -EINVAL;
747
748 reg = arm_spe_event_to_pmsfcr(event);
749 if ((FIELD_GET(PMSFCR_EL1_FE, reg)) &&
750 !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT))
751 return -EOPNOTSUPP;
752
753 if ((FIELD_GET(PMSFCR_EL1_FnE, reg)) &&
754 !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT))
755 return -EOPNOTSUPP;
756
757 if ((FIELD_GET(PMSFCR_EL1_FT, reg)) &&
758 !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP))
759 return -EOPNOTSUPP;
760
761 if ((FIELD_GET(PMSFCR_EL1_FL, reg)) &&
762 !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT))
763 return -EOPNOTSUPP;
764
765 if (ATTR_CFG_GET_FLD(&event->attr, discard) &&
766 !(spe_pmu->features & SPE_PMU_FEAT_DISCARD))
767 return -EOPNOTSUPP;
768
769 set_spe_event_has_cx(event);
770 reg = arm_spe_event_to_pmscr(event);
771 if (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))
772 return perf_allow_kernel();
773
774 return 0;
775 }
776
arm_spe_pmu_start(struct perf_event * event,int flags)777 static void arm_spe_pmu_start(struct perf_event *event, int flags)
778 {
779 u64 reg;
780 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
781 struct hw_perf_event *hwc = &event->hw;
782 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
783
784 hwc->state = 0;
785 arm_spe_perf_aux_output_begin(handle, event);
786 if (hwc->state)
787 return;
788
789 reg = arm_spe_event_to_pmsfcr(event);
790 write_sysreg_s(reg, SYS_PMSFCR_EL1);
791
792 reg = arm_spe_event_to_pmsevfr(event);
793 write_sysreg_s(reg, SYS_PMSEVFR_EL1);
794
795 if (spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT) {
796 reg = arm_spe_event_to_pmsnevfr(event);
797 write_sysreg_s(reg, SYS_PMSNEVFR_EL1);
798 }
799
800 reg = arm_spe_event_to_pmslatfr(event);
801 write_sysreg_s(reg, SYS_PMSLATFR_EL1);
802
803 if (flags & PERF_EF_RELOAD) {
804 reg = arm_spe_event_to_pmsirr(event);
805 write_sysreg_s(reg, SYS_PMSIRR_EL1);
806 isb();
807 reg = local64_read(&hwc->period_left);
808 write_sysreg_s(reg, SYS_PMSICR_EL1);
809 }
810
811 reg = arm_spe_event_to_pmscr(event);
812 isb();
813 write_sysreg_s(reg, SYS_PMSCR_EL1);
814 }
815
arm_spe_pmu_stop(struct perf_event * event,int flags)816 static void arm_spe_pmu_stop(struct perf_event *event, int flags)
817 {
818 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
819 struct hw_perf_event *hwc = &event->hw;
820 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
821
822 /* If we're already stopped, then nothing to do */
823 if (hwc->state & PERF_HES_STOPPED)
824 return;
825
826 /* Stop all trace generation */
827 arm_spe_pmu_disable_and_drain_local();
828
829 if (flags & PERF_EF_UPDATE) {
830 /*
831 * If there's a fault pending then ensure we contain it
832 * to this buffer, since we might be on the context-switch
833 * path.
834 */
835 if (perf_get_aux(handle)) {
836 enum arm_spe_pmu_buf_fault_action act;
837
838 act = arm_spe_pmu_buf_get_fault_act(handle);
839 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
840 arm_spe_perf_aux_output_end(handle);
841 else
842 write_sysreg_s(0, SYS_PMBSR_EL1);
843 }
844
845 /*
846 * This may also contain ECOUNT, but nobody else should
847 * be looking at period_left, since we forbid frequency
848 * based sampling.
849 */
850 local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1));
851 hwc->state |= PERF_HES_UPTODATE;
852 }
853
854 hwc->state |= PERF_HES_STOPPED;
855 }
856
arm_spe_pmu_add(struct perf_event * event,int flags)857 static int arm_spe_pmu_add(struct perf_event *event, int flags)
858 {
859 int ret = 0;
860 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
861 struct hw_perf_event *hwc = &event->hw;
862 int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu;
863
864 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
865 return -ENOENT;
866
867 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
868
869 if (flags & PERF_EF_START) {
870 arm_spe_pmu_start(event, PERF_EF_RELOAD);
871 if (hwc->state & PERF_HES_STOPPED)
872 ret = -EINVAL;
873 }
874
875 return ret;
876 }
877
arm_spe_pmu_del(struct perf_event * event,int flags)878 static void arm_spe_pmu_del(struct perf_event *event, int flags)
879 {
880 arm_spe_pmu_stop(event, PERF_EF_UPDATE);
881 }
882
arm_spe_pmu_read(struct perf_event * event)883 static void arm_spe_pmu_read(struct perf_event *event)
884 {
885 }
886
arm_spe_pmu_setup_aux(struct perf_event * event,void ** pages,int nr_pages,bool snapshot)887 static void *arm_spe_pmu_setup_aux(struct perf_event *event, void **pages,
888 int nr_pages, bool snapshot)
889 {
890 int i, cpu = event->cpu;
891 struct page **pglist;
892 struct arm_spe_pmu_buf *buf;
893
894 /* We need at least two pages for this to work. */
895 if (nr_pages < 2)
896 return NULL;
897
898 /*
899 * We require an even number of pages for snapshot mode, so that
900 * we can effectively treat the buffer as consisting of two equal
901 * parts and give userspace a fighting chance of getting some
902 * useful data out of it.
903 */
904 if (snapshot && (nr_pages & 1))
905 return NULL;
906
907 if (cpu == -1)
908 cpu = raw_smp_processor_id();
909
910 buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu));
911 if (!buf)
912 return NULL;
913
914 pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
915 if (!pglist)
916 goto out_free_buf;
917
918 for (i = 0; i < nr_pages; ++i)
919 pglist[i] = virt_to_page(pages[i]);
920
921 buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
922 if (!buf->base)
923 goto out_free_pglist;
924
925 buf->nr_pages = nr_pages;
926 buf->snapshot = snapshot;
927
928 kfree(pglist);
929 return buf;
930
931 out_free_pglist:
932 kfree(pglist);
933 out_free_buf:
934 kfree(buf);
935 return NULL;
936 }
937
arm_spe_pmu_free_aux(void * aux)938 static void arm_spe_pmu_free_aux(void *aux)
939 {
940 struct arm_spe_pmu_buf *buf = aux;
941
942 vunmap(buf->base);
943 kfree(buf);
944 }
945
946 /* Initialisation and teardown functions */
arm_spe_pmu_perf_init(struct arm_spe_pmu * spe_pmu)947 static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
948 {
949 static atomic_t pmu_idx = ATOMIC_INIT(-1);
950
951 int idx;
952 char *name;
953 struct device *dev = &spe_pmu->pdev->dev;
954
955 spe_pmu->pmu = (struct pmu) {
956 .module = THIS_MODULE,
957 .parent = &spe_pmu->pdev->dev,
958 .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
959 .attr_groups = arm_spe_pmu_attr_groups,
960 /*
961 * We hitch a ride on the software context here, so that
962 * we can support per-task profiling (which is not possible
963 * with the invalid context as it doesn't get sched callbacks).
964 * This requires that userspace either uses a dummy event for
965 * perf_event_open, since the aux buffer is not setup until
966 * a subsequent mmap, or creates the profiling event in a
967 * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it
968 * once the buffer has been created.
969 */
970 .task_ctx_nr = perf_sw_context,
971 .event_init = arm_spe_pmu_event_init,
972 .add = arm_spe_pmu_add,
973 .del = arm_spe_pmu_del,
974 .start = arm_spe_pmu_start,
975 .stop = arm_spe_pmu_stop,
976 .read = arm_spe_pmu_read,
977 .setup_aux = arm_spe_pmu_setup_aux,
978 .free_aux = arm_spe_pmu_free_aux,
979 };
980
981 idx = atomic_inc_return(&pmu_idx);
982 name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx);
983 if (!name) {
984 dev_err(dev, "failed to allocate name for pmu %d\n", idx);
985 return -ENOMEM;
986 }
987
988 return perf_pmu_register(&spe_pmu->pmu, name, -1);
989 }
990
arm_spe_pmu_perf_destroy(struct arm_spe_pmu * spe_pmu)991 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu)
992 {
993 perf_pmu_unregister(&spe_pmu->pmu);
994 }
995
__arm_spe_pmu_dev_probe(void * info)996 static void __arm_spe_pmu_dev_probe(void *info)
997 {
998 int fld;
999 u64 reg;
1000 struct arm_spe_pmu *spe_pmu = info;
1001 struct device *dev = &spe_pmu->pdev->dev;
1002
1003 fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1),
1004 ID_AA64DFR0_EL1_PMSVer_SHIFT);
1005 if (!fld) {
1006 dev_err(dev,
1007 "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n",
1008 fld, smp_processor_id());
1009 return;
1010 }
1011 spe_pmu->pmsver = (u16)fld;
1012
1013 /* Read PMBIDR first to determine whether or not we have access */
1014 reg = read_sysreg_s(SYS_PMBIDR_EL1);
1015 if (FIELD_GET(PMBIDR_EL1_P, reg)) {
1016 dev_err(dev,
1017 "profiling buffer owned by higher exception level\n");
1018 return;
1019 }
1020
1021 /* Minimum alignment. If it's out-of-range, then fail the probe */
1022 fld = FIELD_GET(PMBIDR_EL1_ALIGN, reg);
1023 spe_pmu->align = 1 << fld;
1024 if (spe_pmu->align > SZ_2K) {
1025 dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n",
1026 fld, smp_processor_id());
1027 return;
1028 }
1029
1030 /* It's now safe to read PMSIDR and figure out what we've got */
1031 reg = read_sysreg_s(SYS_PMSIDR_EL1);
1032 if (FIELD_GET(PMSIDR_EL1_FE, reg))
1033 spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT;
1034
1035 if (FIELD_GET(PMSIDR_EL1_FnE, reg))
1036 spe_pmu->features |= SPE_PMU_FEAT_INV_FILT_EVT;
1037
1038 if (FIELD_GET(PMSIDR_EL1_FT, reg))
1039 spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;
1040
1041 if (FIELD_GET(PMSIDR_EL1_FL, reg))
1042 spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT;
1043
1044 if (FIELD_GET(PMSIDR_EL1_ARCHINST, reg))
1045 spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST;
1046
1047 if (FIELD_GET(PMSIDR_EL1_LDS, reg))
1048 spe_pmu->features |= SPE_PMU_FEAT_LDS;
1049
1050 if (FIELD_GET(PMSIDR_EL1_ERND, reg))
1051 spe_pmu->features |= SPE_PMU_FEAT_ERND;
1052
1053 if (spe_pmu->pmsver >= ID_AA64DFR0_EL1_PMSVer_V1P2)
1054 spe_pmu->features |= SPE_PMU_FEAT_DISCARD;
1055
1056 /* This field has a spaced out encoding, so just use a look-up */
1057 fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg);
1058 switch (fld) {
1059 case PMSIDR_EL1_INTERVAL_256:
1060 spe_pmu->min_period = 256;
1061 break;
1062 case PMSIDR_EL1_INTERVAL_512:
1063 spe_pmu->min_period = 512;
1064 break;
1065 case PMSIDR_EL1_INTERVAL_768:
1066 spe_pmu->min_period = 768;
1067 break;
1068 case PMSIDR_EL1_INTERVAL_1024:
1069 spe_pmu->min_period = 1024;
1070 break;
1071 case PMSIDR_EL1_INTERVAL_1536:
1072 spe_pmu->min_period = 1536;
1073 break;
1074 case PMSIDR_EL1_INTERVAL_2048:
1075 spe_pmu->min_period = 2048;
1076 break;
1077 case PMSIDR_EL1_INTERVAL_3072:
1078 spe_pmu->min_period = 3072;
1079 break;
1080 default:
1081 dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
1082 fld);
1083 fallthrough;
1084 case PMSIDR_EL1_INTERVAL_4096:
1085 spe_pmu->min_period = 4096;
1086 }
1087
1088 /* Maximum record size. If it's out-of-range, then fail the probe */
1089 fld = FIELD_GET(PMSIDR_EL1_MAXSIZE, reg);
1090 spe_pmu->max_record_sz = 1 << fld;
1091 if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) {
1092 dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
1093 fld, smp_processor_id());
1094 return;
1095 }
1096
1097 fld = FIELD_GET(PMSIDR_EL1_COUNTSIZE, reg);
1098 switch (fld) {
1099 default:
1100 dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
1101 fld);
1102 fallthrough;
1103 case PMSIDR_EL1_COUNTSIZE_12_BIT_SAT:
1104 spe_pmu->counter_sz = 12;
1105 break;
1106 case PMSIDR_EL1_COUNTSIZE_16_BIT_SAT:
1107 spe_pmu->counter_sz = 16;
1108 }
1109
1110 dev_info(dev,
1111 "probed SPEv1.%d for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n",
1112 spe_pmu->pmsver - 1, cpumask_pr_args(&spe_pmu->supported_cpus),
1113 spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features);
1114
1115 spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED;
1116 }
1117
__arm_spe_pmu_reset_local(void)1118 static void __arm_spe_pmu_reset_local(void)
1119 {
1120 /*
1121 * This is probably overkill, as we have no idea where we're
1122 * draining any buffered data to...
1123 */
1124 arm_spe_pmu_disable_and_drain_local();
1125
1126 /* Reset the buffer base pointer */
1127 write_sysreg_s(0, SYS_PMBPTR_EL1);
1128 isb();
1129
1130 /* Clear any pending management interrupts */
1131 write_sysreg_s(0, SYS_PMBSR_EL1);
1132 isb();
1133 }
1134
__arm_spe_pmu_setup_one(void * info)1135 static void __arm_spe_pmu_setup_one(void *info)
1136 {
1137 struct arm_spe_pmu *spe_pmu = info;
1138
1139 __arm_spe_pmu_reset_local();
1140 enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE);
1141 }
1142
__arm_spe_pmu_stop_one(void * info)1143 static void __arm_spe_pmu_stop_one(void *info)
1144 {
1145 struct arm_spe_pmu *spe_pmu = info;
1146
1147 disable_percpu_irq(spe_pmu->irq);
1148 __arm_spe_pmu_reset_local();
1149 }
1150
arm_spe_pmu_cpu_startup(unsigned int cpu,struct hlist_node * node)1151 static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node)
1152 {
1153 struct arm_spe_pmu *spe_pmu;
1154
1155 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1156 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1157 return 0;
1158
1159 __arm_spe_pmu_setup_one(spe_pmu);
1160 return 0;
1161 }
1162
arm_spe_pmu_cpu_teardown(unsigned int cpu,struct hlist_node * node)1163 static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node)
1164 {
1165 struct arm_spe_pmu *spe_pmu;
1166
1167 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1168 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1169 return 0;
1170
1171 __arm_spe_pmu_stop_one(spe_pmu);
1172 return 0;
1173 }
1174
arm_spe_pmu_dev_init(struct arm_spe_pmu * spe_pmu)1175 static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu)
1176 {
1177 int ret;
1178 cpumask_t *mask = &spe_pmu->supported_cpus;
1179
1180 /* Make sure we probe the hardware on a relevant CPU */
1181 ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1);
1182 if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED))
1183 return -ENXIO;
1184
1185 /* Request our PPIs (note that the IRQ is still disabled) */
1186 ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME,
1187 spe_pmu->handle);
1188 if (ret)
1189 return ret;
1190
1191 /*
1192 * Register our hotplug notifier now so we don't miss any events.
1193 * This will enable the IRQ for any supported CPUs that are already
1194 * up.
1195 */
1196 ret = cpuhp_state_add_instance(arm_spe_pmu_online,
1197 &spe_pmu->hotplug_node);
1198 if (ret)
1199 free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1200
1201 return ret;
1202 }
1203
arm_spe_pmu_dev_teardown(struct arm_spe_pmu * spe_pmu)1204 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu)
1205 {
1206 cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node);
1207 free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1208 }
1209
1210 /* Driver and device probing */
arm_spe_pmu_irq_probe(struct arm_spe_pmu * spe_pmu)1211 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu)
1212 {
1213 struct platform_device *pdev = spe_pmu->pdev;
1214 int irq = platform_get_irq(pdev, 0);
1215
1216 if (irq < 0)
1217 return -ENXIO;
1218
1219 if (!irq_is_percpu(irq)) {
1220 dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq);
1221 return -EINVAL;
1222 }
1223
1224 if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) {
1225 dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq);
1226 return -EINVAL;
1227 }
1228
1229 spe_pmu->irq = irq;
1230 return 0;
1231 }
1232
1233 static const struct of_device_id arm_spe_pmu_of_match[] = {
1234 { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 },
1235 { /* Sentinel */ },
1236 };
1237 MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match);
1238
1239 static const struct platform_device_id arm_spe_match[] = {
1240 { ARMV8_SPE_PDEV_NAME, 0},
1241 { }
1242 };
1243 MODULE_DEVICE_TABLE(platform, arm_spe_match);
1244
arm_spe_pmu_device_probe(struct platform_device * pdev)1245 static int arm_spe_pmu_device_probe(struct platform_device *pdev)
1246 {
1247 int ret;
1248 struct arm_spe_pmu *spe_pmu;
1249 struct device *dev = &pdev->dev;
1250
1251 /*
1252 * If kernelspace is unmapped when running at EL0, then the SPE
1253 * buffer will fault and prematurely terminate the AUX session.
1254 */
1255 if (arm64_kernel_unmapped_at_el0()) {
1256 dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n");
1257 return -EPERM;
1258 }
1259
1260 spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL);
1261 if (!spe_pmu)
1262 return -ENOMEM;
1263
1264 spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle));
1265 if (!spe_pmu->handle)
1266 return -ENOMEM;
1267
1268 spe_pmu->pdev = pdev;
1269 platform_set_drvdata(pdev, spe_pmu);
1270
1271 ret = arm_spe_pmu_irq_probe(spe_pmu);
1272 if (ret)
1273 goto out_free_handle;
1274
1275 ret = arm_spe_pmu_dev_init(spe_pmu);
1276 if (ret)
1277 goto out_free_handle;
1278
1279 ret = arm_spe_pmu_perf_init(spe_pmu);
1280 if (ret)
1281 goto out_teardown_dev;
1282
1283 return 0;
1284
1285 out_teardown_dev:
1286 arm_spe_pmu_dev_teardown(spe_pmu);
1287 out_free_handle:
1288 free_percpu(spe_pmu->handle);
1289 return ret;
1290 }
1291
arm_spe_pmu_device_remove(struct platform_device * pdev)1292 static void arm_spe_pmu_device_remove(struct platform_device *pdev)
1293 {
1294 struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
1295
1296 arm_spe_pmu_perf_destroy(spe_pmu);
1297 arm_spe_pmu_dev_teardown(spe_pmu);
1298 free_percpu(spe_pmu->handle);
1299 }
1300
1301 static struct platform_driver arm_spe_pmu_driver = {
1302 .id_table = arm_spe_match,
1303 .driver = {
1304 .name = DRVNAME,
1305 .of_match_table = of_match_ptr(arm_spe_pmu_of_match),
1306 .suppress_bind_attrs = true,
1307 },
1308 .probe = arm_spe_pmu_device_probe,
1309 .remove = arm_spe_pmu_device_remove,
1310 };
1311
arm_spe_pmu_init(void)1312 static int __init arm_spe_pmu_init(void)
1313 {
1314 int ret;
1315
1316 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
1317 arm_spe_pmu_cpu_startup,
1318 arm_spe_pmu_cpu_teardown);
1319 if (ret < 0)
1320 return ret;
1321 arm_spe_pmu_online = ret;
1322
1323 ret = platform_driver_register(&arm_spe_pmu_driver);
1324 if (ret)
1325 cpuhp_remove_multi_state(arm_spe_pmu_online);
1326
1327 return ret;
1328 }
1329
arm_spe_pmu_exit(void)1330 static void __exit arm_spe_pmu_exit(void)
1331 {
1332 platform_driver_unregister(&arm_spe_pmu_driver);
1333 cpuhp_remove_multi_state(arm_spe_pmu_online);
1334 }
1335
1336 module_init(arm_spe_pmu_init);
1337 module_exit(arm_spe_pmu_exit);
1338
1339 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension");
1340 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1341 MODULE_LICENSE("GPL v2");
1342