1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_QMI_H 8 #define ATH11K_QMI_H 9 10 #if defined(__FreeBSD__) 11 #include <linux/types.h> 12 #include <linux/list.h> 13 #endif 14 #include <linux/mutex.h> 15 #include <linux/soc/qcom/qmi.h> 16 17 #define ATH11K_HOST_VERSION_STRING "WIN" 18 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 19 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 20 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 21 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 22 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 23 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 24 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 25 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 26 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 27 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 28 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750 0x03 29 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 30 #define ATH11K_QMI_RESP_LEN_MAX 8192 31 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 32 #define ATH11K_QMI_CALDB_SIZE 0x480000 33 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 34 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 5 35 36 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 37 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 38 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x003E 39 #define QMI_WLFW_FW_READY_IND_V01 0x0021 40 #define QMI_WLFW_FW_INIT_DONE_IND_V01 0x0038 41 42 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 43 #define ATH11K_FIRMWARE_MODE_OFF 4 44 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) 45 46 #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 47 48 struct ath11k_base; 49 50 enum ath11k_qmi_file_type { 51 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 52 ATH11K_QMI_FILE_TYPE_CALDATA = 2, 53 ATH11K_QMI_FILE_TYPE_EEPROM, 54 ATH11K_QMI_MAX_FILE_TYPE, 55 }; 56 57 enum ath11k_qmi_bdf_type { 58 ATH11K_QMI_BDF_TYPE_BIN = 0, 59 ATH11K_QMI_BDF_TYPE_ELF = 1, 60 ATH11K_QMI_BDF_TYPE_REGDB = 4, 61 }; 62 63 enum ath11k_qmi_event_type { 64 ATH11K_QMI_EVENT_SERVER_ARRIVE, 65 ATH11K_QMI_EVENT_SERVER_EXIT, 66 ATH11K_QMI_EVENT_REQUEST_MEM, 67 ATH11K_QMI_EVENT_FW_MEM_READY, 68 ATH11K_QMI_EVENT_FW_READY, 69 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 70 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 71 ATH11K_QMI_EVENT_REGISTER_DRIVER, 72 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 73 ATH11K_QMI_EVENT_RECOVERY, 74 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 75 ATH11K_QMI_EVENT_POWER_UP, 76 ATH11K_QMI_EVENT_POWER_DOWN, 77 ATH11K_QMI_EVENT_FW_INIT_DONE, 78 ATH11K_QMI_EVENT_MAX, 79 }; 80 81 struct ath11k_qmi_driver_event { 82 struct list_head list; 83 enum ath11k_qmi_event_type type; 84 void *data; 85 }; 86 87 struct ath11k_qmi_ce_cfg { 88 const struct ce_pipe_config *tgt_ce; 89 int tgt_ce_len; 90 const struct service_to_pipe *svc_to_ce_map; 91 int svc_to_ce_map_len; 92 const u8 *shadow_reg; 93 int shadow_reg_len; 94 u32 *shadow_reg_v2; 95 int shadow_reg_v2_len; 96 }; 97 98 struct ath11k_qmi_event_msg { 99 struct list_head list; 100 enum ath11k_qmi_event_type type; 101 }; 102 103 struct target_mem_chunk { 104 u32 size; 105 u32 type; 106 u32 prev_size; 107 u32 prev_type; 108 dma_addr_t paddr; 109 union { 110 u32 *vaddr; 111 void __iomem *iaddr; 112 void *anyaddr; 113 }; 114 }; 115 116 struct target_info { 117 u32 chip_id; 118 u32 chip_family; 119 u32 board_id; 120 u32 soc_id; 121 u32 fw_version; 122 u32 eeprom_caldata; 123 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 124 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 125 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH]; 126 }; 127 128 struct m3_mem_region { 129 u32 size; 130 dma_addr_t paddr; 131 void *vaddr; 132 }; 133 134 struct ath11k_qmi { 135 struct ath11k_base *ab; 136 struct qmi_handle handle; 137 struct sockaddr_qrtr sq; 138 struct work_struct event_work; 139 struct workqueue_struct *event_wq; 140 struct list_head event_list; 141 spinlock_t event_lock; /* spinlock for qmi event list */ 142 struct ath11k_qmi_ce_cfg ce_cfg; 143 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 144 u32 mem_seg_count; 145 u32 target_mem_mode; 146 bool target_mem_delayed; 147 u8 cal_done; 148 struct target_info target; 149 struct m3_mem_region m3_mem; 150 unsigned int service_ins_id; 151 wait_queue_head_t cold_boot_waitq; 152 }; 153 154 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 155 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 156 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 157 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 158 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 159 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 160 #define HOST_DDR_REGION_TYPE 0x1 161 #define BDF_MEM_REGION_TYPE 0x2 162 #define M3_DUMP_REGION_TYPE 0x3 163 #define CALDB_MEM_REGION_TYPE 0x4 164 #define PAGEABLE_MEM_REGION_TYPE 0x9 165 166 struct qmi_wlanfw_host_cap_req_msg_v01 { 167 u8 num_clients_valid; 168 u32 num_clients; 169 u8 wake_msi_valid; 170 u32 wake_msi; 171 u8 gpios_valid; 172 u32 gpios_len; 173 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 174 u8 nm_modem_valid; 175 u8 nm_modem; 176 u8 bdf_support_valid; 177 u8 bdf_support; 178 u8 bdf_cache_support_valid; 179 u8 bdf_cache_support; 180 u8 m3_support_valid; 181 u8 m3_support; 182 u8 m3_cache_support_valid; 183 u8 m3_cache_support; 184 u8 cal_filesys_support_valid; 185 u8 cal_filesys_support; 186 u8 cal_cache_support_valid; 187 u8 cal_cache_support; 188 u8 cal_done_valid; 189 u8 cal_done; 190 u8 mem_bucket_valid; 191 u32 mem_bucket; 192 u8 mem_cfg_mode_valid; 193 u8 mem_cfg_mode; 194 }; 195 196 struct qmi_wlanfw_host_cap_resp_msg_v01 { 197 struct qmi_response_type_v01 resp; 198 }; 199 200 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 201 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 202 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 203 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 204 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 205 206 struct qmi_wlanfw_ind_register_req_msg_v01 { 207 u8 fw_ready_enable_valid; 208 u8 fw_ready_enable; 209 u8 initiate_cal_download_enable_valid; 210 u8 initiate_cal_download_enable; 211 u8 initiate_cal_update_enable_valid; 212 u8 initiate_cal_update_enable; 213 u8 msa_ready_enable_valid; 214 u8 msa_ready_enable; 215 u8 pin_connect_result_enable_valid; 216 u8 pin_connect_result_enable; 217 u8 client_id_valid; 218 u32 client_id; 219 u8 request_mem_enable_valid; 220 u8 request_mem_enable; 221 u8 fw_mem_ready_enable_valid; 222 u8 fw_mem_ready_enable; 223 u8 fw_init_done_enable_valid; 224 u8 fw_init_done_enable; 225 u8 rejuvenate_enable_valid; 226 u32 rejuvenate_enable; 227 u8 xo_cal_enable_valid; 228 u8 xo_cal_enable; 229 u8 cal_done_enable_valid; 230 u8 cal_done_enable; 231 }; 232 233 struct qmi_wlanfw_ind_register_resp_msg_v01 { 234 struct qmi_response_type_v01 resp; 235 u8 fw_status_valid; 236 u64 fw_status; 237 }; 238 239 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 240 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 241 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 242 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 243 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 244 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 245 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 246 247 struct qmi_wlanfw_mem_cfg_s_v01 { 248 u64 offset; 249 u32 size; 250 u8 secure_flag; 251 }; 252 253 enum qmi_wlanfw_mem_type_enum_v01 { 254 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 255 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 256 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 257 QMI_WLANFW_MEM_BDF_V01 = 2, 258 QMI_WLANFW_MEM_M3_V01 = 3, 259 QMI_WLANFW_MEM_CAL_V01 = 4, 260 QMI_WLANFW_MEM_DPD_V01 = 5, 261 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 262 }; 263 264 struct qmi_wlanfw_mem_seg_s_v01 { 265 u32 size; 266 enum qmi_wlanfw_mem_type_enum_v01 type; 267 u32 mem_cfg_len; 268 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 269 }; 270 271 struct qmi_wlanfw_request_mem_ind_msg_v01 { 272 u32 mem_seg_len; 273 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 274 }; 275 276 struct qmi_wlanfw_mem_seg_resp_s_v01 { 277 u64 addr; 278 u32 size; 279 enum qmi_wlanfw_mem_type_enum_v01 type; 280 u8 restore; 281 }; 282 283 struct qmi_wlanfw_respond_mem_req_msg_v01 { 284 u32 mem_seg_len; 285 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 286 }; 287 288 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 289 struct qmi_response_type_v01 resp; 290 }; 291 292 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 293 char placeholder; 294 }; 295 296 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 297 char placeholder; 298 }; 299 300 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 301 char placeholder; 302 }; 303 304 struct qmi_wlfw_fw_init_done_ind_msg_v01 { 305 char placeholder; 306 }; 307 308 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 309 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 310 #define QMI_WLANFW_CAP_REQ_V01 0x0024 311 #define QMI_WLANFW_CAP_RESP_V01 0x0024 312 #define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C 313 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN 0 314 315 enum qmi_wlanfw_pipedir_enum_v01 { 316 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 317 QMI_WLFW_PIPEDIR_IN_V01 = 1, 318 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 319 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 320 }; 321 322 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 323 __le32 pipe_num; 324 __le32 pipe_dir; 325 __le32 nentries; 326 __le32 nbytes_max; 327 __le32 flags; 328 }; 329 330 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 331 __le32 service_id; 332 __le32 pipe_dir; 333 __le32 pipe_num; 334 }; 335 336 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 337 u16 id; 338 u16 offset; 339 }; 340 341 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 342 u32 addr; 343 }; 344 345 struct qmi_wlanfw_memory_region_info_s_v01 { 346 u64 region_addr; 347 u32 size; 348 u8 secure_flag; 349 }; 350 351 struct qmi_wlanfw_rf_chip_info_s_v01 { 352 u32 chip_id; 353 u32 chip_family; 354 }; 355 356 struct qmi_wlanfw_rf_board_info_s_v01 { 357 u32 board_id; 358 }; 359 360 struct qmi_wlanfw_soc_info_s_v01 { 361 u32 soc_id; 362 }; 363 364 struct qmi_wlanfw_fw_version_info_s_v01 { 365 u32 fw_version; 366 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 367 }; 368 369 enum qmi_wlanfw_cal_temp_id_enum_v01 { 370 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 371 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 372 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 373 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 374 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 375 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 376 }; 377 378 struct qmi_wlanfw_cap_resp_msg_v01 { 379 struct qmi_response_type_v01 resp; 380 u8 chip_info_valid; 381 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 382 u8 board_info_valid; 383 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 384 u8 soc_info_valid; 385 struct qmi_wlanfw_soc_info_s_v01 soc_info; 386 u8 fw_version_info_valid; 387 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 388 u8 fw_build_id_valid; 389 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 390 u8 num_macs_valid; 391 u8 num_macs; 392 u8 voltage_mv_valid; 393 u32 voltage_mv; 394 u8 time_freq_hz_valid; 395 u32 time_freq_hz; 396 u8 otp_version_valid; 397 u32 otp_version; 398 u8 eeprom_read_timeout_valid; 399 u32 eeprom_read_timeout; 400 }; 401 402 struct qmi_wlanfw_cap_req_msg_v01 { 403 char placeholder; 404 }; 405 406 struct qmi_wlanfw_device_info_req_msg_v01 { 407 char placeholder; 408 }; 409 410 struct qmi_wlanfw_device_info_resp_msg_v01 { 411 struct qmi_response_type_v01 resp; 412 u64 bar_addr; 413 u32 bar_size; 414 u8 bar_addr_valid; 415 u8 bar_size_valid; 416 }; 417 418 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 419 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 420 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 421 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 422 /* TODO: Need to check with MCL and FW team that data can be pointer and 423 * can be last element in structure 424 */ 425 struct qmi_wlanfw_bdf_download_req_msg_v01 { 426 u8 valid; 427 u8 file_id_valid; 428 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 429 u8 total_size_valid; 430 u32 total_size; 431 u8 seg_id_valid; 432 u32 seg_id; 433 u8 data_valid; 434 u32 data_len; 435 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 436 u8 end_valid; 437 u8 end; 438 u8 bdf_type_valid; 439 u8 bdf_type; 440 441 }; 442 443 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 444 struct qmi_response_type_v01 resp; 445 }; 446 447 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 448 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 449 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 450 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 451 452 struct qmi_wlanfw_m3_info_req_msg_v01 { 453 u64 addr; 454 u32 size; 455 }; 456 457 struct qmi_wlanfw_m3_info_resp_msg_v01 { 458 struct qmi_response_type_v01 resp; 459 }; 460 461 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 462 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 463 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 464 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 465 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 4 466 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 467 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 468 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 469 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 470 #define QMI_WLANFW_WLAN_INI_REQ_V01 0x002F 471 #define QMI_WLANFW_MAX_STR_LEN_V01 16 472 #define QMI_WLANFW_MAX_NUM_CE_V01 12 473 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 474 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 475 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 476 477 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 478 u32 mode; 479 u8 hw_debug_valid; 480 u8 hw_debug; 481 }; 482 483 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 484 struct qmi_response_type_v01 resp; 485 }; 486 487 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 488 u8 host_version_valid; 489 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 490 u8 tgt_cfg_valid; 491 u32 tgt_cfg_len; 492 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 493 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 494 u8 svc_cfg_valid; 495 u32 svc_cfg_len; 496 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 497 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 498 u8 shadow_reg_valid; 499 u32 shadow_reg_len; 500 struct qmi_wlanfw_shadow_reg_cfg_s_v01 501 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 502 u8 shadow_reg_v2_valid; 503 u32 shadow_reg_v2_len; 504 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 505 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 506 }; 507 508 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 509 struct qmi_response_type_v01 resp; 510 }; 511 512 struct qmi_wlanfw_wlan_ini_req_msg_v01 { 513 /* Must be set to true if enablefwlog is being passed */ 514 u8 enablefwlog_valid; 515 u8 enablefwlog; 516 }; 517 518 struct qmi_wlanfw_wlan_ini_resp_msg_v01 { 519 struct qmi_response_type_v01 resp; 520 }; 521 522 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 523 u32 mode); 524 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 525 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 526 int ath11k_qmi_init_service(struct ath11k_base *ab); 527 void ath11k_qmi_free_resource(struct ath11k_base *ab); 528 int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab); 529 530 #endif 531