1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH11K_CORE_H
8 #define ATH11K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/rhashtable.h>
17 #include <linux/average.h>
18 #if defined(__FreeBSD__)
19 #include <linux/wait.h>
20 #endif
21 #include "qmi.h"
22 #include "htc.h"
23 #include "wmi.h"
24 #include "hal.h"
25 #include "dp.h"
26 #include "ce.h"
27 #include "mac.h"
28 #include "hw.h"
29 #include "hal_rx.h"
30 #include "reg.h"
31 #include "thermal.h"
32 #include "dbring.h"
33 #include "spectral.h"
34 #include "wow.h"
35
36 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
37
38 #define ATH11K_TX_MGMT_NUM_PENDING_MAX 512
39
40 #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
41
42 /* Pending management packets threshold for dropping probe responses */
43 #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
44
45 #define ATH11K_INVALID_HW_MAC_ID 0xFF
46 #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ)
47
48 /* SMBIOS type containing Board Data File Name Extension */
49 #define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8
50
51 /* SMBIOS type structure length (excluding strings-set) */
52 #define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9
53
54 /* The magic used by QCA spec */
55 #define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_"
56
57 extern unsigned int ath11k_frame_mode;
58 extern bool ath11k_ftm_mode;
59
60 #define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
61
62 #define ATH11K_MON_TIMER_INTERVAL 10
63 #define ATH11K_RESET_TIMEOUT_HZ (20 * HZ)
64 #define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3
65 #define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5
66 #define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
67 #define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
68 #define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
69
70 enum ath11k_supported_bw {
71 ATH11K_BW_20 = 0,
72 ATH11K_BW_40 = 1,
73 ATH11K_BW_80 = 2,
74 ATH11K_BW_160 = 3,
75 };
76
77 enum ath11k_bdf_search {
78 ATH11K_BDF_SEARCH_DEFAULT,
79 ATH11K_BDF_SEARCH_BUS_AND_BOARD,
80 };
81
82 #if defined(__FreeBSD__)
83 #ifdef WME_AC_BE
84 #undef WME_AC_BE
85 #endif
86 #ifdef WME_AC_BK
87 #undef WME_AC_BK
88 #endif
89 #ifdef WME_AC_VI
90 #undef WME_AC_VI
91 #endif
92 #ifdef WME_AC_VO
93 #undef WME_AC_VO
94 #endif
95 #ifdef WME_NUM_AC
96 #undef WME_NUM_AC
97 #endif
98 #endif
99
100 enum wme_ac {
101 WME_AC_BE,
102 WME_AC_BK,
103 WME_AC_VI,
104 WME_AC_VO,
105 WME_NUM_AC
106 };
107
108 #define ATH11K_HT_MCS_MAX 7
109 #define ATH11K_VHT_MCS_MAX 9
110 #define ATH11K_HE_MCS_MAX 11
111
112 enum ath11k_crypt_mode {
113 /* Only use hardware crypto engine */
114 ATH11K_CRYPT_MODE_HW,
115 /* Only use software crypto */
116 ATH11K_CRYPT_MODE_SW,
117 };
118
ath11k_tid_to_ac(u32 tid)119 static inline enum wme_ac ath11k_tid_to_ac(u32 tid)
120 {
121 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
122 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
123 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
124 WME_AC_VO);
125 }
126
127 enum ath11k_skb_flags {
128 ATH11K_SKB_HW_80211_ENCAP = BIT(0),
129 ATH11K_SKB_CIPHER_SET = BIT(1),
130 };
131
132 struct ath11k_skb_cb {
133 dma_addr_t paddr;
134 u8 eid;
135 u8 flags;
136 u32 cipher;
137 struct ath11k *ar;
138 struct ieee80211_vif *vif;
139 } __packed;
140
141 struct ath11k_skb_rxcb {
142 dma_addr_t paddr;
143 bool is_first_msdu;
144 bool is_last_msdu;
145 bool is_continuation;
146 bool is_mcbc;
147 bool is_eapol;
148 struct hal_rx_desc *rx_desc;
149 u8 err_rel_src;
150 u8 err_code;
151 u8 mac_id;
152 u8 unmapped;
153 u8 is_frag;
154 u8 tid;
155 u16 peer_id;
156 u16 seq_no;
157 };
158
159 enum ath11k_hw_rev {
160 ATH11K_HW_IPQ8074,
161 ATH11K_HW_QCA6390_HW20,
162 ATH11K_HW_IPQ6018_HW10,
163 ATH11K_HW_QCN9074_HW10,
164 ATH11K_HW_WCN6855_HW20,
165 ATH11K_HW_WCN6855_HW21,
166 ATH11K_HW_WCN6750_HW10,
167 ATH11K_HW_IPQ5018_HW10,
168 };
169
170 enum ath11k_firmware_mode {
171 /* the default mode, standard 802.11 functionality */
172 ATH11K_FIRMWARE_MODE_NORMAL,
173
174 /* factory tests etc */
175 ATH11K_FIRMWARE_MODE_FTM,
176
177 /* Cold boot calibration */
178 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7,
179 };
180
181 extern bool ath11k_cold_boot_cal;
182
183 #define ATH11K_IRQ_NUM_MAX 52
184 #define ATH11K_EXT_IRQ_NUM_MAX 16
185
186 struct ath11k_ext_irq_grp {
187 struct ath11k_base *ab;
188 u32 irqs[ATH11K_EXT_IRQ_NUM_MAX];
189 u32 num_irq;
190 u32 grp_id;
191 u64 timestamp;
192 bool napi_enabled;
193 struct napi_struct napi;
194 struct net_device napi_ndev;
195 };
196
197 enum ath11k_smbios_cc_type {
198 /* disable country code setting from SMBIOS */
199 ATH11K_SMBIOS_CC_DISABLE = 0,
200
201 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
202 ATH11K_SMBIOS_CC_ISO = 1,
203
204 /* worldwide regdomain */
205 ATH11K_SMBIOS_CC_WW = 2,
206 };
207
208 struct ath11k_smbios_bdf {
209 struct dmi_header hdr;
210
211 u8 features_disabled;
212
213 /* enum ath11k_smbios_cc_type */
214 u8 country_code_flag;
215
216 /* To set specific country, you need to set country code
217 * flag=ATH11K_SMBIOS_CC_ISO first, then if country is United
218 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
219 * 0x53). To set country to INDONESIA, then country code value =
220 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
221 * ATH11K_SMBIOS_CC_WW, then you can use worldwide regulatory
222 * setting.
223 */
224 u16 cc_code;
225
226 u8 bdf_enabled;
227 u8 bdf_ext[];
228 } __packed;
229
230 #define HEHANDLE_CAP_PHYINFO_SIZE 3
231 #define HECAP_PHYINFO_SIZE 9
232 #define HECAP_MACINFO_SIZE 5
233 #define HECAP_TXRX_MCS_NSS_SIZE 2
234 #define HECAP_PPET16_PPET8_MAX_SIZE 25
235
236 #define HE_PPET16_PPET8_SIZE 8
237
238 /* 802.11ax PPE (PPDU packet Extension) threshold */
239 struct he_ppe_threshold {
240 u32 numss_m1;
241 u32 ru_mask;
242 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
243 };
244
245 struct ath11k_he {
246 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
247 u32 hecap_rxmcsnssmap;
248 u32 hecap_txmcsnssmap;
249 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
250 struct he_ppe_threshold hecap_ppet;
251 u32 heop_param;
252 };
253
254 #define MAX_RADIOS 3
255
256 /* ipq5018 hw param macros */
257 #define MAX_RADIOS_5018 1
258 #define CE_CNT_5018 6
259 #define TARGET_CE_CNT_5018 9
260 #define SVC_CE_MAP_LEN_5018 17
261 #define RXDMA_PER_PDEV_5018 1
262
263 enum {
264 WMI_HOST_TP_SCALE_MAX = 0,
265 WMI_HOST_TP_SCALE_50 = 1,
266 WMI_HOST_TP_SCALE_25 = 2,
267 WMI_HOST_TP_SCALE_12 = 3,
268 WMI_HOST_TP_SCALE_MIN = 4,
269 WMI_HOST_TP_SCALE_SIZE = 5,
270 };
271
272 enum ath11k_scan_state {
273 ATH11K_SCAN_IDLE,
274 ATH11K_SCAN_STARTING,
275 ATH11K_SCAN_RUNNING,
276 ATH11K_SCAN_ABORTING,
277 };
278
279 enum ath11k_11d_state {
280 ATH11K_11D_IDLE,
281 ATH11K_11D_PREPARING,
282 ATH11K_11D_RUNNING,
283 };
284
285 enum ath11k_dev_flags {
286 ATH11K_CAC_RUNNING,
287 ATH11K_FLAG_CORE_REGISTERED,
288 ATH11K_FLAG_CRASH_FLUSH,
289 ATH11K_FLAG_RAW_MODE,
290 ATH11K_FLAG_HW_CRYPTO_DISABLED,
291 ATH11K_FLAG_BTCOEX,
292 ATH11K_FLAG_RECOVERY,
293 ATH11K_FLAG_UNREGISTERING,
294 ATH11K_FLAG_REGISTERED,
295 ATH11K_FLAG_QMI_FAIL,
296 ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
297 ATH11K_FLAG_CE_IRQ_ENABLED,
298 ATH11K_FLAG_EXT_IRQ_ENABLED,
299 ATH11K_FLAG_FIXED_MEM_RGN,
300 ATH11K_FLAG_DEVICE_INIT_DONE,
301 ATH11K_FLAG_MULTI_MSI_VECTORS,
302 ATH11K_FLAG_FTM_SEGMENTED,
303 };
304
305 enum ath11k_monitor_flags {
306 ATH11K_FLAG_MONITOR_CONF_ENABLED,
307 ATH11K_FLAG_MONITOR_STARTED,
308 ATH11K_FLAG_MONITOR_VDEV_CREATED,
309 };
310
311 #define ATH11K_IPV6_UC_TYPE 0
312 #define ATH11K_IPV6_AC_TYPE 1
313
314 #define ATH11K_IPV6_MAX_COUNT 16
315 #define ATH11K_IPV4_MAX_COUNT 2
316
317 struct ath11k_arp_ns_offload {
318 u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4];
319 u32 ipv4_count;
320 u32 ipv6_count;
321 u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
322 u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
323 u8 ipv6_type[ATH11K_IPV6_MAX_COUNT];
324 bool ipv6_valid[ATH11K_IPV6_MAX_COUNT];
325 u8 mac_addr[ETH_ALEN];
326 };
327
328 struct ath11k_rekey_data {
329 u8 kck[NL80211_KCK_LEN];
330 u8 kek[NL80211_KCK_LEN];
331 u64 replay_ctr;
332 bool enable_offload;
333 };
334
335 struct ath11k_vif {
336 u32 vdev_id;
337 enum wmi_vdev_type vdev_type;
338 enum wmi_vdev_subtype vdev_subtype;
339 u32 beacon_interval;
340 u32 dtim_period;
341 u16 ast_hash;
342 u16 ast_idx;
343 u16 tcl_metadata;
344 u8 hal_addr_search_flags;
345 u8 search_type;
346
347 struct ath11k *ar;
348 struct ieee80211_vif *vif;
349
350 u16 tx_seq_no;
351 struct wmi_wmm_params_all_arg wmm_params;
352 struct list_head list;
353 union {
354 struct {
355 u32 uapsd;
356 } sta;
357 struct {
358 /* 127 stations; wmi limit */
359 u8 tim_bitmap[16];
360 u8 tim_len;
361 u32 ssid_len;
362 u8 ssid[IEEE80211_MAX_SSID_LEN];
363 bool hidden_ssid;
364 /* P2P_IE with NoA attribute for P2P_GO case */
365 u32 noa_len;
366 u8 *noa_data;
367 } ap;
368 } u;
369
370 bool is_started;
371 bool is_up;
372 bool ftm_responder;
373 bool spectral_enabled;
374 bool ps;
375 u32 aid;
376 u8 bssid[ETH_ALEN];
377 struct cfg80211_bitrate_mask bitrate_mask;
378 struct delayed_work connection_loss_work;
379 int num_legacy_stations;
380 int rtscts_prot_mode;
381 int txpower;
382 bool rsnie_present;
383 bool wpaie_present;
384 bool bcca_zero_sent;
385 bool do_not_send_tmpl;
386 struct ieee80211_chanctx_conf chanctx;
387 struct ath11k_arp_ns_offload arp_ns_offload;
388 struct ath11k_rekey_data rekey_data;
389
390 #ifdef CONFIG_ATH11K_DEBUGFS
391 struct dentry *debugfs_twt;
392 #endif /* CONFIG_ATH11K_DEBUGFS */
393 };
394
395 struct ath11k_vif_iter {
396 u32 vdev_id;
397 struct ath11k_vif *arvif;
398 };
399
400 struct ath11k_rx_peer_stats {
401 u64 num_msdu;
402 u64 num_mpdu_fcs_ok;
403 u64 num_mpdu_fcs_err;
404 u64 tcp_msdu_count;
405 u64 udp_msdu_count;
406 u64 other_msdu_count;
407 u64 ampdu_msdu_count;
408 u64 non_ampdu_msdu_count;
409 u64 stbc_count;
410 u64 beamformed_count;
411 u64 mcs_count[HAL_RX_MAX_MCS + 1];
412 u64 nss_count[HAL_RX_MAX_NSS];
413 u64 bw_count[HAL_RX_BW_MAX];
414 u64 gi_count[HAL_RX_GI_MAX];
415 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
416 u64 tid_count[IEEE80211_NUM_TIDS + 1];
417 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
418 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
419 u64 rx_duration;
420 u64 dcm_count;
421 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
422 };
423
424 #define ATH11K_HE_MCS_NUM 12
425 #define ATH11K_VHT_MCS_NUM 10
426 #define ATH11K_BW_NUM 4
427 #define ATH11K_NSS_NUM 4
428 #define ATH11K_LEGACY_NUM 12
429 #define ATH11K_GI_NUM 4
430 #define ATH11K_HT_MCS_NUM 32
431
432 enum ath11k_pkt_rx_err {
433 ATH11K_PKT_RX_ERR_FCS,
434 ATH11K_PKT_RX_ERR_TKIP,
435 ATH11K_PKT_RX_ERR_CRYPT,
436 ATH11K_PKT_RX_ERR_PEER_IDX_INVAL,
437 ATH11K_PKT_RX_ERR_MAX,
438 };
439
440 enum ath11k_ampdu_subfrm_num {
441 ATH11K_AMPDU_SUBFRM_NUM_10,
442 ATH11K_AMPDU_SUBFRM_NUM_20,
443 ATH11K_AMPDU_SUBFRM_NUM_30,
444 ATH11K_AMPDU_SUBFRM_NUM_40,
445 ATH11K_AMPDU_SUBFRM_NUM_50,
446 ATH11K_AMPDU_SUBFRM_NUM_60,
447 ATH11K_AMPDU_SUBFRM_NUM_MORE,
448 ATH11K_AMPDU_SUBFRM_NUM_MAX,
449 };
450
451 enum ath11k_amsdu_subfrm_num {
452 ATH11K_AMSDU_SUBFRM_NUM_1,
453 ATH11K_AMSDU_SUBFRM_NUM_2,
454 ATH11K_AMSDU_SUBFRM_NUM_3,
455 ATH11K_AMSDU_SUBFRM_NUM_4,
456 ATH11K_AMSDU_SUBFRM_NUM_MORE,
457 ATH11K_AMSDU_SUBFRM_NUM_MAX,
458 };
459
460 enum ath11k_counter_type {
461 ATH11K_COUNTER_TYPE_BYTES,
462 ATH11K_COUNTER_TYPE_PKTS,
463 ATH11K_COUNTER_TYPE_MAX,
464 };
465
466 enum ath11k_stats_type {
467 ATH11K_STATS_TYPE_SUCC,
468 ATH11K_STATS_TYPE_FAIL,
469 ATH11K_STATS_TYPE_RETRY,
470 ATH11K_STATS_TYPE_AMPDU,
471 ATH11K_STATS_TYPE_MAX,
472 };
473
474 struct ath11k_htt_data_stats {
475 u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM];
476 u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM];
477 u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM];
478 u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM];
479 u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM];
480 u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM];
481 u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM];
482 };
483
484 struct ath11k_htt_tx_stats {
485 struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX];
486 u64 tx_duration;
487 u64 ba_fails;
488 u64 ack_fails;
489 };
490
491 struct ath11k_per_ppdu_tx_stats {
492 u16 succ_pkts;
493 u16 failed_pkts;
494 u16 retry_pkts;
495 u32 succ_bytes;
496 u32 failed_bytes;
497 u32 retry_bytes;
498 };
499
500 DECLARE_EWMA(avg_rssi, 10, 8)
501
502 struct ath11k_sta {
503 struct ath11k_vif *arvif;
504
505 /* the following are protected by ar->data_lock */
506 u32 changed; /* IEEE80211_RC_* */
507 u32 bw;
508 u32 nss;
509 u32 smps;
510 enum hal_pn_type pn_type;
511
512 struct work_struct update_wk;
513 struct work_struct set_4addr_wk;
514 struct rate_info txrate;
515 u32 peer_nss;
516 struct rate_info last_txrate;
517 u64 rx_duration;
518 u64 tx_duration;
519 u8 rssi_comb;
520 struct ewma_avg_rssi avg_rssi;
521 s8 rssi_beacon;
522 s8 chain_signal[IEEE80211_MAX_CHAINS];
523 struct ath11k_htt_tx_stats *tx_stats;
524 struct ath11k_rx_peer_stats *rx_stats;
525
526 #ifdef CONFIG_MAC80211_DEBUGFS
527 /* protected by conf_mutex */
528 bool aggr_mode;
529 #endif
530
531 bool use_4addr_set;
532 u16 tcl_metadata;
533
534 /* Protected with ar->data_lock */
535 enum ath11k_wmi_peer_ps_state peer_ps_state;
536 u64 ps_start_time;
537 u64 ps_start_jiffies;
538 u64 ps_total_duration;
539 bool peer_current_ps_valid;
540
541 u32 bw_prev;
542 };
543
544 #define ATH11K_MIN_5G_FREQ 4150
545 #define ATH11K_MIN_6G_FREQ 5925
546 #define ATH11K_MAX_6G_FREQ 7115
547 #define ATH11K_NUM_CHANS 102
548 #define ATH11K_MAX_5G_CHAN 177
549
550 enum ath11k_state {
551 ATH11K_STATE_OFF,
552 ATH11K_STATE_ON,
553 ATH11K_STATE_RESTARTING,
554 ATH11K_STATE_RESTARTED,
555 ATH11K_STATE_WEDGED,
556 ATH11K_STATE_FTM,
557 /* Add other states as required */
558 };
559
560 /* Antenna noise floor */
561 #define ATH11K_DEFAULT_NOISE_FLOOR -95
562
563 #define ATH11K_INVALID_RSSI_FULL -1
564
565 #define ATH11K_INVALID_RSSI_EMPTY -128
566
567 struct ath11k_fw_stats {
568 struct dentry *debugfs_fwstats;
569 u32 pdev_id;
570 u32 stats_id;
571 struct list_head pdevs;
572 struct list_head vdevs;
573 struct list_head bcn;
574 };
575
576 struct ath11k_dbg_htt_stats {
577 u8 type;
578 u8 reset;
579 struct debug_htt_stats_req *stats_req;
580 /* protects shared stats req buffer */
581 spinlock_t lock;
582 };
583
584 #define MAX_MODULE_ID_BITMAP_WORDS 16
585
586 struct ath11k_debug {
587 struct dentry *debugfs_pdev;
588 struct ath11k_dbg_htt_stats htt_stats;
589 u32 extd_tx_stats;
590 u32 extd_rx_stats;
591 u32 pktlog_filter;
592 u32 pktlog_mode;
593 u32 pktlog_peer_valid;
594 u8 pktlog_peer_addr[ETH_ALEN];
595 u32 rx_filter;
596 u32 mem_offset;
597 u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS];
598 struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX];
599 };
600
601 struct ath11k_per_peer_tx_stats {
602 u32 succ_bytes;
603 u32 retry_bytes;
604 u32 failed_bytes;
605 u16 succ_pkts;
606 u16 retry_pkts;
607 u16 failed_pkts;
608 u32 duration;
609 u8 ba_fails;
610 bool is_ampdu;
611 };
612
613 #define ATH11K_FLUSH_TIMEOUT (5 * HZ)
614 #define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
615
616 struct ath11k {
617 struct ath11k_base *ab;
618 struct ath11k_pdev *pdev;
619 struct ieee80211_hw *hw;
620 struct ieee80211_ops *ops;
621 struct ath11k_pdev_wmi *wmi;
622 struct ath11k_pdev_dp dp;
623 u8 mac_addr[ETH_ALEN];
624 struct ath11k_he ar_he;
625 enum ath11k_state state;
626 bool supports_6ghz;
627 struct {
628 struct completion started;
629 struct completion completed;
630 struct completion on_channel;
631 struct delayed_work timeout;
632 enum ath11k_scan_state state;
633 bool is_roc;
634 int vdev_id;
635 int roc_freq;
636 bool roc_notify;
637 } scan;
638
639 struct {
640 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
641 struct ieee80211_sband_iftype_data
642 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
643 } mac;
644
645 unsigned long dev_flags;
646 unsigned int filter_flags;
647 unsigned long monitor_flags;
648 u32 min_tx_power;
649 u32 max_tx_power;
650 u32 txpower_limit_2g;
651 u32 txpower_limit_5g;
652 u32 txpower_scale;
653 u32 power_scale;
654 u32 chan_tx_pwr;
655 u32 num_stations;
656 u32 max_num_stations;
657 /* To synchronize concurrent synchronous mac80211 callback operations,
658 * concurrent debugfs configuration and concurrent FW statistics events.
659 */
660 struct mutex conf_mutex;
661 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
662 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info,
663 * channel context data, survey info, test mode data.
664 */
665 spinlock_t data_lock;
666
667 struct list_head arvifs;
668 /* should never be NULL; needed for regular htt rx */
669 struct ieee80211_channel *rx_channel;
670
671 /* valid during scan; needed for mgmt rx during scan */
672 struct ieee80211_channel *scan_channel;
673
674 u8 cfg_tx_chainmask;
675 u8 cfg_rx_chainmask;
676 u8 num_rx_chains;
677 u8 num_tx_chains;
678 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
679 u8 pdev_idx;
680 u8 lmac_id;
681
682 struct completion peer_assoc_done;
683 struct completion peer_delete_done;
684
685 int install_key_status;
686 struct completion install_key_done;
687
688 int last_wmi_vdev_start_status;
689 struct completion vdev_setup_done;
690 struct completion vdev_delete_done;
691
692 int num_peers;
693 int max_num_peers;
694 u32 num_started_vdevs;
695 u32 num_created_vdevs;
696 unsigned long long allocated_vdev_map;
697
698 struct idr txmgmt_idr;
699 /* protects txmgmt_idr data */
700 spinlock_t txmgmt_idr_lock;
701 atomic_t num_pending_mgmt_tx;
702 wait_queue_head_t txmgmt_empty_waitq;
703
704 /* cycle count is reported twice for each visited channel during scan.
705 * access protected by data_lock
706 */
707 u32 survey_last_rx_clear_count;
708 u32 survey_last_cycle_count;
709
710 /* Channel info events are expected to come in pairs without and with
711 * COMPLETE flag set respectively for each channel visit during scan.
712 *
713 * However there are deviations from this rule. This flag is used to
714 * avoid reporting garbage data.
715 */
716 bool ch_info_can_report_survey;
717 struct survey_info survey[ATH11K_NUM_CHANS];
718 struct completion bss_survey_done;
719
720 struct work_struct regd_update_work;
721
722 struct work_struct wmi_mgmt_tx_work;
723 struct sk_buff_head wmi_mgmt_tx_queue;
724
725 struct ath11k_wow wow;
726 struct completion target_suspend;
727 bool target_suspend_ack;
728 struct ath11k_per_peer_tx_stats peer_tx_stats;
729 struct list_head ppdu_stats_info;
730 u32 ppdu_stat_list_depth;
731
732 struct ath11k_per_peer_tx_stats cached_stats;
733 u32 last_ppdu_id;
734 u32 cached_ppdu_id;
735 int monitor_vdev_id;
736 struct completion fw_mode_reset;
737 u8 ftm_msgref;
738 #ifdef CONFIG_ATH11K_DEBUGFS
739 struct ath11k_debug debug;
740 #endif
741 #ifdef CONFIG_ATH11K_SPECTRAL
742 struct ath11k_spectral spectral;
743 #endif
744 bool dfs_block_radar_events;
745 struct ath11k_thermal thermal;
746 u32 vdev_id_11d_scan;
747 struct completion completed_11d_scan;
748 enum ath11k_11d_state state_11d;
749 bool regdom_set_by_user;
750 int hw_rate_code;
751 u8 twt_enabled;
752 bool nlo_enabled;
753 u8 alpha2[REG_ALPHA2_LEN + 1];
754 struct ath11k_fw_stats fw_stats;
755 struct completion fw_stats_complete;
756 bool fw_stats_done;
757
758 /* protected by conf_mutex */
759 bool ps_state_enable;
760 bool ps_timekeeper_enable;
761 };
762
763 struct ath11k_band_cap {
764 u32 phy_id;
765 u32 max_bw_supported;
766 u32 ht_cap_info;
767 u32 he_cap_info[2];
768 u32 he_mcs;
769 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
770 struct ath11k_ppe_threshold he_ppet;
771 u16 he_6ghz_capa;
772 };
773
774 struct ath11k_pdev_cap {
775 u32 supported_bands;
776 u32 ampdu_density;
777 u32 vht_cap;
778 u32 vht_mcs;
779 u32 he_mcs;
780 u32 tx_chain_mask;
781 u32 rx_chain_mask;
782 u32 tx_chain_mask_shift;
783 u32 rx_chain_mask_shift;
784 struct ath11k_band_cap band[NUM_NL80211_BANDS];
785 bool nss_ratio_enabled;
786 u8 nss_ratio_info;
787 };
788
789 struct ath11k_pdev {
790 struct ath11k *ar;
791 u32 pdev_id;
792 struct ath11k_pdev_cap cap;
793 u8 mac_addr[ETH_ALEN];
794 };
795
796 struct ath11k_board_data {
797 const struct firmware *fw;
798 const void *data;
799 size_t len;
800 };
801
802 struct ath11k_pci_ops {
803 int (*wakeup)(struct ath11k_base *ab);
804 void (*release)(struct ath11k_base *ab);
805 int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
806 void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
807 u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
808 };
809
810 /* IPQ8074 HW channel counters frequency value in hertz */
811 #define IPQ8074_CC_FREQ_HERTZ 320000
812
813 struct ath11k_bp_stats {
814 /* Head Pointer reported by the last HTT Backpressure event for the ring */
815 u16 hp;
816
817 /* Tail Pointer reported by the last HTT Backpressure event for the ring */
818 u16 tp;
819
820 /* Number of Backpressure events received for the ring */
821 u32 count;
822
823 /* Last recorded event timestamp */
824 unsigned long jiffies;
825 };
826
827 struct ath11k_dp_ring_bp_stats {
828 struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX];
829 struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS];
830 };
831
832 struct ath11k_soc_dp_tx_err_stats {
833 /* TCL Ring Descriptor unavailable */
834 u32 desc_na[DP_TCL_NUM_RING_MAX];
835 /* Other failures during dp_tx due to mem allocation failure
836 * idr unavailable etc.
837 */
838 atomic_t misc_fail;
839 };
840
841 struct ath11k_soc_dp_stats {
842 u32 err_ring_pkts;
843 u32 invalid_rbm;
844 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
845 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
846 u32 hal_reo_error[DP_REO_DST_RING_MAX];
847 struct ath11k_soc_dp_tx_err_stats tx_err;
848 struct ath11k_dp_ring_bp_stats bp_stats;
849 };
850
851 struct ath11k_msi_user {
852 char *name;
853 int num_vectors;
854 u32 base_vector;
855 };
856
857 struct ath11k_msi_config {
858 int total_vectors;
859 int total_users;
860 struct ath11k_msi_user *users;
861 u16 hw_rev;
862 };
863
864 /* Master structure to hold the hw data which may be used in core module */
865 struct ath11k_base {
866 enum ath11k_hw_rev hw_rev;
867 enum ath11k_firmware_mode fw_mode;
868 struct platform_device *pdev;
869 struct device *dev;
870 struct ath11k_qmi qmi;
871 struct ath11k_wmi_base wmi_ab;
872 struct completion fw_ready;
873 int num_radios;
874 /* HW channel counters frequency value in hertz common to all MACs */
875 u32 cc_freq_hz;
876
877 struct ath11k_htc htc;
878
879 struct ath11k_dp dp;
880
881 void __iomem *mem;
882 void __iomem *mem_ce;
883 unsigned long mem_len;
884
885 struct {
886 enum ath11k_bus bus;
887 const struct ath11k_hif_ops *ops;
888 } hif;
889
890 struct {
891 struct completion wakeup_completed;
892 } wow;
893
894 struct ath11k_ce ce;
895 struct timer_list rx_replenish_retry;
896 struct ath11k_hal hal;
897 /* To synchronize core_start/core_stop */
898 struct mutex core_lock;
899 /* Protects data like peers */
900 spinlock_t base_lock;
901 struct ath11k_pdev pdevs[MAX_RADIOS];
902 struct {
903 enum WMI_HOST_WLAN_BAND supported_bands;
904 u32 pdev_id;
905 } target_pdev_ids[MAX_RADIOS];
906 u8 target_pdev_count;
907 struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
908 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
909 unsigned long long free_vdev_map;
910
911 /* To synchronize rhash tbl write operation */
912 struct mutex tbl_mtx_lock;
913
914 /* The rhashtable containing struct ath11k_peer keyed by mac addr */
915 struct rhashtable *rhead_peer_addr;
916 struct rhashtable_params rhash_peer_addr_param;
917
918 /* The rhashtable containing struct ath11k_peer keyed by id */
919 struct rhashtable *rhead_peer_id;
920 struct rhashtable_params rhash_peer_id_param;
921
922 struct list_head peers;
923 wait_queue_head_t peer_mapping_wq;
924 u8 mac_addr[ETH_ALEN];
925 bool wmi_ready;
926 u32 wlan_init_status;
927 int irq_num[ATH11K_IRQ_NUM_MAX];
928 struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
929 struct ath11k_targ_cap target_caps;
930 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
931 bool pdevs_macaddr_valid;
932 int bd_api;
933
934 struct ath11k_hw_params hw_params;
935
936 const struct firmware *cal_file;
937
938 /* Below regd's are protected by ab->data_lock */
939 /* This is the regd set for every radio
940 * by the firmware during initialization
941 */
942 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
943 /* This regd is set during dynamic country setting
944 * This may or may not be used during the runtime
945 */
946 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
947
948 /* Current DFS Regulatory */
949 enum ath11k_dfs_region dfs_region;
950 #ifdef CONFIG_ATH11K_DEBUGFS
951 struct dentry *debugfs_soc;
952 #endif
953 struct ath11k_soc_dp_stats soc_stats;
954
955 unsigned long dev_flags;
956 struct completion driver_recovery;
957 struct workqueue_struct *workqueue;
958 struct work_struct restart_work;
959 struct work_struct update_11d_work;
960 u8 new_alpha2[3];
961 struct workqueue_struct *workqueue_aux;
962 struct work_struct reset_work;
963 atomic_t reset_count;
964 atomic_t recovery_count;
965 atomic_t recovery_start_count;
966 bool is_reset;
967 struct completion reset_complete;
968 struct completion reconfigure_complete;
969 struct completion recovery_start;
970 /* continuous recovery fail count */
971 atomic_t fail_cont_count;
972 unsigned long reset_fail_timeout;
973 struct {
974 /* protected by data_lock */
975 u32 fw_crash_counter;
976 } stats;
977 u32 pktlog_defs_checksum;
978
979 struct ath11k_dbring_cap *db_caps;
980 u32 num_db_cap;
981
982 /* To synchronize 11d scan vdev id */
983 struct mutex vdev_id_11d_lock;
984 struct timer_list mon_reap_timer;
985
986 struct completion htc_suspend;
987
988 struct {
989 enum ath11k_bdf_search bdf_search;
990 u32 vendor;
991 u32 device;
992 u32 subsystem_vendor;
993 u32 subsystem_device;
994 } id;
995
996 struct {
997 struct {
998 const struct ath11k_msi_config *config;
999 u32 ep_base_data;
1000 u32 irqs[32];
1001 u32 addr_lo;
1002 u32 addr_hi;
1003 } msi;
1004
1005 const struct ath11k_pci_ops *ops;
1006 } pci;
1007
1008 #ifdef CONFIG_NL80211_TESTMODE
1009 struct {
1010 u32 data_pos;
1011 u32 expected_seq;
1012 u8 *eventdata;
1013 } testmode;
1014 #endif
1015
1016 /* must be last */
1017 u8 drv_priv[] __aligned(sizeof(void *));
1018 };
1019
1020 struct ath11k_fw_stats_pdev {
1021 struct list_head list;
1022
1023 /* PDEV stats */
1024 s32 ch_noise_floor;
1025 /* Cycles spent transmitting frames */
1026 u32 tx_frame_count;
1027 /* Cycles spent receiving frames */
1028 u32 rx_frame_count;
1029 /* Total channel busy time, evidently */
1030 u32 rx_clear_count;
1031 /* Total on-channel time */
1032 u32 cycle_count;
1033 u32 phy_err_count;
1034 u32 chan_tx_power;
1035 u32 ack_rx_bad;
1036 u32 rts_bad;
1037 u32 rts_good;
1038 u32 fcs_bad;
1039 u32 no_beacons;
1040 u32 mib_int_count;
1041
1042 /* PDEV TX stats */
1043 /* Num HTT cookies queued to dispatch list */
1044 s32 comp_queued;
1045 /* Num HTT cookies dispatched */
1046 s32 comp_delivered;
1047 /* Num MSDU queued to WAL */
1048 s32 msdu_enqued;
1049 /* Num MPDU queue to WAL */
1050 s32 mpdu_enqued;
1051 /* Num MSDUs dropped by WMM limit */
1052 s32 wmm_drop;
1053 /* Num Local frames queued */
1054 s32 local_enqued;
1055 /* Num Local frames done */
1056 s32 local_freed;
1057 /* Num queued to HW */
1058 s32 hw_queued;
1059 /* Num PPDU reaped from HW */
1060 s32 hw_reaped;
1061 /* Num underruns */
1062 s32 underrun;
1063 /* Num hw paused */
1064 u32 hw_paused;
1065 /* Num PPDUs cleaned up in TX abort */
1066 s32 tx_abort;
1067 /* Num MPDUs requeued by SW */
1068 s32 mpdus_requeued;
1069 /* excessive retries */
1070 u32 tx_ko;
1071 u32 tx_xretry;
1072 /* data hw rate code */
1073 u32 data_rc;
1074 /* Scheduler self triggers */
1075 u32 self_triggers;
1076 /* frames dropped due to excessive sw retries */
1077 u32 sw_retry_failure;
1078 /* illegal rate phy errors */
1079 u32 illgl_rate_phy_err;
1080 /* wal pdev continuous xretry */
1081 u32 pdev_cont_xretry;
1082 /* wal pdev tx timeouts */
1083 u32 pdev_tx_timeout;
1084 /* wal pdev resets */
1085 u32 pdev_resets;
1086 /* frames dropped due to non-availability of stateless TIDs */
1087 u32 stateless_tid_alloc_failure;
1088 /* PhY/BB underrun */
1089 u32 phy_underrun;
1090 /* MPDU is more than txop limit */
1091 u32 txop_ovf;
1092 /* Num sequences posted */
1093 u32 seq_posted;
1094 /* Num sequences failed in queueing */
1095 u32 seq_failed_queueing;
1096 /* Num sequences completed */
1097 u32 seq_completed;
1098 /* Num sequences restarted */
1099 u32 seq_restarted;
1100 /* Num of MU sequences posted */
1101 u32 mu_seq_posted;
1102 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
1103 * (Reset,channel change)
1104 */
1105 s32 mpdus_sw_flush;
1106 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */
1107 s32 mpdus_hw_filter;
1108 /* Num MPDUs truncated by PDG (TXOP, TBTT,
1109 * PPDU_duration based on rate, dyn_bw)
1110 */
1111 s32 mpdus_truncated;
1112 /* Num MPDUs that was tried but didn't receive ACK or BA */
1113 s32 mpdus_ack_failed;
1114 /* Num MPDUs that was dropped du to expiry. */
1115 s32 mpdus_expired;
1116
1117 /* PDEV RX stats */
1118 /* Cnts any change in ring routing mid-ppdu */
1119 s32 mid_ppdu_route_change;
1120 /* Total number of statuses processed */
1121 s32 status_rcvd;
1122 /* Extra frags on rings 0-3 */
1123 s32 r0_frags;
1124 s32 r1_frags;
1125 s32 r2_frags;
1126 s32 r3_frags;
1127 /* MSDUs / MPDUs delivered to HTT */
1128 s32 htt_msdus;
1129 s32 htt_mpdus;
1130 /* MSDUs / MPDUs delivered to local stack */
1131 s32 loc_msdus;
1132 s32 loc_mpdus;
1133 /* AMSDUs that have more MSDUs than the status ring size */
1134 s32 oversize_amsdu;
1135 /* Number of PHY errors */
1136 s32 phy_errs;
1137 /* Number of PHY errors drops */
1138 s32 phy_err_drop;
1139 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1140 s32 mpdu_errs;
1141 /* Num overflow errors */
1142 s32 rx_ovfl_errs;
1143 };
1144
1145 struct ath11k_fw_stats_vdev {
1146 struct list_head list;
1147
1148 u32 vdev_id;
1149 u32 beacon_snr;
1150 u32 data_snr;
1151 u32 num_tx_frames[WLAN_MAX_AC];
1152 u32 num_rx_frames;
1153 u32 num_tx_frames_retries[WLAN_MAX_AC];
1154 u32 num_tx_frames_failures[WLAN_MAX_AC];
1155 u32 num_rts_fail;
1156 u32 num_rts_success;
1157 u32 num_rx_err;
1158 u32 num_rx_discard;
1159 u32 num_tx_not_acked;
1160 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1161 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1162 };
1163
1164 struct ath11k_fw_stats_bcn {
1165 struct list_head list;
1166
1167 u32 vdev_id;
1168 u32 tx_bcn_succ_cnt;
1169 u32 tx_bcn_outage_cnt;
1170 };
1171
1172 void ath11k_fw_stats_init(struct ath11k *ar);
1173 void ath11k_fw_stats_pdevs_free(struct list_head *head);
1174 void ath11k_fw_stats_vdevs_free(struct list_head *head);
1175 void ath11k_fw_stats_bcn_free(struct list_head *head);
1176 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats);
1177
1178 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[];
1179 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[];
1180 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[];
1181
1182 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[];
1183 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[];
1184
1185 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[];
1186 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[];
1187
1188 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[];
1189 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[];
1190 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
1191 int ath11k_core_pre_init(struct ath11k_base *ab);
1192 int ath11k_core_init(struct ath11k_base *ath11k);
1193 void ath11k_core_deinit(struct ath11k_base *ath11k);
1194 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
1195 enum ath11k_bus bus);
1196 void ath11k_core_free(struct ath11k_base *ath11k);
1197 int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
1198 struct ath11k_board_data *bd);
1199 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd);
1200 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1201 struct ath11k_board_data *bd,
1202 const char *name);
1203 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
1204 int ath11k_core_check_dt(struct ath11k_base *ath11k);
1205 int ath11k_core_check_smbios(struct ath11k_base *ab);
1206 void ath11k_core_halt(struct ath11k *ar);
1207 int ath11k_core_resume(struct ath11k_base *ab);
1208 int ath11k_core_suspend(struct ath11k_base *ab);
1209 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab);
1210 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab);
1211
1212 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1213 const char *filename);
1214
ath11k_scan_state_str(enum ath11k_scan_state state)1215 static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state)
1216 {
1217 switch (state) {
1218 case ATH11K_SCAN_IDLE:
1219 return "idle";
1220 case ATH11K_SCAN_STARTING:
1221 return "starting";
1222 case ATH11K_SCAN_RUNNING:
1223 return "running";
1224 case ATH11K_SCAN_ABORTING:
1225 return "aborting";
1226 }
1227
1228 return "unknown";
1229 }
1230
ATH11K_SKB_CB(struct sk_buff * skb)1231 static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb)
1232 {
1233 BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) >
1234 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1235 return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1236 }
1237
ATH11K_SKB_RXCB(struct sk_buff * skb)1238 static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb)
1239 {
1240 BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb));
1241 return (struct ath11k_skb_rxcb *)skb->cb;
1242 }
1243
ath11k_vif_to_arvif(struct ieee80211_vif * vif)1244 static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif)
1245 {
1246 return (struct ath11k_vif *)vif->drv_priv;
1247 }
1248
ath11k_ab_to_ar(struct ath11k_base * ab,int mac_id)1249 static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab,
1250 int mac_id)
1251 {
1252 return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
1253 }
1254
ath11k_core_create_firmware_path(struct ath11k_base * ab,const char * filename,void * buf,size_t buf_len)1255 static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab,
1256 const char *filename,
1257 void *buf, size_t buf_len)
1258 {
1259 snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR,
1260 ab->hw_params.fw.dir, filename);
1261 }
1262
ath11k_bus_str(enum ath11k_bus bus)1263 static inline const char *ath11k_bus_str(enum ath11k_bus bus)
1264 {
1265 switch (bus) {
1266 case ATH11K_BUS_PCI:
1267 return "pci";
1268 case ATH11K_BUS_AHB:
1269 return "ahb";
1270 }
1271
1272 return "unknown";
1273 }
1274
1275 #endif /* _CORE_H_ */
1276