xref: /linux/drivers/crypto/aspeed/aspeed-hace.h (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 #ifndef __ASPEED_HACE_H__
3 #define __ASPEED_HACE_H__
4 
5 #include <crypto/aes.h>
6 #include <crypto/engine.h>
7 #include <crypto/hash.h>
8 #include <crypto/sha2.h>
9 #include <linux/bits.h>
10 #include <linux/compiler_attributes.h>
11 #include <linux/interrupt.h>
12 #include <linux/types.h>
13 
14 /*****************************
15  *                           *
16  * HACE register definitions *
17  *                           *
18  * ***************************/
19 #define ASPEED_HACE_SRC			0x00	/* Crypto Data Source Base Address Register */
20 #define ASPEED_HACE_DEST		0x04	/* Crypto Data Destination Base Address Register */
21 #define ASPEED_HACE_CONTEXT		0x08	/* Crypto Context Buffer Base Address Register */
22 #define ASPEED_HACE_DATA_LEN		0x0C	/* Crypto Data Length Register */
23 #define ASPEED_HACE_CMD			0x10	/* Crypto Engine Command Register */
24 
25 /* G5 */
26 #define ASPEED_HACE_TAG			0x18	/* HACE Tag Register */
27 /* G6 */
28 #define ASPEED_HACE_GCM_ADD_LEN		0x14	/* Crypto AES-GCM Additional Data Length Register */
29 #define ASPEED_HACE_GCM_TAG_BASE_ADDR	0x18	/* Crypto AES-GCM Tag Write Buff Base Address Reg */
30 
31 #define ASPEED_HACE_STS			0x1C	/* HACE Status Register */
32 
33 #define ASPEED_HACE_HASH_SRC		0x20	/* Hash Data Source Base Address Register */
34 #define ASPEED_HACE_HASH_DIGEST_BUFF	0x24	/* Hash Digest Write Buffer Base Address Register */
35 #define ASPEED_HACE_HASH_KEY_BUFF	0x28	/* Hash HMAC Key Buffer Base Address Register */
36 #define ASPEED_HACE_HASH_DATA_LEN	0x2C	/* Hash Data Length Register */
37 #define ASPEED_HACE_HASH_CMD		0x30	/* Hash Engine Command Register */
38 
39 /* crypto cmd */
40 #define  HACE_CMD_SINGLE_DES		0
41 #define  HACE_CMD_TRIPLE_DES		BIT(17)
42 #define  HACE_CMD_AES_SELECT		0
43 #define  HACE_CMD_DES_SELECT		BIT(16)
44 #define  HACE_CMD_ISR_EN		BIT(12)
45 #define  HACE_CMD_CONTEXT_SAVE_ENABLE	(0)
46 #define  HACE_CMD_CONTEXT_SAVE_DISABLE	BIT(9)
47 #define  HACE_CMD_AES			(0)
48 #define  HACE_CMD_DES			(0)
49 #define  HACE_CMD_RC4			BIT(8)
50 #define  HACE_CMD_DECRYPT		(0)
51 #define  HACE_CMD_ENCRYPT		BIT(7)
52 
53 #define  HACE_CMD_ECB			(0x0 << 4)
54 #define  HACE_CMD_CBC			(0x1 << 4)
55 #define  HACE_CMD_CFB			(0x2 << 4)
56 #define  HACE_CMD_OFB			(0x3 << 4)
57 #define  HACE_CMD_CTR			(0x4 << 4)
58 #define  HACE_CMD_OP_MODE_MASK		(0x7 << 4)
59 
60 #define  HACE_CMD_AES128		(0x0 << 2)
61 #define  HACE_CMD_AES192		(0x1 << 2)
62 #define  HACE_CMD_AES256		(0x2 << 2)
63 #define  HACE_CMD_OP_CASCADE		(0x3)
64 #define  HACE_CMD_OP_INDEPENDENT	(0x1)
65 
66 /* G5 */
67 #define  HACE_CMD_RI_WO_DATA_ENABLE	(0)
68 #define  HACE_CMD_RI_WO_DATA_DISABLE	BIT(11)
69 #define  HACE_CMD_CONTEXT_LOAD_ENABLE	(0)
70 #define  HACE_CMD_CONTEXT_LOAD_DISABLE	BIT(10)
71 /* G6 */
72 #define  HACE_CMD_AES_KEY_FROM_OTP	BIT(24)
73 #define  HACE_CMD_GHASH_TAG_XOR_EN	BIT(23)
74 #define  HACE_CMD_GHASH_PAD_LEN_INV	BIT(22)
75 #define  HACE_CMD_GCM_TAG_ADDR_SEL	BIT(21)
76 #define  HACE_CMD_MBUS_REQ_SYNC_EN	BIT(20)
77 #define  HACE_CMD_DES_SG_CTRL		BIT(19)
78 #define  HACE_CMD_SRC_SG_CTRL		BIT(18)
79 #define  HACE_CMD_CTR_IV_AES_96		(0x1 << 14)
80 #define  HACE_CMD_CTR_IV_DES_32		(0x1 << 14)
81 #define  HACE_CMD_CTR_IV_AES_64		(0x2 << 14)
82 #define  HACE_CMD_CTR_IV_AES_32		(0x3 << 14)
83 #define  HACE_CMD_AES_KEY_HW_EXP	BIT(13)
84 #define  HACE_CMD_GCM			(0x5 << 4)
85 
86 /* interrupt status reg */
87 #define  HACE_CRYPTO_ISR		BIT(12)
88 #define  HACE_HASH_ISR			BIT(9)
89 #define  HACE_HASH_BUSY			BIT(0)
90 
91 /* hash cmd reg */
92 #define  HASH_CMD_MBUS_REQ_SYNC_EN	BIT(20)
93 #define  HASH_CMD_HASH_SRC_SG_CTRL	BIT(18)
94 #define  HASH_CMD_SHA512_224		(0x3 << 10)
95 #define  HASH_CMD_SHA512_256		(0x2 << 10)
96 #define  HASH_CMD_SHA384		(0x1 << 10)
97 #define  HASH_CMD_SHA512		(0)
98 #define  HASH_CMD_INT_ENABLE		BIT(9)
99 #define  HASH_CMD_HMAC			(0x1 << 7)
100 #define  HASH_CMD_ACC_MODE		(0x2 << 7)
101 #define  HASH_CMD_HMAC_KEY		(0x3 << 7)
102 #define  HASH_CMD_SHA1			(0x2 << 4)
103 #define  HASH_CMD_SHA224		(0x4 << 4)
104 #define  HASH_CMD_SHA256		(0x5 << 4)
105 #define  HASH_CMD_SHA512_SER		(0x6 << 4)
106 #define  HASH_CMD_SHA_SWAP		(0x2 << 2)
107 
108 #define HASH_SG_LAST_LIST		BIT(31)
109 
110 #define CRYPTO_FLAGS_BUSY		BIT(1)
111 
112 #define SHA_OP_UPDATE			1
113 #define SHA_OP_FINAL			2
114 
115 #define SHA_FLAGS_SHA1			BIT(0)
116 #define SHA_FLAGS_SHA224		BIT(1)
117 #define SHA_FLAGS_SHA256		BIT(2)
118 #define SHA_FLAGS_SHA384		BIT(3)
119 #define SHA_FLAGS_SHA512		BIT(4)
120 #define SHA_FLAGS_SHA512_224		BIT(5)
121 #define SHA_FLAGS_SHA512_256		BIT(6)
122 #define SHA_FLAGS_HMAC			BIT(8)
123 #define SHA_FLAGS_FINUP			BIT(9)
124 #define SHA_FLAGS_MASK			(0xff)
125 
126 #define ASPEED_CRYPTO_SRC_DMA_BUF_LEN	0xa000
127 #define ASPEED_CRYPTO_DST_DMA_BUF_LEN	0xa000
128 #define ASPEED_CRYPTO_GCM_TAG_OFFSET	0x9ff0
129 #define ASPEED_HASH_SRC_DMA_BUF_LEN	0xa000
130 #define ASPEED_HASH_QUEUE_LENGTH	50
131 
132 #define HACE_CMD_IV_REQUIRE		(HACE_CMD_CBC | HACE_CMD_CFB | \
133 					 HACE_CMD_OFB | HACE_CMD_CTR)
134 
135 struct aspeed_hace_dev;
136 struct scatterlist;
137 
138 typedef int (*aspeed_hace_fn_t)(struct aspeed_hace_dev *);
139 
140 struct aspeed_sg_list {
141 	__le32 len;
142 	__le32 phy_addr;
143 };
144 
145 struct aspeed_engine_hash {
146 	struct tasklet_struct		done_task;
147 	unsigned long			flags;
148 	struct ahash_request		*req;
149 
150 	/* input buffer */
151 	void				*ahash_src_addr;
152 	dma_addr_t			ahash_src_dma_addr;
153 
154 	dma_addr_t			src_dma;
155 	dma_addr_t			digest_dma;
156 
157 	size_t				src_length;
158 
159 	/* callback func */
160 	aspeed_hace_fn_t		resume;
161 	aspeed_hace_fn_t		dma_prepare;
162 };
163 
164 struct aspeed_sha_hmac_ctx {
165 	struct crypto_shash *shash;
166 	u8 ipad[SHA512_BLOCK_SIZE];
167 	u8 opad[SHA512_BLOCK_SIZE];
168 };
169 
170 struct aspeed_sham_ctx {
171 	struct aspeed_hace_dev		*hace_dev;
172 	unsigned long			flags;	/* hmac flag */
173 
174 	struct aspeed_sha_hmac_ctx	base[];
175 };
176 
177 struct aspeed_sham_reqctx {
178 	unsigned long		flags;		/* final update flag should no use*/
179 	unsigned long		op;		/* final or update */
180 	u32			cmd;		/* trigger cmd */
181 
182 	/* walk state */
183 	struct scatterlist	*src_sg;
184 	int			src_nents;
185 	unsigned int		offset;		/* offset in current sg */
186 	unsigned int		total;		/* per update length */
187 
188 	size_t			digsize;
189 	size_t			block_size;
190 	size_t			ivsize;
191 	const __be32		*sha_iv;
192 
193 	/* remain data buffer */
194 	u8			buffer[SHA512_BLOCK_SIZE * 2];
195 	dma_addr_t		buffer_dma_addr;
196 	size_t			bufcnt;		/* buffer counter */
197 
198 	/* output buffer */
199 	u8			digest[SHA512_DIGEST_SIZE] __aligned(64);
200 	dma_addr_t		digest_dma_addr;
201 	u64			digcnt[2];
202 };
203 
204 struct aspeed_engine_crypto {
205 	struct tasklet_struct		done_task;
206 	unsigned long			flags;
207 	struct skcipher_request		*req;
208 
209 	/* context buffer */
210 	void				*cipher_ctx;
211 	dma_addr_t			cipher_ctx_dma;
212 
213 	/* input buffer, could be single/scatter-gather lists */
214 	void				*cipher_addr;
215 	dma_addr_t			cipher_dma_addr;
216 
217 	/* output buffer, only used in scatter-gather lists */
218 	void				*dst_sg_addr;
219 	dma_addr_t			dst_sg_dma_addr;
220 
221 	/* callback func */
222 	aspeed_hace_fn_t		resume;
223 };
224 
225 struct aspeed_cipher_ctx {
226 	struct aspeed_hace_dev		*hace_dev;
227 	int				key_len;
228 	u8				key[AES_MAX_KEYLENGTH];
229 
230 	/* callback func */
231 	aspeed_hace_fn_t		start;
232 
233 	struct crypto_skcipher          *fallback_tfm;
234 };
235 
236 struct aspeed_cipher_reqctx {
237 	int enc_cmd;
238 	int src_nents;
239 	int dst_nents;
240 
241 	struct skcipher_request         fallback_req;   /* keep at the end */
242 };
243 
244 struct aspeed_hace_dev {
245 	void __iomem			*regs;
246 	struct device			*dev;
247 	int				irq;
248 	struct clk			*clk;
249 	unsigned long			version;
250 
251 	struct crypto_engine		*crypt_engine_hash;
252 	struct crypto_engine		*crypt_engine_crypto;
253 
254 	struct aspeed_engine_hash	hash_engine;
255 	struct aspeed_engine_crypto	crypto_engine;
256 };
257 
258 struct aspeed_hace_alg {
259 	struct aspeed_hace_dev		*hace_dev;
260 
261 	const char			*alg_base;
262 
263 	union {
264 		struct skcipher_engine_alg skcipher;
265 		struct ahash_engine_alg ahash;
266 	} alg;
267 };
268 
269 enum aspeed_version {
270 	AST2500_VERSION = 5,
271 	AST2600_VERSION
272 };
273 
274 #define ast_hace_write(hace, val, offset)	\
275 	writel((val), (hace)->regs + (offset))
276 #define ast_hace_read(hace, offset)		\
277 	readl((hace)->regs + (offset))
278 
279 void aspeed_register_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
280 void aspeed_unregister_hace_hash_algs(struct aspeed_hace_dev *hace_dev);
281 void aspeed_register_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
282 void aspeed_unregister_hace_crypto_algs(struct aspeed_hace_dev *hace_dev);
283 
284 #endif
285