xref: /titanic_41/usr/src/uts/common/io/arn/arn_phy.h (revision dd1de3740722a4b99a74005255effebbd20a6d70)
1 /*
2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2008 Atheros Communications Inc.
8  *
9  * Permission to use, copy, modify, and/or distribute this software for any
10  * purpose with or without fee is hereby granted, provided that the above
11  * copyright notice and this permission notice appear in all copies.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20  */
21 
22 #ifndef	_ARN_PHY_H
23 #define	_ARN_PHY_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 boolean_t ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
30     struct ath9k_channel *chan);
31 boolean_t ath9k_hw_set_channel(struct ath_hal *ah,
32     struct ath9k_channel *chan);
33 void ath9k_hw_write_regs(struct ath_hal *ah, uint32_t modesIndex,
34     uint32_t freqIndex, int regWrites);
35 boolean_t ath9k_hw_set_rf_regs(struct ath_hal *ah,
36     struct ath9k_channel *chan, uint16_t modesIndex);
37 void ath9k_hw_decrease_chain_power(struct ath_hal *ah,
38     struct ath9k_channel *chan);
39 boolean_t ath9k_hw_init_rf(struct ath_hal *ah, int *status);
40 
41 #define	AR_PHY_BASE	0x9800
42 #define	AR_PHY(_n)	(AR_PHY_BASE + ((_n)<<2))
43 
44 #define	AR_PHY_TEST	0x9800
45 #define	PHY_AGC_CLR	0x10000000
46 #define	RFSILENT_BB	0x00002000
47 
48 #define	AR_PHY_TURBO			0x9804
49 #define	AR_PHY_FC_TURBO_MODE		0x00000001
50 #define	AR_PHY_FC_TURBO_SHORT		0x00000002
51 #define	AR_PHY_FC_DYN2040_EN		0x00000004
52 #define	AR_PHY_FC_DYN2040_PRI_ONLY	0x00000008
53 #define	AR_PHY_FC_DYN2040_PRI_CH	0x00000010
54 #define	AR_PHY_FC_DYN2040_EXT_CH	0x00000020
55 #define	AR_PHY_FC_HT_EN			0x00000040
56 #define	AR_PHY_FC_SHORT_GI_40		0x00000080
57 #define	AR_PHY_FC_WALSH			0x00000100
58 #define	AR_PHY_FC_SINGLE_HT_LTF1	0x00000200
59 #define	AR_PHY_FC_ENABLE_DAC_FIFO	0x00000800
60 #define	AR_PHY_TEST2	0x9808
61 
62 #define	AR_PHY_TIMING2			0x9810
63 #define	AR_PHY_TIMING3			0x9814
64 #define	AR_PHY_TIMING3_DSC_MAN		0xFFFE0000
65 #define	AR_PHY_TIMING3_DSC_MAN_S	17
66 #define	AR_PHY_TIMING3_DSC_EXP		0x0001E000
67 #define	AR_PHY_TIMING3_DSC_EXP_S	13
68 
69 #define	AR_PHY_CHIP_ID			0x9818
70 #define	AR_PHY_CHIP_ID_REV_0		0x80
71 #define	AR_PHY_CHIP_ID_REV_1		0x81
72 #define	AR_PHY_CHIP_ID_9160_REV_0	0xb0
73 
74 #define	AR_PHY_ACTIVE			0x981C
75 #define	AR_PHY_ACTIVE_EN		0x00000001
76 #define	AR_PHY_ACTIVE_DIS		0x00000000
77 
78 #define	AR_PHY_RF_CTL2			0x9824
79 #define	AR_PHY_TX_END_DATA_START	0x000000FF
80 #define	AR_PHY_TX_END_DATA_START_S	0
81 #define	AR_PHY_TX_END_PA_ON		0x0000FF00
82 #define	AR_PHY_TX_END_PA_ON_S		8
83 
84 #define	AR_PHY_RF_CTL3			0x9828
85 #define	AR_PHY_TX_END_TO_A2_RX_ON	0x00FF0000
86 #define	AR_PHY_TX_END_TO_A2_RX_ON_S	16
87 
88 #define	AR_PHY_ADC_CTL			0x982C
89 #define	AR_PHY_ADC_CTL_OFF_INBUFGAIN	0x00000003
90 #define	AR_PHY_ADC_CTL_OFF_INBUFGAIN_S	0
91 #define	AR_PHY_ADC_CTL_OFF_PWDDAC	0x00002000
92 #define	AR_PHY_ADC_CTL_OFF_PWDBANDGAP	0x00004000
93 #define	AR_PHY_ADC_CTL_OFF_PWDADC	0x00008000
94 #define	AR_PHY_ADC_CTL_ON_INBUFGAIN	0x00030000
95 #define	AR_PHY_ADC_CTL_ON_INBUFGAIN_S	16
96 
97 #define	AR_PHY_ADC_SERIAL_CTL		0x9830
98 #define	AR_PHY_SEL_INTERNAL_ADDAC	0x00000000
99 #define	AR_PHY_SEL_EXTERNAL_RADIO	0x00000001
100 
101 #define	AR_PHY_RF_CTL4				0x9834
102 #define	AR_PHY_RF_CTL4_TX_END_XPAB_OFF		0xFF000000
103 #define	AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S	24
104 #define	AR_PHY_RF_CTL4_TX_END_XPAA_OFF		0x00FF0000
105 #define	AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S	16
106 #define	AR_PHY_RF_CTL4_FRAME_XPAB_ON		0x0000FF00
107 #define	AR_PHY_RF_CTL4_FRAME_XPAB_ON_S		8
108 #define	AR_PHY_RF_CTL4_FRAME_XPAA_ON		0x000000FF
109 #define	AR_PHY_RF_CTL4_FRAME_XPAA_ON_S		0
110 #define	AR_PHY_TSTDAC_CONST	0x983c
111 
112 #define	AR_PHY_SETTLING			0x9844
113 #define	AR_PHY_SETTLING_SWITCH		0x00003F80
114 #define	AR_PHY_SETTLING_SWITCH_S	7
115 
116 #define	AR_PHY_RXGAIN			0x9848
117 #define	AR_PHY_RXGAIN_TXRX_ATTEN	0x0003F000
118 #define	AR_PHY_RXGAIN_TXRX_ATTEN_S	12
119 #define	AR_PHY_RXGAIN_TXRX_RF_MAX	0x007C0000
120 #define	AR_PHY_RXGAIN_TXRX_RF_MAX_S	18
121 #define	AR9280_PHY_RXGAIN_TXRX_ATTEN	0x00003F80
122 #define	AR9280_PHY_RXGAIN_TXRX_ATTEN_S	7
123 #define	AR9280_PHY_RXGAIN_TXRX_MARGIN	0x001FC000
124 #define	AR9280_PHY_RXGAIN_TXRX_MARGIN_S	14
125 
126 #define	AR_PHY_DESIRED_SZ		0x9850
127 #define	AR_PHY_DESIRED_SZ_ADC		0x000000FF
128 #define	AR_PHY_DESIRED_SZ_ADC_S		0
129 #define	AR_PHY_DESIRED_SZ_PGA		0x0000FF00
130 #define	AR_PHY_DESIRED_SZ_PGA_S		8
131 #define	AR_PHY_DESIRED_SZ_TOT_DES	0x0FF00000
132 #define	AR_PHY_DESIRED_SZ_TOT_DES_S	20
133 
134 #define	AR_PHY_FIND_SIG			0x9858
135 #define	AR_PHY_FIND_SIG_FIRSTEP		0x0003F000
136 #define	AR_PHY_FIND_SIG_FIRSTEP_S	12
137 #define	AR_PHY_FIND_SIG_FIRPWR		0x03FC0000
138 #define	AR_PHY_FIND_SIG_FIRPWR_S	18
139 
140 #define	AR_PHY_AGC_CTL1			0x985C
141 #define	AR_PHY_AGC_CTL1_COARSE_LOW	0x00007F80
142 #define	AR_PHY_AGC_CTL1_COARSE_LOW_S	7
143 #define	AR_PHY_AGC_CTL1_COARSE_HIGH	0x003F8000
144 #define	AR_PHY_AGC_CTL1_COARSE_HIGH_S	15
145 
146 #define	AR_PHY_AGC_CONTROL		0x9860
147 #define	AR_PHY_AGC_CONTROL_CAL		0x00000001
148 #define	AR_PHY_AGC_CONTROL_NF		0x00000002
149 #define	AR_PHY_AGC_CONTROL_ENABLE_NF	0x00008000
150 #define	AR_PHY_AGC_CONTROL_FLTR_CAL	0x00010000
151 #define	AR_PHY_AGC_CONTROL_NO_UPDATE_NF	0x00020000
152 
153 #define	AR_PHY_CCA			0x9864
154 #define	AR_PHY_MINCCA_PWR		0x0FF80000
155 #define	AR_PHY_MINCCA_PWR_S		19
156 #define	AR_PHY_CCA_THRESH62		0x0007F000
157 #define	AR_PHY_CCA_THRESH62_S		12
158 #define	AR9280_PHY_MINCCA_PWR		0x1FF00000
159 #define	AR9280_PHY_MINCCA_PWR_S		20
160 #define	AR9280_PHY_CCA_THRESH62		0x000FF000
161 #define	AR9280_PHY_CCA_THRESH62_S	12
162 
163 #define	AR_PHY_SFCORR_LOW			0x986C
164 #define	AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW	0x00000001
165 #define	AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW	0x00003F00
166 #define	AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S	8
167 #define	AR_PHY_SFCORR_LOW_M1_THRESH_LOW		0x001FC000
168 #define	AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S	14
169 #define	AR_PHY_SFCORR_LOW_M2_THRESH_LOW		0x0FE00000
170 #define	AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S	21
171 
172 #define	AR_PHY_SFCORR			0x9868
173 #define	AR_PHY_SFCORR_M2COUNT_THR	0x0000001F
174 #define	AR_PHY_SFCORR_M2COUNT_THR_S	0
175 #define	AR_PHY_SFCORR_M1_THRESH		0x00FE0000
176 #define	AR_PHY_SFCORR_M1_THRESH_S	17
177 #define	AR_PHY_SFCORR_M2_THRESH		0x7F000000
178 #define	AR_PHY_SFCORR_M2_THRESH_S	24
179 
180 #define	AR_PHY_SLEEP_CTR_CONTROL	0x9870
181 #define	AR_PHY_SLEEP_CTR_LIMIT		0x9874
182 #define	AR_PHY_SYNTH_CONTROL		0x9874
183 #define	AR_PHY_SLEEP_SCAL		0x9878
184 
185 #define	AR_PHY_PLL_CTL			0x987c
186 #define	AR_PHY_PLL_CTL_40		0xaa
187 #define	AR_PHY_PLL_CTL_40_5413		0x04
188 #define	AR_PHY_PLL_CTL_44		0xab
189 #define	AR_PHY_PLL_CTL_44_2133		0xeb
190 #define	AR_PHY_PLL_CTL_40_2133		0xea
191 
192 #define	AR_PHY_RX_DELAY			0x9914
193 #define	AR_PHY_SEARCH_START_DELAY	0x9918
194 #define	AR_PHY_RX_DELAY_DELAY		0x00003FFF
195 
196 #define	AR_PHY_TIMING_CTRL4(_i)	(0x9920 + ((_i) << 12))
197 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF		0x01F
198 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S		0
199 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF		0x7E0
200 #define	AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S		5
201 #define	AR_PHY_TIMING_CTRL4_IQCORR_ENABLE		0x800
202 #define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX		0xF000
203 #define	AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12
204 #define	AR_PHY_TIMING_CTRL4_DO_CAL			0x10000
205 
206 #define	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI	0x80000000
207 #define	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER	0x40000000
208 #define	AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK	0x20000000
209 #define	AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK	0x10000000
210 
211 #define	AR_PHY_TIMING5			0x9924
212 #define	AR_PHY_TIMING5_CYCPWR_THR1	0x000000FE
213 #define	AR_PHY_TIMING5_CYCPWR_THR1_S	1
214 
215 #define	AR_PHY_POWER_TX_RATE1			0x9934
216 #define	AR_PHY_POWER_TX_RATE2			0x9938
217 #define	AR_PHY_POWER_TX_RATE_MAX		0x993c
218 #define	AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE	0x00000040
219 
220 #define	AR_PHY_FRAME_CTL		0x9944
221 #define	AR_PHY_FRAME_CTL_TX_CLIP	0x00000038
222 #define	AR_PHY_FRAME_CTL_TX_CLIP_S	3
223 
224 #define	AR_PHY_TXPWRADJ				0x994C
225 #define	AR_PHY_TXPWRADJ_CCK_GAIN_DELTA		0x00000FC0
226 #define	AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S  	6
227 #define	AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX		0x00FC0000
228 #define	AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S	18
229 
230 #define	AR_PHY_RADAR_EXT	0x9940
231 #define	AR_PHY_RADAR_EXT_ENA	0x00004000
232 
233 #define	AR_PHY_RADAR_0		0x9954
234 #define	AR_PHY_RADAR_0_ENA	0x00000001
235 #define	AR_PHY_RADAR_0_FFT_ENA	0x80000000
236 #define	AR_PHY_RADAR_0_INBAND	0x0000003e
237 #define	AR_PHY_RADAR_0_INBAND_S	1
238 #define	AR_PHY_RADAR_0_PRSSI	0x00000FC0
239 #define	AR_PHY_RADAR_0_PRSSI_S	6
240 #define	AR_PHY_RADAR_0_HEIGHT	0x0003F000
241 #define	AR_PHY_RADAR_0_HEIGHT_S	12
242 #define	AR_PHY_RADAR_0_RRSSI	0x00FC0000
243 #define	AR_PHY_RADAR_0_RRSSI_S	18
244 #define	AR_PHY_RADAR_0_FIRPWR	0x7F000000
245 #define	AR_PHY_RADAR_0_FIRPWR_S	24
246 
247 #define	AR_PHY_RADAR_1			0x9958
248 #define	AR_PHY_RADAR_1_RELPWR_ENA	0x00800000
249 #define	AR_PHY_RADAR_1_USE_FIR128	0x00400000
250 #define	AR_PHY_RADAR_1_RELPWR_THRESH	0x003F0000
251 #define	AR_PHY_RADAR_1_RELPWR_THRESH_S	16
252 #define	AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
253 #define	AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
254 #define	AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
255 #define	AR_PHY_RADAR_1_RELSTEP_THRESH	0x00001F00
256 #define	AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
257 #define	AR_PHY_RADAR_1_MAXLEN		0x000000FF
258 #define	AR_PHY_RADAR_1_MAXLEN_S		0
259 
260 #define	AR_PHY_SWITCH_CHAIN_0		0x9960
261 #define	AR_PHY_SWITCH_COM		0x9964
262 
263 #define	AR_PHY_SIGMA_DELTA		0x996C
264 #define	AR_PHY_SIGMA_DELTA_ADC_SEL	0x00000003
265 #define	AR_PHY_SIGMA_DELTA_ADC_SEL_S	0
266 #define	AR_PHY_SIGMA_DELTA_FILT2	0x000000F8
267 #define	AR_PHY_SIGMA_DELTA_FILT2_S	3
268 #define	AR_PHY_SIGMA_DELTA_FILT1	0x00001F00
269 #define	AR_PHY_SIGMA_DELTA_FILT1_S	8
270 #define	AR_PHY_SIGMA_DELTA_ADC_CLIP	0x01FFE000
271 #define	AR_PHY_SIGMA_DELTA_ADC_CLIP_S	13
272 
273 #define	AR_PHY_RESTART			0x9970
274 #define	AR_PHY_RESTART_DIV_GC		0x001C0000
275 #define	AR_PHY_RESTART_DIV_GC_S		18
276 
277 #define	AR_PHY_RFBUS_REQ		0x997C
278 #define	AR_PHY_RFBUS_REQ_EN		0x00000001
279 
280 #define	AR_PHY_TIMING7			0x9980
281 #define	AR_PHY_TIMING8			0x9984
282 #define	AR_PHY_TIMING8_PILOT_MASK_2	0x000FFFFF
283 #define	AR_PHY_TIMING8_PILOT_MASK_2_S	0
284 
285 #define	AR_PHY_BIN_MASK2_1	0x9988
286 #define	AR_PHY_BIN_MASK2_2	0x998c
287 #define	AR_PHY_BIN_MASK2_3	0x9990
288 #define	AR_PHY_BIN_MASK2_4	0x9994
289 
290 #define	AR_PHY_BIN_MASK_1	0x9900
291 #define	AR_PHY_BIN_MASK_2	0x9904
292 #define	AR_PHY_BIN_MASK_3	0x9908
293 
294 #define	AR_PHY_MASK_CTL		0x990c
295 
296 #define	AR_PHY_BIN_MASK2_4_MASK_4	0x00003FFF
297 #define	AR_PHY_BIN_MASK2_4_MASK_4_S	0
298 
299 #define	AR_PHY_TIMING9			0x9998
300 #define	AR_PHY_TIMING10			0x999c
301 #define	AR_PHY_TIMING10_PILOT_MASK_2	0x000FFFFF
302 #define	AR_PHY_TIMING10_PILOT_MASK_2_S	0
303 
304 #define	AR_PHY_TIMING11				0x99a0
305 #define	AR_PHY_TIMING11_SPUR_DELTA_PHASE	0x000FFFFF
306 #define	AR_PHY_TIMING11_SPUR_DELTA_PHASE_S	0
307 #define	AR_PHY_TIMING11_SPUR_FREQ_SD		0x3FF00000
308 #define	AR_PHY_TIMING11_SPUR_FREQ_SD_S		20
309 #define	AR_PHY_TIMING11_USE_SPUR_IN_AGC		0x40000000
310 #define	AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR	0x80000000
311 
312 #define	AR_PHY_RX_CHAINMASK			0x99a4
313 #define	AR_PHY_NEW_ADC_DC_GAIN_CORR(_i)		(0x99b4 + ((_i) << 12))
314 #define	AR_PHY_NEW_ADC_GAIN_CORR_ENABLE		0x40000000
315 #define	AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE	0x80000000
316 #define	AR_PHY_MULTICHAIN_GAIN_CTL  0x99ac
317 
318 #define	AR_PHY_EXT_CCA0			0x99b8
319 #define	AR_PHY_EXT_CCA0_THRESH62	0x000000FF
320 #define	AR_PHY_EXT_CCA0_THRESH62_S	0
321 
322 #define	AR_PHY_EXT_CCA			0x99bc
323 #define	AR_PHY_EXT_CCA_CYCPWR_THR1	0x0000FE00
324 #define	AR_PHY_EXT_CCA_CYCPWR_THR1_S	9
325 #define	AR_PHY_EXT_CCA_THRESH62		0x007F0000
326 #define	AR_PHY_EXT_CCA_THRESH62_S	16
327 #define	AR_PHY_EXT_MINCCA_PWR		0xFF800000
328 #define	AR_PHY_EXT_MINCCA_PWR_S		23
329 #define	AR9280_PHY_EXT_MINCCA_PWR	0x01FF0000
330 #define	AR9280_PHY_EXT_MINCCA_PWR_S	16
331 
332 #define	AR_PHY_SFCORR_EXT			0x99c0
333 #define	AR_PHY_SFCORR_EXT_M1_THRESH		0x0000007F
334 #define	AR_PHY_SFCORR_EXT_M1_THRESH_S		0
335 #define	AR_PHY_SFCORR_EXT_M2_THRESH		0x00003F80
336 #define	AR_PHY_SFCORR_EXT_M2_THRESH_S		7
337 #define	AR_PHY_SFCORR_EXT_M1_THRESH_LOW		0x001FC000
338 #define	AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S	14
339 #define	AR_PHY_SFCORR_EXT_M2_THRESH_LOW		0x0FE00000
340 #define	AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S	21
341 #define	AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S		28
342 
343 #define	AR_PHY_HALFGI		0x99D0
344 #define	AR_PHY_HALFGI_DSC_MAN	0x0007FFF0
345 #define	AR_PHY_HALFGI_DSC_MAN_S	4
346 #define	AR_PHY_HALFGI_DSC_EXP	0x0000000F
347 #define	AR_PHY_HALFGI_DSC_EXP_S	0
348 
349 #define	AR_PHY_CHAN_INFO_MEMORY			0x99DC
350 #define	AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK	0x0001
351 
352 #define	AR_PHY_HEAVY_CLIP_ENABLE	0x99E0
353 
354 #define	AR_PHY_M_SLEEP		0x99f0
355 #define	AR_PHY_REFCLKDLY	0x99f4
356 #define	AR_PHY_REFCLKPD		0x99f8
357 
358 #define	AR_PHY_CALMODE		0x99f0
359 
360 #define	AR_PHY_CALMODE_IQ		0x00000000
361 #define	AR_PHY_CALMODE_ADC_GAIN		0x00000001
362 #define	AR_PHY_CALMODE_ADC_DC_PER	0x00000002
363 #define	AR_PHY_CALMODE_ADC_DC_INIT	0x00000003
364 
365 #define	AR_PHY_CAL_MEAS_0(_i)	(0x9c10 + ((_i) << 12))
366 #define	AR_PHY_CAL_MEAS_1(_i)	(0x9c14 + ((_i) << 12))
367 #define	AR_PHY_CAL_MEAS_2(_i)	(0x9c18 + ((_i) << 12))
368 #define	AR_PHY_CAL_MEAS_3(_i)	(0x9c1c + ((_i) << 12))
369 
370 #define	AR_PHY_CURRENT_RSSI	0x9c1c
371 #define	AR9280_PHY_CURRENT_RSSI	0x9c3c
372 
373 #define	AR_PHY_RFBUS_GRANT	0x9C20
374 #define	AR_PHY_RFBUS_GRANT_EN	0x00000001
375 
376 #define	AR_PHY_CHAN_INFO_GAIN_DIFF		0x9CF4
377 #define	AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT	320
378 
379 #define	AR_PHY_CHAN_INFO_GAIN	0x9CFC
380 
381 #define	AR_PHY_MODE		0xA200
382 #define	AR_PHY_MODE_AR2133	0x08
383 #define	AR_PHY_MODE_AR5111	0x00
384 #define	AR_PHY_MODE_AR5112	0x08
385 #define	AR_PHY_MODE_DYNAMIC	0x04
386 #define	AR_PHY_MODE_RF2GHZ	0x02
387 #define	AR_PHY_MODE_RF5GHZ	0x00
388 #define	AR_PHY_MODE_CCK		0x01
389 #define	AR_PHY_MODE_OFDM	0x00
390 #define	AR_PHY_MODE_DYN_CCK_DISABLE	0x100
391 
392 #define	AR_PHY_CCK_TX_CTRL		0xA204
393 #define	AR_PHY_CCK_TX_CTRL_JAPAN	0x00000010
394 
395 #define	AR_PHY_CCK_DETECT			0xA208
396 #define	AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK	0x0000003F
397 #define	AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S	0
398 /* [12:6] settling time for antenna switch */
399 #define	AR_PHY_CCK_DETECT_ANT_SWITCH_TIME		0x00001FC0
400 #define	AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S		6
401 #define	AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV	0x2000
402 
403 #define	AR_PHY_GAIN_2GHZ		0xA20C
404 #define	AR_PHY_GAIN_2GHZ_RXTX_MARGIN	0x00FC0000
405 #define	AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S	18
406 #define	AR_PHY_GAIN_2GHZ_BSW_MARGIN	0x00003C00
407 #define	AR_PHY_GAIN_2GHZ_BSW_MARGIN_S	10
408 #define	AR_PHY_GAIN_2GHZ_BSW_ATTEN	0x0000001F
409 #define	AR_PHY_GAIN_2GHZ_BSW_ATTEN_S	0
410 
411 #define	AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN		0x003E0000
412 #define	AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S	17
413 #define	AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN		0x0001F000
414 #define	AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S	12
415 #define	AR_PHY_GAIN_2GHZ_XATTEN2_DB		0x00000FC0
416 #define	AR_PHY_GAIN_2GHZ_XATTEN2_DB_S		6
417 #define	AR_PHY_GAIN_2GHZ_XATTEN1_DB		0x0000003F
418 #define	AR_PHY_GAIN_2GHZ_XATTEN1_DB_S		0
419 
420 #define	AR_PHY_CCK_RXCTRL4			0xA21C
421 #define	AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT	0x01F80000
422 #define	AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S	19
423 
424 #define	AR_PHY_DAG_CTRLCCK		0xA228
425 #define	AR_PHY_DAG_CTRLCCK_EN_RSSI_THR	0x00000200
426 #define	AR_PHY_DAG_CTRLCCK_RSSI_THR	0x0001FC00
427 #define	AR_PHY_DAG_CTRLCCK_RSSI_THR_S	10
428 
429 #define	AR_PHY_FORCE_CLKEN_CCK		0xA22C
430 #define	AR_PHY_FORCE_CLKEN_CCK_MRC_MUX	0x00000040
431 
432 #define	AR_PHY_POWER_TX_RATE3	0xA234
433 #define	AR_PHY_POWER_TX_RATE4	0xA238
434 
435 #define	AR_PHY_SCRM_SEQ_XR		0xA23C
436 #define	AR_PHY_HEADER_DETECT_XR		0xA240
437 #define	AR_PHY_CHIRP_DETECTED_XR	0xA244
438 #define	AR_PHY_BLUETOOTH		0xA254
439 
440 #define	AR_PHY_TPCRG1			0xA258
441 #define	AR_PHY_TPCRG1_NUM_PD_GAIN	0x0000c000
442 #define	AR_PHY_TPCRG1_NUM_PD_GAIN_S	14
443 
444 #define	AR_PHY_TPCRG1_PD_GAIN_1		0x00030000
445 #define	AR_PHY_TPCRG1_PD_GAIN_1_S	16
446 #define	AR_PHY_TPCRG1_PD_GAIN_2		0x000C0000
447 #define	AR_PHY_TPCRG1_PD_GAIN_2_S	18
448 #define	AR_PHY_TPCRG1_PD_GAIN_3		0x00300000
449 #define	AR_PHY_TPCRG1_PD_GAIN_3_S	20
450 
451 #define	AR_PHY_VIT_MASK2_M_46_61	0xa3a0
452 #define	AR_PHY_MASK2_M_31_45		0xa3a4
453 #define	AR_PHY_MASK2_M_16_30		0xa3a8
454 #define	AR_PHY_MASK2_M_00_15		0xa3ac
455 #define	AR_PHY_MASK2_P_15_01		0xa3b8
456 #define	AR_PHY_MASK2_P_30_16		0xa3bc
457 #define	AR_PHY_MASK2_P_45_31		0xa3c0
458 #define	AR_PHY_MASK2_P_61_45		0xa3c4
459 #define	AR_PHY_SPUR_REG			0x994c
460 
461 #define	AR_PHY_SPUR_REG_MASK_RATE_CNTL		(0xFF << 18)
462 #define	AR_PHY_SPUR_REG_MASK_RATE_CNTL_S	18
463 
464 #define	AR_PHY_SPUR_REG_ENABLE_MASK_PPM		0x20000
465 #define	AR_PHY_SPUR_REG_MASK_RATE_SELECT	(0xFF << 9)
466 #define	AR_PHY_SPUR_REG_MASK_RATE_SELECT_S	9
467 #define	AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI	0x100
468 #define	AR_PHY_SPUR_REG_SPUR_RSSI_THRESH	0x7F
469 #define	AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S	0
470 
471 #define	AR_PHY_PILOT_MASK_01_30		0xa3b0
472 #define	AR_PHY_PILOT_MASK_31_60		0xa3b4
473 
474 #define	AR_PHY_CHANNEL_MASK_01_30	0x99d4
475 #define	AR_PHY_CHANNEL_MASK_31_60	0x99d8
476 
477 #define	AR_PHY_ANALOG_SWAP		0xa268
478 #define	AR_PHY_SWAP_ALT_CHAIN		0x00000040
479 
480 #define	AR_PHY_TPCRG5	0xA26C
481 #define	AR_PHY_TPCRG5_PD_GAIN_OVERLAP		0x0000000F
482 #define	AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S		0
483 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1	0x000003F0
484 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S	4
485 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2	0x0000FC00
486 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S	10
487 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3	0x003F0000
488 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S	16
489 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4	0x0FC00000
490 #define	AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S	22
491 
492 #define	AR_PHY_POWER_TX_RATE5	0xA38C
493 #define	AR_PHY_POWER_TX_RATE6	0xA390
494 
495 #define	AR_PHY_CAL_CHAINMASK	0xA39C
496 
497 #define	AR_PHY_POWER_TX_SUB	0xA3C8
498 #define	AR_PHY_POWER_TX_RATE7	0xA3CC
499 #define	AR_PHY_POWER_TX_RATE8	0xA3D0
500 #define	AR_PHY_POWER_TX_RATE9	0xA3D4
501 
502 #define	AR_PHY_XPA_CFG		0xA3D8
503 #define	AR_PHY_FORCE_XPA_CFG	0x000000001
504 #define	AR_PHY_FORCE_XPA_CFG_S	0
505 
506 #define	AR_PHY_CH1_CCA			0xa864
507 #define	AR_PHY_CH1_MINCCA_PWR		0x0FF80000
508 #define	AR_PHY_CH1_MINCCA_PWR_S		19
509 #define	AR9280_PHY_CH1_MINCCA_PWR	0x1FF00000
510 #define	AR9280_PHY_CH1_MINCCA_PWR_S	20
511 
512 #define	AR_PHY_CH2_CCA		0xb864
513 #define	AR_PHY_CH2_MINCCA_PWR	0x0FF80000
514 #define	AR_PHY_CH2_MINCCA_PWR_S	19
515 
516 #define	AR_PHY_CH1_EXT_CCA		0xa9bc
517 #define	AR_PHY_CH1_EXT_MINCCA_PWR	0xFF800000
518 #define	AR_PHY_CH1_EXT_MINCCA_PWR_S	23
519 #define	AR9280_PHY_CH1_EXT_MINCCA_PWR	0x01FF0000
520 #define	AR9280_PHY_CH1_EXT_MINCCA_PWR_S	16
521 
522 #define	AR_PHY_CH2_EXT_CCA		0xb9bc
523 #define	AR_PHY_CH2_EXT_MINCCA_PWR	0xFF800000
524 #define	AR_PHY_CH2_EXT_MINCCA_PWR_S	23
525 
526 #define	REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
527 		int r;							\
528 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
529 			REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
530 		}							\
531 		_NOTE(CONSTCOND) \
532 	} while (0)
533 
534 #define	ATH9K_KEY_XOR	0xaau
535 
536 #define	ATH9K_IS_MIC_ENABLED(ah)					\
537 	(AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
538 
539 #define	ANTSWAP_AB	0x0001
540 #define	REDUCE_CHAIN_0	0x00000050
541 #define	REDUCE_CHAIN_1	0x00000051
542 
543 #define	RF_BANK_SETUP(_bank, _iniarray, _col) do {			\
544 		int i;							\
545 		for (i = 0; i < (_iniarray)->ia_rows; i++)		\
546 			(_bank)[i] = INI_RA((_iniarray), i, _col);	\
547 		_NOTE(CONSTCOND) \
548 	} while (0)
549 
550 #ifdef __cplusplus
551 }
552 #endif
553 
554 
555 #endif /* _ARN_PHY_H */
556