1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _ATH_AH_EEPROM_H_ 20 #define _ATH_AH_EEPROM_H_ 21 22 #define AR_EEPROM_VER1 0x1000 /* Version 1.0; 5210 only */ 23 /* 24 * Version 3 EEPROMs are all 16K. 25 * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info, 26 * and 2.4Ghz ob/db for B & G 27 * 3.2 has more accurate pcdac intercepts and analog chip 28 * calibration. 29 * 3.3 adds ctl in-band limit, 32 ctl's, and frequency 30 * expansion 31 * 3.4 adds xr power, gainI, and 2.4 turbo params 32 */ 33 #define AR_EEPROM_VER3 0x3000 /* Version 3.0; start of 16k EEPROM */ 34 #define AR_EEPROM_VER3_1 0x3001 /* Version 3.1 */ 35 #define AR_EEPROM_VER3_2 0x3002 /* Version 3.2 */ 36 #define AR_EEPROM_VER3_3 0x3003 /* Version 3.3 */ 37 #define AR_EEPROM_VER3_4 0x3004 /* Version 3.4 */ 38 #define AR_EEPROM_VER4 0x4000 /* Version 4.x */ 39 #define AR_EEPROM_VER4_0 0x4000 /* Version 4.0 */ 40 #define AR_EEPROM_VER4_1 0x4001 /* Version 4.0 */ 41 #define AR_EEPROM_VER4_2 0x4002 /* Version 4.0 */ 42 #define AR_EEPROM_VER4_3 0x4003 /* Version 4.0 */ 43 #define AR_EEPROM_VER4_6 0x4006 /* Version 4.0 */ 44 #define AR_EEPROM_VER4_7 0x3007 /* Version 4.7 */ 45 #define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */ 46 #define AR_EEPROM_VER5 0x5000 /* Version 5.x */ 47 #define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */ 48 #define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */ 49 #define AR_EEPROM_VER5_3 0x5003 /* Adds spur mitigation table */ 50 #define AR_EEPROM_VER5_4 0x5004 51 /* 52 * Version 14 EEPROMs came in with AR5416. 53 * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc 54 * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40 55 */ 56 #define AR_EEPROM_VER14 0xE000 /* Version 14.x */ 57 #define AR_EEPROM_VER14_1 0xE001 /* Adds 11n support */ 58 #define AR_EEPROM_VER14_2 0xE002 59 #define AR_EEPROM_VER14_3 0xE003 60 #define AR_EEPROM_VER14_7 0xE007 61 #define AR_EEPROM_VER14_9 0xE009 62 #define AR_EEPROM_VER14_16 0xE010 63 #define AR_EEPROM_VER14_17 0xE011 64 #define AR_EEPROM_VER14_19 0xE013 65 66 enum { 67 AR_EEP_RFKILL, /* use ath_hal_eepromGetFlag */ 68 AR_EEP_AMODE, /* use ath_hal_eepromGetFlag */ 69 AR_EEP_BMODE, /* use ath_hal_eepromGetFlag */ 70 AR_EEP_GMODE, /* use ath_hal_eepromGetFlag */ 71 AR_EEP_TURBO5DISABLE, /* use ath_hal_eepromGetFlag */ 72 AR_EEP_TURBO2DISABLE, /* use ath_hal_eepromGetFlag */ 73 AR_EEP_ISTALON, /* use ath_hal_eepromGetFlag */ 74 AR_EEP_32KHZCRYSTAL, /* use ath_hal_eepromGetFlag */ 75 AR_EEP_MACADDR, /* uint8_t* */ 76 AR_EEP_COMPRESS, /* use ath_hal_eepromGetFlag */ 77 AR_EEP_FASTFRAME, /* use ath_hal_eepromGetFlag */ 78 AR_EEP_AES, /* use ath_hal_eepromGetFlag */ 79 AR_EEP_BURST, /* use ath_hal_eepromGetFlag */ 80 AR_EEP_MAXQCU, /* uint16_t* */ 81 AR_EEP_KCENTRIES, /* uint16_t* */ 82 AR_EEP_NFTHRESH_5, /* int16_t* */ 83 AR_EEP_NFTHRESH_2, /* int16_t* */ 84 AR_EEP_REGDMN_0, /* uint16_t* */ 85 AR_EEP_REGDMN_1, /* uint16_t* */ 86 AR_EEP_OPCAP, /* uint16_t* */ 87 AR_EEP_OPMODE, /* uint16_t* */ 88 AR_EEP_RFSILENT, /* uint16_t* */ 89 AR_EEP_OB_5, /* uint8_t* */ 90 AR_EEP_DB_5, /* uint8_t* */ 91 AR_EEP_OB_2, /* uint8_t* */ 92 AR_EEP_DB_2, /* uint8_t* */ 93 AR_EEP_TXMASK, /* uint8_t* */ 94 AR_EEP_RXMASK, /* uint8_t* */ 95 AR_EEP_RXGAIN_TYPE, /* uint8_t* */ 96 AR_EEP_TXGAIN_TYPE, /* uint8_t* */ 97 AR_EEP_DAC_HPWR_5G, /* uint8_t* */ 98 AR_EEP_OL_PWRCTRL, /* use ath_hal_eepromGetFlag */ 99 AR_EEP_FSTCLK_5G, /* use ath_hal_eepromGetFlag */ 100 AR_EEP_ANTGAINMAX_5, /* int8_t* */ 101 AR_EEP_ANTGAINMAX_2, /* int8_t* */ 102 AR_EEP_WRITEPROTECT, /* use ath_hal_eepromGetFlag */ 103 AR_EEP_PWR_TABLE_OFFSET,/* int8_t* */ 104 AR_EEP_PWDCLKIND, /* uint8_t* */ 105 AR_EEP_TEMPSENSE_SLOPE, /* int8_t* */ 106 AR_EEP_TEMPSENSE_SLOPE_PAL_ON, /* int8_t* */ 107 AR_EEP_FRAC_N_5G, /* uint8_t* */ 108 109 /* New fields for AR9300 and later */ 110 AR_EEP_DRIVE_STRENGTH, 111 AR_EEP_PAPRD_ENABLED, 112 }; 113 114 typedef struct { 115 uint16_t rdEdge; 116 uint16_t twice_rdEdgePower; 117 HAL_BOOL flag; 118 } RD_EDGES_POWER; 119 120 /* XXX should probably be version-dependent */ 121 #define SD_NO_CTL 0xf0 122 #define NO_CTL 0xff 123 #define CTL_MODE_M 0x0f 124 #define CTL_11A 0 125 #define CTL_11B 1 126 #define CTL_11G 2 127 #define CTL_TURBO 3 128 #define CTL_108G 4 129 #define CTL_2GHT20 5 130 #define CTL_5GHT20 6 131 #define CTL_2GHT40 7 132 #define CTL_5GHT40 8 133 134 /* XXX must match what FCC/MKK/ETSI are defined as in ah_regdomain.h */ 135 #define HAL_REG_DMN_MASK 0xf0 136 #define HAL_REGDMN_FCC 0x10 137 #define HAL_REGDMN_MKK 0x40 138 #define HAL_REGDMN_ETSI 0x30 139 140 #define is_reg_dmn_fcc(reg_dmn) \ 141 (((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_FCC) ? 1 : 0) 142 #define is_reg_dmn_etsi(reg_dmn) \ 143 (((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_ETSI) ? 1 : 0) 144 #define is_reg_dmn_mkk(reg_dmn) \ 145 (((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_MKK) ? 1 : 0) 146 147 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 148 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 149 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 150 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 151 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 152 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 153 154 /* regulatory capabilities prior to eeprom version 4.0 */ 155 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 156 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 157 158 #define AR_NO_SPUR 0x8000 159 160 /* XXX exposed to chip code */ 161 #define MAX_RATE_POWER 63 162 163 HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah); 164 HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah); 165 HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah); 166 HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah); 167 HAL_STATUS ath_hal_9287EepromAttach(struct ath_hal *ah); 168 #endif /* _ATH_AH_EEPROM_H_ */ 169