1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 18 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 19 select ARCH_ENABLE_MEMORY_HOTPLUG 20 select ARCH_ENABLE_MEMORY_HOTREMOVE 21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 22 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 23 select ARCH_HAS_CACHE_LINE_SIZE 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 41 select ARCH_HAS_PTE_DEVMAP 42 select ARCH_HAS_PTE_SPECIAL 43 select ARCH_HAS_HW_PTE_YOUNG 44 select ARCH_HAS_SETUP_DMA_OPS 45 select ARCH_HAS_SET_DIRECT_MAP 46 select ARCH_HAS_SET_MEMORY 47 select ARCH_STACKWALK 48 select ARCH_HAS_STRICT_KERNEL_RWX 49 select ARCH_HAS_STRICT_MODULE_RWX 50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 51 select ARCH_HAS_SYNC_DMA_FOR_CPU 52 select ARCH_HAS_SYSCALL_WRAPPER 53 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 54 select ARCH_HAS_ZONE_DMA_SET if EXPERT 55 select ARCH_HAVE_ELF_PROT 56 select ARCH_HAVE_NMI_SAFE_CMPXCHG 57 select ARCH_HAVE_TRACE_MMIO_ACCESS 58 select ARCH_INLINE_READ_LOCK if !PREEMPTION 59 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 63 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 64 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 71 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 74 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 81 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 83 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 84 select ARCH_KEEP_MEMBLOCK 85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 86 select ARCH_USE_CMPXCHG_LOCKREF 87 select ARCH_USE_GNU_PROPERTY 88 select ARCH_USE_MEMTEST 89 select ARCH_USE_QUEUED_RWLOCKS 90 select ARCH_USE_QUEUED_SPINLOCKS 91 select ARCH_USE_SYM_ANNOTATIONS 92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 93 select ARCH_SUPPORTS_HUGETLBFS 94 select ARCH_SUPPORTS_MEMORY_FAILURE 95 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 96 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 97 select ARCH_SUPPORTS_LTO_CLANG_THIN 98 select ARCH_SUPPORTS_CFI_CLANG 99 select ARCH_SUPPORTS_ATOMIC_RMW 100 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 101 select ARCH_SUPPORTS_NUMA_BALANCING 102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 103 select ARCH_SUPPORTS_PER_VMA_LOCK 104 select ARCH_SUPPORTS_RT 105 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 106 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 107 select ARCH_WANT_DEFAULT_BPF_JIT 108 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 109 select ARCH_WANT_FRAME_POINTERS 110 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 111 select ARCH_WANT_LD_ORPHAN_WARN 112 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 113 select ARCH_WANTS_NO_INSTR 114 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 115 select ARCH_HAS_UBSAN 116 select ARM_AMBA 117 select ARM_ARCH_TIMER 118 select ARM_GIC 119 select AUDIT_ARCH_COMPAT_GENERIC 120 select ARM_GIC_V2M if PCI 121 select ARM_GIC_V3 122 select ARM_GIC_V3_ITS if PCI 123 select ARM_PSCI_FW 124 select BUILDTIME_TABLE_SORT 125 select CLONE_BACKWARDS 126 select COMMON_CLK 127 select CPU_PM if (SUSPEND || CPU_IDLE) 128 select CPUMASK_OFFSTACK if NR_CPUS > 256 129 select CRC32 130 select DCACHE_WORD_ACCESS 131 select DYNAMIC_FTRACE if FUNCTION_TRACER 132 select DMA_BOUNCE_UNALIGNED_KMALLOC 133 select DMA_DIRECT_REMAP 134 select EDAC_SUPPORT 135 select FRAME_POINTER 136 select FUNCTION_ALIGNMENT_4B 137 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 138 select GENERIC_ALLOCATOR 139 select GENERIC_ARCH_TOPOLOGY 140 select GENERIC_CLOCKEVENTS_BROADCAST 141 select GENERIC_CPU_AUTOPROBE 142 select GENERIC_CPU_DEVICES 143 select GENERIC_CPU_VULNERABILITIES 144 select GENERIC_EARLY_IOREMAP 145 select GENERIC_IDLE_POLL_SETUP 146 select GENERIC_IOREMAP 147 select GENERIC_IRQ_IPI 148 select GENERIC_IRQ_PROBE 149 select GENERIC_IRQ_SHOW 150 select GENERIC_IRQ_SHOW_LEVEL 151 select GENERIC_LIB_DEVMEM_IS_ALLOWED 152 select GENERIC_PCI_IOMAP 153 select GENERIC_PTDUMP 154 select GENERIC_SCHED_CLOCK 155 select GENERIC_SMP_IDLE_THREAD 156 select GENERIC_TIME_VSYSCALL 157 select GENERIC_GETTIMEOFDAY 158 select GENERIC_VDSO_TIME_NS 159 select HARDIRQS_SW_RESEND 160 select HAS_IOPORT 161 select HAVE_MOVE_PMD 162 select HAVE_MOVE_PUD 163 select HAVE_PCI 164 select HAVE_ACPI_APEI if (ACPI && EFI) 165 select HAVE_ALIGNED_STRUCT_PAGE 166 select HAVE_ARCH_AUDITSYSCALL 167 select HAVE_ARCH_BITREVERSE 168 select HAVE_ARCH_COMPILER_H 169 select HAVE_ARCH_HUGE_VMALLOC 170 select HAVE_ARCH_HUGE_VMAP 171 select HAVE_ARCH_JUMP_LABEL 172 select HAVE_ARCH_JUMP_LABEL_RELATIVE 173 select HAVE_ARCH_KASAN 174 select HAVE_ARCH_KASAN_VMALLOC 175 select HAVE_ARCH_KASAN_SW_TAGS 176 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 177 # Some instrumentation may be unsound, hence EXPERT 178 select HAVE_ARCH_KCSAN if EXPERT 179 select HAVE_ARCH_KFENCE 180 select HAVE_ARCH_KGDB 181 select HAVE_ARCH_MMAP_RND_BITS 182 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 183 select HAVE_ARCH_PREL32_RELOCATIONS 184 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 185 select HAVE_ARCH_SECCOMP_FILTER 186 select HAVE_ARCH_STACKLEAK 187 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 188 select HAVE_ARCH_TRACEHOOK 189 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 190 select HAVE_ARCH_VMAP_STACK 191 select HAVE_ARM_SMCCC 192 select HAVE_ASM_MODVERSIONS 193 select HAVE_EBPF_JIT 194 select HAVE_C_RECORDMCOUNT 195 select HAVE_CMPXCHG_DOUBLE 196 select HAVE_CMPXCHG_LOCAL 197 select HAVE_CONTEXT_TRACKING_USER 198 select HAVE_DEBUG_KMEMLEAK 199 select HAVE_DMA_CONTIGUOUS 200 select HAVE_DYNAMIC_FTRACE 201 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 202 if $(cc-option,-fpatchable-function-entry=2) 203 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 204 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 205 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 206 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 207 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 208 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 209 if DYNAMIC_FTRACE_WITH_ARGS 210 select HAVE_SAMPLE_FTRACE_DIRECT 211 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 212 select HAVE_EFFICIENT_UNALIGNED_ACCESS 213 select HAVE_GUP_FAST 214 select HAVE_FTRACE_MCOUNT_RECORD 215 select HAVE_FUNCTION_TRACER 216 select HAVE_FUNCTION_ERROR_INJECTION 217 select HAVE_FUNCTION_GRAPH_TRACER 218 select HAVE_FUNCTION_GRAPH_RETVAL 219 select HAVE_GCC_PLUGINS 220 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 221 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 222 select HAVE_HW_BREAKPOINT if PERF_EVENTS 223 select HAVE_IOREMAP_PROT 224 select HAVE_IRQ_TIME_ACCOUNTING 225 select HAVE_MOD_ARCH_SPECIFIC 226 select HAVE_NMI 227 select HAVE_PERF_EVENTS 228 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 229 select HAVE_PERF_REGS 230 select HAVE_PERF_USER_STACK_DUMP 231 select HAVE_PREEMPT_DYNAMIC_KEY 232 select HAVE_REGS_AND_STACK_ACCESS_API 233 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 234 select HAVE_FUNCTION_ARG_ACCESS_API 235 select MMU_GATHER_RCU_TABLE_FREE 236 select HAVE_RSEQ 237 select HAVE_RUST if CPU_LITTLE_ENDIAN 238 select HAVE_STACKPROTECTOR 239 select HAVE_SYSCALL_TRACEPOINTS 240 select HAVE_KPROBES 241 select HAVE_KRETPROBES 242 select HAVE_GENERIC_VDSO 243 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 244 select IRQ_DOMAIN 245 select IRQ_FORCED_THREADING 246 select KASAN_VMALLOC if KASAN 247 select LOCK_MM_AND_FIND_VMA 248 select MODULES_USE_ELF_RELA 249 select NEED_DMA_MAP_STATE 250 select NEED_SG_DMA_LENGTH 251 select OF 252 select OF_EARLY_FLATTREE 253 select PCI_DOMAINS_GENERIC if PCI 254 select PCI_ECAM if (ACPI && PCI) 255 select PCI_SYSCALL if PCI 256 select POWER_RESET 257 select POWER_SUPPLY 258 select SPARSE_IRQ 259 select SWIOTLB 260 select SYSCTL_EXCEPTION_TRACE 261 select THREAD_INFO_IN_TASK 262 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 263 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 264 select TRACE_IRQFLAGS_SUPPORT 265 select TRACE_IRQFLAGS_NMI_SUPPORT 266 select HAVE_SOFTIRQ_ON_OWN_STACK 267 select USER_STACKTRACE_SUPPORT 268 select VDSO_GETRANDOM 269 help 270 ARM 64-bit (AArch64) Linux support. 271 272config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 273 def_bool CC_IS_CLANG 274 # https://github.com/ClangBuiltLinux/linux/issues/1507 275 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 276 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 277 278config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 279 def_bool CC_IS_GCC 280 depends on $(cc-option,-fpatchable-function-entry=2) 281 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 282 283config 64BIT 284 def_bool y 285 286config MMU 287 def_bool y 288 289config ARM64_CONT_PTE_SHIFT 290 int 291 default 5 if PAGE_SIZE_64KB 292 default 7 if PAGE_SIZE_16KB 293 default 4 294 295config ARM64_CONT_PMD_SHIFT 296 int 297 default 5 if PAGE_SIZE_64KB 298 default 5 if PAGE_SIZE_16KB 299 default 4 300 301config ARCH_MMAP_RND_BITS_MIN 302 default 14 if PAGE_SIZE_64KB 303 default 16 if PAGE_SIZE_16KB 304 default 18 305 306# max bits determined by the following formula: 307# VA_BITS - PAGE_SHIFT - 3 308config ARCH_MMAP_RND_BITS_MAX 309 default 19 if ARM64_VA_BITS=36 310 default 24 if ARM64_VA_BITS=39 311 default 27 if ARM64_VA_BITS=42 312 default 30 if ARM64_VA_BITS=47 313 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 314 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 315 default 33 if ARM64_VA_BITS=48 316 default 14 if ARM64_64K_PAGES 317 default 16 if ARM64_16K_PAGES 318 default 18 319 320config ARCH_MMAP_RND_COMPAT_BITS_MIN 321 default 7 if ARM64_64K_PAGES 322 default 9 if ARM64_16K_PAGES 323 default 11 324 325config ARCH_MMAP_RND_COMPAT_BITS_MAX 326 default 16 327 328config NO_IOPORT_MAP 329 def_bool y if !PCI 330 331config STACKTRACE_SUPPORT 332 def_bool y 333 334config ILLEGAL_POINTER_VALUE 335 hex 336 default 0xdead000000000000 337 338config LOCKDEP_SUPPORT 339 def_bool y 340 341config GENERIC_BUG 342 def_bool y 343 depends on BUG 344 345config GENERIC_BUG_RELATIVE_POINTERS 346 def_bool y 347 depends on GENERIC_BUG 348 349config GENERIC_HWEIGHT 350 def_bool y 351 352config GENERIC_CSUM 353 def_bool y 354 355config GENERIC_CALIBRATE_DELAY 356 def_bool y 357 358config SMP 359 def_bool y 360 361config KERNEL_MODE_NEON 362 def_bool y 363 364config FIX_EARLYCON_MEM 365 def_bool y 366 367config PGTABLE_LEVELS 368 int 369 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 370 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 371 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 372 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 373 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 374 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 375 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 376 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 377 378config ARCH_SUPPORTS_UPROBES 379 def_bool y 380 381config ARCH_PROC_KCORE_TEXT 382 def_bool y 383 384config BROKEN_GAS_INST 385 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 386 387config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 388 bool 389 # Clang's __builtin_return_address() strips the PAC since 12.0.0 390 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 391 default y if CC_IS_CLANG 392 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 393 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 394 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 395 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 396 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 397 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 398 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 399 default n 400 401config KASAN_SHADOW_OFFSET 402 hex 403 depends on KASAN_GENERIC || KASAN_SW_TAGS 404 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 405 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 406 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 407 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 408 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 409 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 410 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 411 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 412 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 413 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 414 default 0xffffffffffffffff 415 416config UNWIND_TABLES 417 bool 418 419source "arch/arm64/Kconfig.platforms" 420 421menu "Kernel Features" 422 423menu "ARM errata workarounds via the alternatives framework" 424 425config AMPERE_ERRATUM_AC03_CPU_38 426 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 427 default y 428 help 429 This option adds an alternative code sequence to work around Ampere 430 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 431 432 The affected design reports FEAT_HAFDBS as not implemented in 433 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 434 as required by the architecture. The unadvertised HAFDBS 435 implementation suffers from an additional erratum where hardware 436 A/D updates can occur after a PTE has been marked invalid. 437 438 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 439 which avoids enabling unadvertised hardware Access Flag management 440 at stage-2. 441 442 If unsure, say Y. 443 444config ARM64_WORKAROUND_CLEAN_CACHE 445 bool 446 447config ARM64_ERRATUM_826319 448 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 449 default y 450 select ARM64_WORKAROUND_CLEAN_CACHE 451 help 452 This option adds an alternative code sequence to work around ARM 453 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 454 AXI master interface and an L2 cache. 455 456 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 457 and is unable to accept a certain write via this interface, it will 458 not progress on read data presented on the read data channel and the 459 system can deadlock. 460 461 The workaround promotes data cache clean instructions to 462 data cache clean-and-invalidate. 463 Please note that this does not necessarily enable the workaround, 464 as it depends on the alternative framework, which will only patch 465 the kernel if an affected CPU is detected. 466 467 If unsure, say Y. 468 469config ARM64_ERRATUM_827319 470 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 471 default y 472 select ARM64_WORKAROUND_CLEAN_CACHE 473 help 474 This option adds an alternative code sequence to work around ARM 475 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 476 master interface and an L2 cache. 477 478 Under certain conditions this erratum can cause a clean line eviction 479 to occur at the same time as another transaction to the same address 480 on the AMBA 5 CHI interface, which can cause data corruption if the 481 interconnect reorders the two transactions. 482 483 The workaround promotes data cache clean instructions to 484 data cache clean-and-invalidate. 485 Please note that this does not necessarily enable the workaround, 486 as it depends on the alternative framework, which will only patch 487 the kernel if an affected CPU is detected. 488 489 If unsure, say Y. 490 491config ARM64_ERRATUM_824069 492 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 493 default y 494 select ARM64_WORKAROUND_CLEAN_CACHE 495 help 496 This option adds an alternative code sequence to work around ARM 497 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 498 to a coherent interconnect. 499 500 If a Cortex-A53 processor is executing a store or prefetch for 501 write instruction at the same time as a processor in another 502 cluster is executing a cache maintenance operation to the same 503 address, then this erratum might cause a clean cache line to be 504 incorrectly marked as dirty. 505 506 The workaround promotes data cache clean instructions to 507 data cache clean-and-invalidate. 508 Please note that this option does not necessarily enable the 509 workaround, as it depends on the alternative framework, which will 510 only patch the kernel if an affected CPU is detected. 511 512 If unsure, say Y. 513 514config ARM64_ERRATUM_819472 515 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 516 default y 517 select ARM64_WORKAROUND_CLEAN_CACHE 518 help 519 This option adds an alternative code sequence to work around ARM 520 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 521 present when it is connected to a coherent interconnect. 522 523 If the processor is executing a load and store exclusive sequence at 524 the same time as a processor in another cluster is executing a cache 525 maintenance operation to the same address, then this erratum might 526 cause data corruption. 527 528 The workaround promotes data cache clean instructions to 529 data cache clean-and-invalidate. 530 Please note that this does not necessarily enable the workaround, 531 as it depends on the alternative framework, which will only patch 532 the kernel if an affected CPU is detected. 533 534 If unsure, say Y. 535 536config ARM64_ERRATUM_832075 537 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 538 default y 539 help 540 This option adds an alternative code sequence to work around ARM 541 erratum 832075 on Cortex-A57 parts up to r1p2. 542 543 Affected Cortex-A57 parts might deadlock when exclusive load/store 544 instructions to Write-Back memory are mixed with Device loads. 545 546 The workaround is to promote device loads to use Load-Acquire 547 semantics. 548 Please note that this does not necessarily enable the workaround, 549 as it depends on the alternative framework, which will only patch 550 the kernel if an affected CPU is detected. 551 552 If unsure, say Y. 553 554config ARM64_ERRATUM_834220 555 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 556 depends on KVM 557 help 558 This option adds an alternative code sequence to work around ARM 559 erratum 834220 on Cortex-A57 parts up to r1p2. 560 561 Affected Cortex-A57 parts might report a Stage 2 translation 562 fault as the result of a Stage 1 fault for load crossing a 563 page boundary when there is a permission or device memory 564 alignment fault at Stage 1 and a translation fault at Stage 2. 565 566 The workaround is to verify that the Stage 1 translation 567 doesn't generate a fault before handling the Stage 2 fault. 568 Please note that this does not necessarily enable the workaround, 569 as it depends on the alternative framework, which will only patch 570 the kernel if an affected CPU is detected. 571 572 If unsure, say N. 573 574config ARM64_ERRATUM_1742098 575 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 576 depends on COMPAT 577 default y 578 help 579 This option removes the AES hwcap for aarch32 user-space to 580 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 581 582 Affected parts may corrupt the AES state if an interrupt is 583 taken between a pair of AES instructions. These instructions 584 are only present if the cryptography extensions are present. 585 All software should have a fallback implementation for CPUs 586 that don't implement the cryptography extensions. 587 588 If unsure, say Y. 589 590config ARM64_ERRATUM_845719 591 bool "Cortex-A53: 845719: a load might read incorrect data" 592 depends on COMPAT 593 default y 594 help 595 This option adds an alternative code sequence to work around ARM 596 erratum 845719 on Cortex-A53 parts up to r0p4. 597 598 When running a compat (AArch32) userspace on an affected Cortex-A53 599 part, a load at EL0 from a virtual address that matches the bottom 32 600 bits of the virtual address used by a recent load at (AArch64) EL1 601 might return incorrect data. 602 603 The workaround is to write the contextidr_el1 register on exception 604 return to a 32-bit task. 605 Please note that this does not necessarily enable the workaround, 606 as it depends on the alternative framework, which will only patch 607 the kernel if an affected CPU is detected. 608 609 If unsure, say Y. 610 611config ARM64_ERRATUM_843419 612 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 613 default y 614 help 615 This option links the kernel with '--fix-cortex-a53-843419' and 616 enables PLT support to replace certain ADRP instructions, which can 617 cause subsequent memory accesses to use an incorrect address on 618 Cortex-A53 parts up to r0p4. 619 620 If unsure, say Y. 621 622config ARM64_LD_HAS_FIX_ERRATUM_843419 623 def_bool $(ld-option,--fix-cortex-a53-843419) 624 625config ARM64_ERRATUM_1024718 626 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 627 default y 628 help 629 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 630 631 Affected Cortex-A55 cores (all revisions) could cause incorrect 632 update of the hardware dirty bit when the DBM/AP bits are updated 633 without a break-before-make. The workaround is to disable the usage 634 of hardware DBM locally on the affected cores. CPUs not affected by 635 this erratum will continue to use the feature. 636 637 If unsure, say Y. 638 639config ARM64_ERRATUM_1418040 640 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 641 default y 642 depends on COMPAT 643 help 644 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 645 errata 1188873 and 1418040. 646 647 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 648 cause register corruption when accessing the timer registers 649 from AArch32 userspace. 650 651 If unsure, say Y. 652 653config ARM64_WORKAROUND_SPECULATIVE_AT 654 bool 655 656config ARM64_ERRATUM_1165522 657 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 658 default y 659 select ARM64_WORKAROUND_SPECULATIVE_AT 660 help 661 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 662 663 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 664 corrupted TLBs by speculating an AT instruction during a guest 665 context switch. 666 667 If unsure, say Y. 668 669config ARM64_ERRATUM_1319367 670 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 671 default y 672 select ARM64_WORKAROUND_SPECULATIVE_AT 673 help 674 This option adds work arounds for ARM Cortex-A57 erratum 1319537 675 and A72 erratum 1319367 676 677 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 678 speculating an AT instruction during a guest context switch. 679 680 If unsure, say Y. 681 682config ARM64_ERRATUM_1530923 683 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 684 default y 685 select ARM64_WORKAROUND_SPECULATIVE_AT 686 help 687 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 688 689 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 690 corrupted TLBs by speculating an AT instruction during a guest 691 context switch. 692 693 If unsure, say Y. 694 695config ARM64_WORKAROUND_REPEAT_TLBI 696 bool 697 698config ARM64_ERRATUM_2441007 699 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 700 select ARM64_WORKAROUND_REPEAT_TLBI 701 help 702 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 703 704 Under very rare circumstances, affected Cortex-A55 CPUs 705 may not handle a race between a break-before-make sequence on one 706 CPU, and another CPU accessing the same page. This could allow a 707 store to a page that has been unmapped. 708 709 Work around this by adding the affected CPUs to the list that needs 710 TLB sequences to be done twice. 711 712 If unsure, say N. 713 714config ARM64_ERRATUM_1286807 715 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 716 select ARM64_WORKAROUND_REPEAT_TLBI 717 help 718 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 719 720 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 721 address for a cacheable mapping of a location is being 722 accessed by a core while another core is remapping the virtual 723 address to a new physical page using the recommended 724 break-before-make sequence, then under very rare circumstances 725 TLBI+DSB completes before a read using the translation being 726 invalidated has been observed by other observers. The 727 workaround repeats the TLBI+DSB operation. 728 729 If unsure, say N. 730 731config ARM64_ERRATUM_1463225 732 bool "Cortex-A76: Software Step might prevent interrupt recognition" 733 default y 734 help 735 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 736 737 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 738 of a system call instruction (SVC) can prevent recognition of 739 subsequent interrupts when software stepping is disabled in the 740 exception handler of the system call and either kernel debugging 741 is enabled or VHE is in use. 742 743 Work around the erratum by triggering a dummy step exception 744 when handling a system call from a task that is being stepped 745 in a VHE configuration of the kernel. 746 747 If unsure, say Y. 748 749config ARM64_ERRATUM_1542419 750 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 751 help 752 This option adds a workaround for ARM Neoverse-N1 erratum 753 1542419. 754 755 Affected Neoverse-N1 cores could execute a stale instruction when 756 modified by another CPU. The workaround depends on a firmware 757 counterpart. 758 759 Workaround the issue by hiding the DIC feature from EL0. This 760 forces user-space to perform cache maintenance. 761 762 If unsure, say N. 763 764config ARM64_ERRATUM_1508412 765 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 766 default y 767 help 768 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 769 770 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 771 of a store-exclusive or read of PAR_EL1 and a load with device or 772 non-cacheable memory attributes. The workaround depends on a firmware 773 counterpart. 774 775 KVM guests must also have the workaround implemented or they can 776 deadlock the system. 777 778 Work around the issue by inserting DMB SY barriers around PAR_EL1 779 register reads and warning KVM users. The DMB barrier is sufficient 780 to prevent a speculative PAR_EL1 read. 781 782 If unsure, say Y. 783 784config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 785 bool 786 787config ARM64_ERRATUM_2051678 788 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 789 default y 790 help 791 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 792 Affected Cortex-A510 might not respect the ordering rules for 793 hardware update of the page table's dirty bit. The workaround 794 is to not enable the feature on affected CPUs. 795 796 If unsure, say Y. 797 798config ARM64_ERRATUM_2077057 799 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 800 default y 801 help 802 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 803 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 804 expected, but a Pointer Authentication trap is taken instead. The 805 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 806 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 807 808 This can only happen when EL2 is stepping EL1. 809 810 When these conditions occur, the SPSR_EL2 value is unchanged from the 811 previous guest entry, and can be restored from the in-memory copy. 812 813 If unsure, say Y. 814 815config ARM64_ERRATUM_2658417 816 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 817 default y 818 help 819 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 820 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 821 BFMMLA or VMMLA instructions in rare circumstances when a pair of 822 A510 CPUs are using shared neon hardware. As the sharing is not 823 discoverable by the kernel, hide the BF16 HWCAP to indicate that 824 user-space should not be using these instructions. 825 826 If unsure, say Y. 827 828config ARM64_ERRATUM_2119858 829 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 830 default y 831 depends on CORESIGHT_TRBE 832 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 833 help 834 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 835 836 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 837 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 838 the event of a WRAP event. 839 840 Work around the issue by always making sure we move the TRBPTR_EL1 by 841 256 bytes before enabling the buffer and filling the first 256 bytes of 842 the buffer with ETM ignore packets upon disabling. 843 844 If unsure, say Y. 845 846config ARM64_ERRATUM_2139208 847 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 848 default y 849 depends on CORESIGHT_TRBE 850 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 851 help 852 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 853 854 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 855 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 856 the event of a WRAP event. 857 858 Work around the issue by always making sure we move the TRBPTR_EL1 by 859 256 bytes before enabling the buffer and filling the first 256 bytes of 860 the buffer with ETM ignore packets upon disabling. 861 862 If unsure, say Y. 863 864config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 865 bool 866 867config ARM64_ERRATUM_2054223 868 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 869 default y 870 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 871 help 872 Enable workaround for ARM Cortex-A710 erratum 2054223 873 874 Affected cores may fail to flush the trace data on a TSB instruction, when 875 the PE is in trace prohibited state. This will cause losing a few bytes 876 of the trace cached. 877 878 Workaround is to issue two TSB consecutively on affected cores. 879 880 If unsure, say Y. 881 882config ARM64_ERRATUM_2067961 883 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 884 default y 885 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 886 help 887 Enable workaround for ARM Neoverse-N2 erratum 2067961 888 889 Affected cores may fail to flush the trace data on a TSB instruction, when 890 the PE is in trace prohibited state. This will cause losing a few bytes 891 of the trace cached. 892 893 Workaround is to issue two TSB consecutively on affected cores. 894 895 If unsure, say Y. 896 897config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 898 bool 899 900config ARM64_ERRATUM_2253138 901 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 902 depends on CORESIGHT_TRBE 903 default y 904 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 905 help 906 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 907 908 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 909 for TRBE. Under some conditions, the TRBE might generate a write to the next 910 virtually addressed page following the last page of the TRBE address space 911 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 912 913 Work around this in the driver by always making sure that there is a 914 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 915 916 If unsure, say Y. 917 918config ARM64_ERRATUM_2224489 919 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 920 depends on CORESIGHT_TRBE 921 default y 922 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 923 help 924 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 925 926 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 927 for TRBE. Under some conditions, the TRBE might generate a write to the next 928 virtually addressed page following the last page of the TRBE address space 929 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 930 931 Work around this in the driver by always making sure that there is a 932 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 933 934 If unsure, say Y. 935 936config ARM64_ERRATUM_2441009 937 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 938 select ARM64_WORKAROUND_REPEAT_TLBI 939 help 940 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 941 942 Under very rare circumstances, affected Cortex-A510 CPUs 943 may not handle a race between a break-before-make sequence on one 944 CPU, and another CPU accessing the same page. This could allow a 945 store to a page that has been unmapped. 946 947 Work around this by adding the affected CPUs to the list that needs 948 TLB sequences to be done twice. 949 950 If unsure, say N. 951 952config ARM64_ERRATUM_2064142 953 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 954 depends on CORESIGHT_TRBE 955 default y 956 help 957 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 958 959 Affected Cortex-A510 core might fail to write into system registers after the 960 TRBE has been disabled. Under some conditions after the TRBE has been disabled 961 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 962 and TRBTRG_EL1 will be ignored and will not be effected. 963 964 Work around this in the driver by executing TSB CSYNC and DSB after collection 965 is stopped and before performing a system register write to one of the affected 966 registers. 967 968 If unsure, say Y. 969 970config ARM64_ERRATUM_2038923 971 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 972 depends on CORESIGHT_TRBE 973 default y 974 help 975 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 976 977 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 978 prohibited within the CPU. As a result, the trace buffer or trace buffer state 979 might be corrupted. This happens after TRBE buffer has been enabled by setting 980 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 981 execution changes from a context, in which trace is prohibited to one where it 982 isn't, or vice versa. In these mentioned conditions, the view of whether trace 983 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 984 the trace buffer state might be corrupted. 985 986 Work around this in the driver by preventing an inconsistent view of whether the 987 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 988 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 989 two ISB instructions if no ERET is to take place. 990 991 If unsure, say Y. 992 993config ARM64_ERRATUM_1902691 994 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 995 depends on CORESIGHT_TRBE 996 default y 997 help 998 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 999 1000 Affected Cortex-A510 core might cause trace data corruption, when being written 1001 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1002 trace data. 1003 1004 Work around this problem in the driver by just preventing TRBE initialization on 1005 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1006 on such implementations. This will cover the kernel for any firmware that doesn't 1007 do this already. 1008 1009 If unsure, say Y. 1010 1011config ARM64_ERRATUM_2457168 1012 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1013 depends on ARM64_AMU_EXTN 1014 default y 1015 help 1016 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1017 1018 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1019 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1020 incorrectly giving a significantly higher output value. 1021 1022 Work around this problem by returning 0 when reading the affected counter in 1023 key locations that results in disabling all users of this counter. This effect 1024 is the same to firmware disabling affected counters. 1025 1026 If unsure, say Y. 1027 1028config ARM64_ERRATUM_2645198 1029 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1030 default y 1031 help 1032 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1033 1034 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1035 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1036 next instruction abort caused by permission fault. 1037 1038 Only user-space does executable to non-executable permission transition via 1039 mprotect() system call. Workaround the problem by doing a break-before-make 1040 TLB invalidation, for all changes to executable user space mappings. 1041 1042 If unsure, say Y. 1043 1044config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1045 bool 1046 1047config ARM64_ERRATUM_2966298 1048 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1049 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1050 default y 1051 help 1052 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1053 1054 On an affected Cortex-A520 core, a speculatively executed unprivileged 1055 load might leak data from a privileged level via a cache side channel. 1056 1057 Work around this problem by executing a TLBI before returning to EL0. 1058 1059 If unsure, say Y. 1060 1061config ARM64_ERRATUM_3117295 1062 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1063 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1064 default y 1065 help 1066 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1067 1068 On an affected Cortex-A510 core, a speculatively executed unprivileged 1069 load might leak data from a privileged level via a cache side channel. 1070 1071 Work around this problem by executing a TLBI before returning to EL0. 1072 1073 If unsure, say Y. 1074 1075config ARM64_ERRATUM_3194386 1076 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1077 default y 1078 help 1079 This option adds the workaround for the following errata: 1080 1081 * ARM Cortex-A76 erratum 3324349 1082 * ARM Cortex-A77 erratum 3324348 1083 * ARM Cortex-A78 erratum 3324344 1084 * ARM Cortex-A78C erratum 3324346 1085 * ARM Cortex-A78C erratum 3324347 1086 * ARM Cortex-A710 erratam 3324338 1087 * ARM Cortex-A720 erratum 3456091 1088 * ARM Cortex-A725 erratum 3456106 1089 * ARM Cortex-X1 erratum 3324344 1090 * ARM Cortex-X1C erratum 3324346 1091 * ARM Cortex-X2 erratum 3324338 1092 * ARM Cortex-X3 erratum 3324335 1093 * ARM Cortex-X4 erratum 3194386 1094 * ARM Cortex-X925 erratum 3324334 1095 * ARM Neoverse-N1 erratum 3324349 1096 * ARM Neoverse N2 erratum 3324339 1097 * ARM Neoverse-V1 erratum 3324341 1098 * ARM Neoverse V2 erratum 3324336 1099 * ARM Neoverse-V3 erratum 3312417 1100 1101 On affected cores "MSR SSBS, #0" instructions may not affect 1102 subsequent speculative instructions, which may permit unexepected 1103 speculative store bypassing. 1104 1105 Work around this problem by placing a Speculation Barrier (SB) or 1106 Instruction Synchronization Barrier (ISB) after kernel changes to 1107 SSBS. The presence of the SSBS special-purpose register is hidden 1108 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1109 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1110 1111 If unsure, say Y. 1112 1113config CAVIUM_ERRATUM_22375 1114 bool "Cavium erratum 22375, 24313" 1115 default y 1116 help 1117 Enable workaround for errata 22375 and 24313. 1118 1119 This implements two gicv3-its errata workarounds for ThunderX. Both 1120 with a small impact affecting only ITS table allocation. 1121 1122 erratum 22375: only alloc 8MB table size 1123 erratum 24313: ignore memory access type 1124 1125 The fixes are in ITS initialization and basically ignore memory access 1126 type and table size provided by the TYPER and BASER registers. 1127 1128 If unsure, say Y. 1129 1130config CAVIUM_ERRATUM_23144 1131 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1132 depends on NUMA 1133 default y 1134 help 1135 ITS SYNC command hang for cross node io and collections/cpu mapping. 1136 1137 If unsure, say Y. 1138 1139config CAVIUM_ERRATUM_23154 1140 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1141 default y 1142 help 1143 The ThunderX GICv3 implementation requires a modified version for 1144 reading the IAR status to ensure data synchronization 1145 (access to icc_iar1_el1 is not sync'ed before and after). 1146 1147 It also suffers from erratum 38545 (also present on Marvell's 1148 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1149 spuriously presented to the CPU interface. 1150 1151 If unsure, say Y. 1152 1153config CAVIUM_ERRATUM_27456 1154 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1155 default y 1156 help 1157 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1158 instructions may cause the icache to become corrupted if it 1159 contains data for a non-current ASID. The fix is to 1160 invalidate the icache when changing the mm context. 1161 1162 If unsure, say Y. 1163 1164config CAVIUM_ERRATUM_30115 1165 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1166 default y 1167 help 1168 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1169 1.2, and T83 Pass 1.0, KVM guest execution may disable 1170 interrupts in host. Trapping both GICv3 group-0 and group-1 1171 accesses sidesteps the issue. 1172 1173 If unsure, say Y. 1174 1175config CAVIUM_TX2_ERRATUM_219 1176 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1177 default y 1178 help 1179 On Cavium ThunderX2, a load, store or prefetch instruction between a 1180 TTBR update and the corresponding context synchronizing operation can 1181 cause a spurious Data Abort to be delivered to any hardware thread in 1182 the CPU core. 1183 1184 Work around the issue by avoiding the problematic code sequence and 1185 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1186 trap handler performs the corresponding register access, skips the 1187 instruction and ensures context synchronization by virtue of the 1188 exception return. 1189 1190 If unsure, say Y. 1191 1192config FUJITSU_ERRATUM_010001 1193 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1194 default y 1195 help 1196 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1197 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1198 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1199 This fault occurs under a specific hardware condition when a 1200 load/store instruction performs an address translation using: 1201 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1202 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1203 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1204 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1205 1206 The workaround is to ensure these bits are clear in TCR_ELx. 1207 The workaround only affects the Fujitsu-A64FX. 1208 1209 If unsure, say Y. 1210 1211config HISILICON_ERRATUM_161600802 1212 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1213 default y 1214 help 1215 The HiSilicon Hip07 SoC uses the wrong redistributor base 1216 when issued ITS commands such as VMOVP and VMAPP, and requires 1217 a 128kB offset to be applied to the target address in this commands. 1218 1219 If unsure, say Y. 1220 1221config QCOM_FALKOR_ERRATUM_1003 1222 bool "Falkor E1003: Incorrect translation due to ASID change" 1223 default y 1224 help 1225 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1226 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1227 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1228 then only for entries in the walk cache, since the leaf translation 1229 is unchanged. Work around the erratum by invalidating the walk cache 1230 entries for the trampoline before entering the kernel proper. 1231 1232config QCOM_FALKOR_ERRATUM_1009 1233 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1234 default y 1235 select ARM64_WORKAROUND_REPEAT_TLBI 1236 help 1237 On Falkor v1, the CPU may prematurely complete a DSB following a 1238 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1239 one more time to fix the issue. 1240 1241 If unsure, say Y. 1242 1243config QCOM_QDF2400_ERRATUM_0065 1244 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1245 default y 1246 help 1247 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1248 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1249 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1250 1251 If unsure, say Y. 1252 1253config QCOM_FALKOR_ERRATUM_E1041 1254 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1255 default y 1256 help 1257 Falkor CPU may speculatively fetch instructions from an improper 1258 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1259 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1260 1261 If unsure, say Y. 1262 1263config NVIDIA_CARMEL_CNP_ERRATUM 1264 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1265 default y 1266 help 1267 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1268 invalidate shared TLB entries installed by a different core, as it would 1269 on standard ARM cores. 1270 1271 If unsure, say Y. 1272 1273config ROCKCHIP_ERRATUM_3588001 1274 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1275 default y 1276 help 1277 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1278 This means, that its sharability feature may not be used, even though it 1279 is supported by the IP itself. 1280 1281 If unsure, say Y. 1282 1283config SOCIONEXT_SYNQUACER_PREITS 1284 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1285 default y 1286 help 1287 Socionext Synquacer SoCs implement a separate h/w block to generate 1288 MSI doorbell writes with non-zero values for the device ID. 1289 1290 If unsure, say Y. 1291 1292endmenu # "ARM errata workarounds via the alternatives framework" 1293 1294choice 1295 prompt "Page size" 1296 default ARM64_4K_PAGES 1297 help 1298 Page size (translation granule) configuration. 1299 1300config ARM64_4K_PAGES 1301 bool "4KB" 1302 select HAVE_PAGE_SIZE_4KB 1303 help 1304 This feature enables 4KB pages support. 1305 1306config ARM64_16K_PAGES 1307 bool "16KB" 1308 select HAVE_PAGE_SIZE_16KB 1309 help 1310 The system will use 16KB pages support. AArch32 emulation 1311 requires applications compiled with 16K (or a multiple of 16K) 1312 aligned segments. 1313 1314config ARM64_64K_PAGES 1315 bool "64KB" 1316 select HAVE_PAGE_SIZE_64KB 1317 help 1318 This feature enables 64KB pages support (4KB by default) 1319 allowing only two levels of page tables and faster TLB 1320 look-up. AArch32 emulation requires applications compiled 1321 with 64K aligned segments. 1322 1323endchoice 1324 1325choice 1326 prompt "Virtual address space size" 1327 default ARM64_VA_BITS_52 1328 help 1329 Allows choosing one of multiple possible virtual address 1330 space sizes. The level of translation table is determined by 1331 a combination of page size and virtual address space size. 1332 1333config ARM64_VA_BITS_36 1334 bool "36-bit" if EXPERT 1335 depends on PAGE_SIZE_16KB 1336 1337config ARM64_VA_BITS_39 1338 bool "39-bit" 1339 depends on PAGE_SIZE_4KB 1340 1341config ARM64_VA_BITS_42 1342 bool "42-bit" 1343 depends on PAGE_SIZE_64KB 1344 1345config ARM64_VA_BITS_47 1346 bool "47-bit" 1347 depends on PAGE_SIZE_16KB 1348 1349config ARM64_VA_BITS_48 1350 bool "48-bit" 1351 1352config ARM64_VA_BITS_52 1353 bool "52-bit" 1354 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1355 help 1356 Enable 52-bit virtual addressing for userspace when explicitly 1357 requested via a hint to mmap(). The kernel will also use 52-bit 1358 virtual addresses for its own mappings (provided HW support for 1359 this feature is available, otherwise it reverts to 48-bit). 1360 1361 NOTE: Enabling 52-bit virtual addressing in conjunction with 1362 ARMv8.3 Pointer Authentication will result in the PAC being 1363 reduced from 7 bits to 3 bits, which may have a significant 1364 impact on its susceptibility to brute-force attacks. 1365 1366 If unsure, select 48-bit virtual addressing instead. 1367 1368endchoice 1369 1370config ARM64_FORCE_52BIT 1371 bool "Force 52-bit virtual addresses for userspace" 1372 depends on ARM64_VA_BITS_52 && EXPERT 1373 help 1374 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1375 to maintain compatibility with older software by providing 48-bit VAs 1376 unless a hint is supplied to mmap. 1377 1378 This configuration option disables the 48-bit compatibility logic, and 1379 forces all userspace addresses to be 52-bit on HW that supports it. One 1380 should only enable this configuration option for stress testing userspace 1381 memory management code. If unsure say N here. 1382 1383config ARM64_VA_BITS 1384 int 1385 default 36 if ARM64_VA_BITS_36 1386 default 39 if ARM64_VA_BITS_39 1387 default 42 if ARM64_VA_BITS_42 1388 default 47 if ARM64_VA_BITS_47 1389 default 48 if ARM64_VA_BITS_48 1390 default 52 if ARM64_VA_BITS_52 1391 1392choice 1393 prompt "Physical address space size" 1394 default ARM64_PA_BITS_48 1395 help 1396 Choose the maximum physical address range that the kernel will 1397 support. 1398 1399config ARM64_PA_BITS_48 1400 bool "48-bit" 1401 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1402 1403config ARM64_PA_BITS_52 1404 bool "52-bit" 1405 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1406 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1407 help 1408 Enable support for a 52-bit physical address space, introduced as 1409 part of the ARMv8.2-LPA extension. 1410 1411 With this enabled, the kernel will also continue to work on CPUs that 1412 do not support ARMv8.2-LPA, but with some added memory overhead (and 1413 minor performance overhead). 1414 1415endchoice 1416 1417config ARM64_PA_BITS 1418 int 1419 default 48 if ARM64_PA_BITS_48 1420 default 52 if ARM64_PA_BITS_52 1421 1422config ARM64_LPA2 1423 def_bool y 1424 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1425 1426choice 1427 prompt "Endianness" 1428 default CPU_LITTLE_ENDIAN 1429 help 1430 Select the endianness of data accesses performed by the CPU. Userspace 1431 applications will need to be compiled and linked for the endianness 1432 that is selected here. 1433 1434config CPU_BIG_ENDIAN 1435 bool "Build big-endian kernel" 1436 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1437 depends on AS_IS_GNU || AS_VERSION >= 150000 1438 help 1439 Say Y if you plan on running a kernel with a big-endian userspace. 1440 1441config CPU_LITTLE_ENDIAN 1442 bool "Build little-endian kernel" 1443 help 1444 Say Y if you plan on running a kernel with a little-endian userspace. 1445 This is usually the case for distributions targeting arm64. 1446 1447endchoice 1448 1449config SCHED_MC 1450 bool "Multi-core scheduler support" 1451 help 1452 Multi-core scheduler support improves the CPU scheduler's decision 1453 making when dealing with multi-core CPU chips at a cost of slightly 1454 increased overhead in some places. If unsure say N here. 1455 1456config SCHED_CLUSTER 1457 bool "Cluster scheduler support" 1458 help 1459 Cluster scheduler support improves the CPU scheduler's decision 1460 making when dealing with machines that have clusters of CPUs. 1461 Cluster usually means a couple of CPUs which are placed closely 1462 by sharing mid-level caches, last-level cache tags or internal 1463 busses. 1464 1465config SCHED_SMT 1466 bool "SMT scheduler support" 1467 help 1468 Improves the CPU scheduler's decision making when dealing with 1469 MultiThreading at a cost of slightly increased overhead in some 1470 places. If unsure say N here. 1471 1472config NR_CPUS 1473 int "Maximum number of CPUs (2-4096)" 1474 range 2 4096 1475 default "512" 1476 1477config HOTPLUG_CPU 1478 bool "Support for hot-pluggable CPUs" 1479 select GENERIC_IRQ_MIGRATION 1480 help 1481 Say Y here to experiment with turning CPUs off and on. CPUs 1482 can be controlled through /sys/devices/system/cpu. 1483 1484# Common NUMA Features 1485config NUMA 1486 bool "NUMA Memory Allocation and Scheduler Support" 1487 select GENERIC_ARCH_NUMA 1488 select OF_NUMA 1489 select HAVE_SETUP_PER_CPU_AREA 1490 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1491 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1492 select USE_PERCPU_NUMA_NODE_ID 1493 help 1494 Enable NUMA (Non-Uniform Memory Access) support. 1495 1496 The kernel will try to allocate memory used by a CPU on the 1497 local memory of the CPU and add some more 1498 NUMA awareness to the kernel. 1499 1500config NODES_SHIFT 1501 int "Maximum NUMA Nodes (as a power of 2)" 1502 range 1 10 1503 default "4" 1504 depends on NUMA 1505 help 1506 Specify the maximum number of NUMA Nodes available on the target 1507 system. Increases memory reserved to accommodate various tables. 1508 1509source "kernel/Kconfig.hz" 1510 1511config ARCH_SPARSEMEM_ENABLE 1512 def_bool y 1513 select SPARSEMEM_VMEMMAP_ENABLE 1514 select SPARSEMEM_VMEMMAP 1515 1516config HW_PERF_EVENTS 1517 def_bool y 1518 depends on ARM_PMU 1519 1520# Supported by clang >= 7.0 or GCC >= 12.0.0 1521config CC_HAVE_SHADOW_CALL_STACK 1522 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1523 1524config PARAVIRT 1525 bool "Enable paravirtualization code" 1526 help 1527 This changes the kernel so it can modify itself when it is run 1528 under a hypervisor, potentially improving performance significantly 1529 over full virtualization. 1530 1531config PARAVIRT_TIME_ACCOUNTING 1532 bool "Paravirtual steal time accounting" 1533 select PARAVIRT 1534 help 1535 Select this option to enable fine granularity task steal time 1536 accounting. Time spent executing other tasks in parallel with 1537 the current vCPU is discounted from the vCPU power. To account for 1538 that, there can be a small performance impact. 1539 1540 If in doubt, say N here. 1541 1542config ARCH_SUPPORTS_KEXEC 1543 def_bool PM_SLEEP_SMP 1544 1545config ARCH_SUPPORTS_KEXEC_FILE 1546 def_bool y 1547 1548config ARCH_SELECTS_KEXEC_FILE 1549 def_bool y 1550 depends on KEXEC_FILE 1551 select HAVE_IMA_KEXEC if IMA 1552 1553config ARCH_SUPPORTS_KEXEC_SIG 1554 def_bool y 1555 1556config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1557 def_bool y 1558 1559config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1560 def_bool y 1561 1562config ARCH_SUPPORTS_CRASH_DUMP 1563 def_bool y 1564 1565config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1566 def_bool CRASH_RESERVE 1567 1568config TRANS_TABLE 1569 def_bool y 1570 depends on HIBERNATION || KEXEC_CORE 1571 1572config XEN_DOM0 1573 def_bool y 1574 depends on XEN 1575 1576config XEN 1577 bool "Xen guest support on ARM64" 1578 depends on ARM64 && OF 1579 select SWIOTLB_XEN 1580 select PARAVIRT 1581 help 1582 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1583 1584# include/linux/mmzone.h requires the following to be true: 1585# 1586# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1587# 1588# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1589# 1590# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1591# ----+-------------------+--------------+----------------------+-------------------------+ 1592# 4K | 27 | 12 | 15 | 10 | 1593# 16K | 27 | 14 | 13 | 11 | 1594# 64K | 29 | 16 | 13 | 13 | 1595config ARCH_FORCE_MAX_ORDER 1596 int 1597 default "13" if ARM64_64K_PAGES 1598 default "11" if ARM64_16K_PAGES 1599 default "10" 1600 help 1601 The kernel page allocator limits the size of maximal physically 1602 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1603 defines the maximal power of two of number of pages that can be 1604 allocated as a single contiguous block. This option allows 1605 overriding the default setting when ability to allocate very 1606 large blocks of physically contiguous memory is required. 1607 1608 The maximal size of allocation cannot exceed the size of the 1609 section, so the value of MAX_PAGE_ORDER should satisfy 1610 1611 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1612 1613 Don't change if unsure. 1614 1615config UNMAP_KERNEL_AT_EL0 1616 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1617 default y 1618 help 1619 Speculation attacks against some high-performance processors can 1620 be used to bypass MMU permission checks and leak kernel data to 1621 userspace. This can be defended against by unmapping the kernel 1622 when running in userspace, mapping it back in on exception entry 1623 via a trampoline page in the vector table. 1624 1625 If unsure, say Y. 1626 1627config MITIGATE_SPECTRE_BRANCH_HISTORY 1628 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1629 default y 1630 help 1631 Speculation attacks against some high-performance processors can 1632 make use of branch history to influence future speculation. 1633 When taking an exception from user-space, a sequence of branches 1634 or a firmware call overwrites the branch history. 1635 1636config RODATA_FULL_DEFAULT_ENABLED 1637 bool "Apply r/o permissions of VM areas also to their linear aliases" 1638 default y 1639 help 1640 Apply read-only attributes of VM areas to the linear alias of 1641 the backing pages as well. This prevents code or read-only data 1642 from being modified (inadvertently or intentionally) via another 1643 mapping of the same memory page. This additional enhancement can 1644 be turned off at runtime by passing rodata=[off|on] (and turned on 1645 with rodata=full if this option is set to 'n') 1646 1647 This requires the linear region to be mapped down to pages, 1648 which may adversely affect performance in some cases. 1649 1650config ARM64_SW_TTBR0_PAN 1651 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1652 depends on !KCSAN 1653 help 1654 Enabling this option prevents the kernel from accessing 1655 user-space memory directly by pointing TTBR0_EL1 to a reserved 1656 zeroed area and reserved ASID. The user access routines 1657 restore the valid TTBR0_EL1 temporarily. 1658 1659config ARM64_TAGGED_ADDR_ABI 1660 bool "Enable the tagged user addresses syscall ABI" 1661 default y 1662 help 1663 When this option is enabled, user applications can opt in to a 1664 relaxed ABI via prctl() allowing tagged addresses to be passed 1665 to system calls as pointer arguments. For details, see 1666 Documentation/arch/arm64/tagged-address-abi.rst. 1667 1668menuconfig COMPAT 1669 bool "Kernel support for 32-bit EL0" 1670 depends on ARM64_4K_PAGES || EXPERT 1671 select HAVE_UID16 1672 select OLD_SIGSUSPEND3 1673 select COMPAT_OLD_SIGACTION 1674 help 1675 This option enables support for a 32-bit EL0 running under a 64-bit 1676 kernel at EL1. AArch32-specific components such as system calls, 1677 the user helper functions, VFP support and the ptrace interface are 1678 handled appropriately by the kernel. 1679 1680 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1681 that you will only be able to execute AArch32 binaries that were compiled 1682 with page size aligned segments. 1683 1684 If you want to execute 32-bit userspace applications, say Y. 1685 1686if COMPAT 1687 1688config KUSER_HELPERS 1689 bool "Enable kuser helpers page for 32-bit applications" 1690 default y 1691 help 1692 Warning: disabling this option may break 32-bit user programs. 1693 1694 Provide kuser helpers to compat tasks. The kernel provides 1695 helper code to userspace in read only form at a fixed location 1696 to allow userspace to be independent of the CPU type fitted to 1697 the system. This permits binaries to be run on ARMv4 through 1698 to ARMv8 without modification. 1699 1700 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1701 1702 However, the fixed address nature of these helpers can be used 1703 by ROP (return orientated programming) authors when creating 1704 exploits. 1705 1706 If all of the binaries and libraries which run on your platform 1707 are built specifically for your platform, and make no use of 1708 these helpers, then you can turn this option off to hinder 1709 such exploits. However, in that case, if a binary or library 1710 relying on those helpers is run, it will not function correctly. 1711 1712 Say N here only if you are absolutely certain that you do not 1713 need these helpers; otherwise, the safe option is to say Y. 1714 1715config COMPAT_VDSO 1716 bool "Enable vDSO for 32-bit applications" 1717 depends on !CPU_BIG_ENDIAN 1718 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1719 select GENERIC_COMPAT_VDSO 1720 default y 1721 help 1722 Place in the process address space of 32-bit applications an 1723 ELF shared object providing fast implementations of gettimeofday 1724 and clock_gettime. 1725 1726 You must have a 32-bit build of glibc 2.22 or later for programs 1727 to seamlessly take advantage of this. 1728 1729config THUMB2_COMPAT_VDSO 1730 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1731 depends on COMPAT_VDSO 1732 default y 1733 help 1734 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1735 otherwise with '-marm'. 1736 1737config COMPAT_ALIGNMENT_FIXUPS 1738 bool "Fix up misaligned multi-word loads and stores in user space" 1739 1740menuconfig ARMV8_DEPRECATED 1741 bool "Emulate deprecated/obsolete ARMv8 instructions" 1742 depends on SYSCTL 1743 help 1744 Legacy software support may require certain instructions 1745 that have been deprecated or obsoleted in the architecture. 1746 1747 Enable this config to enable selective emulation of these 1748 features. 1749 1750 If unsure, say Y 1751 1752if ARMV8_DEPRECATED 1753 1754config SWP_EMULATION 1755 bool "Emulate SWP/SWPB instructions" 1756 help 1757 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1758 they are always undefined. Say Y here to enable software 1759 emulation of these instructions for userspace using LDXR/STXR. 1760 This feature can be controlled at runtime with the abi.swp 1761 sysctl which is disabled by default. 1762 1763 In some older versions of glibc [<=2.8] SWP is used during futex 1764 trylock() operations with the assumption that the code will not 1765 be preempted. This invalid assumption may be more likely to fail 1766 with SWP emulation enabled, leading to deadlock of the user 1767 application. 1768 1769 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1770 on an external transaction monitoring block called a global 1771 monitor to maintain update atomicity. If your system does not 1772 implement a global monitor, this option can cause programs that 1773 perform SWP operations to uncached memory to deadlock. 1774 1775 If unsure, say Y 1776 1777config CP15_BARRIER_EMULATION 1778 bool "Emulate CP15 Barrier instructions" 1779 help 1780 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1781 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1782 strongly recommended to use the ISB, DSB, and DMB 1783 instructions instead. 1784 1785 Say Y here to enable software emulation of these 1786 instructions for AArch32 userspace code. When this option is 1787 enabled, CP15 barrier usage is traced which can help 1788 identify software that needs updating. This feature can be 1789 controlled at runtime with the abi.cp15_barrier sysctl. 1790 1791 If unsure, say Y 1792 1793config SETEND_EMULATION 1794 bool "Emulate SETEND instruction" 1795 help 1796 The SETEND instruction alters the data-endianness of the 1797 AArch32 EL0, and is deprecated in ARMv8. 1798 1799 Say Y here to enable software emulation of the instruction 1800 for AArch32 userspace code. This feature can be controlled 1801 at runtime with the abi.setend sysctl. 1802 1803 Note: All the cpus on the system must have mixed endian support at EL0 1804 for this feature to be enabled. If a new CPU - which doesn't support mixed 1805 endian - is hotplugged in after this feature has been enabled, there could 1806 be unexpected results in the applications. 1807 1808 If unsure, say Y 1809endif # ARMV8_DEPRECATED 1810 1811endif # COMPAT 1812 1813menu "ARMv8.1 architectural features" 1814 1815config ARM64_HW_AFDBM 1816 bool "Support for hardware updates of the Access and Dirty page flags" 1817 default y 1818 help 1819 The ARMv8.1 architecture extensions introduce support for 1820 hardware updates of the access and dirty information in page 1821 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1822 capable processors, accesses to pages with PTE_AF cleared will 1823 set this bit instead of raising an access flag fault. 1824 Similarly, writes to read-only pages with the DBM bit set will 1825 clear the read-only bit (AP[2]) instead of raising a 1826 permission fault. 1827 1828 Kernels built with this configuration option enabled continue 1829 to work on pre-ARMv8.1 hardware and the performance impact is 1830 minimal. If unsure, say Y. 1831 1832config ARM64_PAN 1833 bool "Enable support for Privileged Access Never (PAN)" 1834 default y 1835 help 1836 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1837 prevents the kernel or hypervisor from accessing user-space (EL0) 1838 memory directly. 1839 1840 Choosing this option will cause any unprotected (not using 1841 copy_to_user et al) memory access to fail with a permission fault. 1842 1843 The feature is detected at runtime, and will remain as a 'nop' 1844 instruction if the cpu does not implement the feature. 1845 1846config AS_HAS_LSE_ATOMICS 1847 def_bool $(as-instr,.arch_extension lse) 1848 1849config ARM64_LSE_ATOMICS 1850 bool 1851 default ARM64_USE_LSE_ATOMICS 1852 depends on AS_HAS_LSE_ATOMICS 1853 1854config ARM64_USE_LSE_ATOMICS 1855 bool "Atomic instructions" 1856 default y 1857 help 1858 As part of the Large System Extensions, ARMv8.1 introduces new 1859 atomic instructions that are designed specifically to scale in 1860 very large systems. 1861 1862 Say Y here to make use of these instructions for the in-kernel 1863 atomic routines. This incurs a small overhead on CPUs that do 1864 not support these instructions and requires the kernel to be 1865 built with binutils >= 2.25 in order for the new instructions 1866 to be used. 1867 1868endmenu # "ARMv8.1 architectural features" 1869 1870menu "ARMv8.2 architectural features" 1871 1872config AS_HAS_ARMV8_2 1873 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1874 1875config AS_HAS_SHA3 1876 def_bool $(as-instr,.arch armv8.2-a+sha3) 1877 1878config ARM64_PMEM 1879 bool "Enable support for persistent memory" 1880 select ARCH_HAS_PMEM_API 1881 select ARCH_HAS_UACCESS_FLUSHCACHE 1882 help 1883 Say Y to enable support for the persistent memory API based on the 1884 ARMv8.2 DCPoP feature. 1885 1886 The feature is detected at runtime, and the kernel will use DC CVAC 1887 operations if DC CVAP is not supported (following the behaviour of 1888 DC CVAP itself if the system does not define a point of persistence). 1889 1890config ARM64_RAS_EXTN 1891 bool "Enable support for RAS CPU Extensions" 1892 default y 1893 help 1894 CPUs that support the Reliability, Availability and Serviceability 1895 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1896 errors, classify them and report them to software. 1897 1898 On CPUs with these extensions system software can use additional 1899 barriers to determine if faults are pending and read the 1900 classification from a new set of registers. 1901 1902 Selecting this feature will allow the kernel to use these barriers 1903 and access the new registers if the system supports the extension. 1904 Platform RAS features may additionally depend on firmware support. 1905 1906config ARM64_CNP 1907 bool "Enable support for Common Not Private (CNP) translations" 1908 default y 1909 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1910 help 1911 Common Not Private (CNP) allows translation table entries to 1912 be shared between different PEs in the same inner shareable 1913 domain, so the hardware can use this fact to optimise the 1914 caching of such entries in the TLB. 1915 1916 Selecting this option allows the CNP feature to be detected 1917 at runtime, and does not affect PEs that do not implement 1918 this feature. 1919 1920endmenu # "ARMv8.2 architectural features" 1921 1922menu "ARMv8.3 architectural features" 1923 1924config ARM64_PTR_AUTH 1925 bool "Enable support for pointer authentication" 1926 default y 1927 help 1928 Pointer authentication (part of the ARMv8.3 Extensions) provides 1929 instructions for signing and authenticating pointers against secret 1930 keys, which can be used to mitigate Return Oriented Programming (ROP) 1931 and other attacks. 1932 1933 This option enables these instructions at EL0 (i.e. for userspace). 1934 Choosing this option will cause the kernel to initialise secret keys 1935 for each process at exec() time, with these keys being 1936 context-switched along with the process. 1937 1938 The feature is detected at runtime. If the feature is not present in 1939 hardware it will not be advertised to userspace/KVM guest nor will it 1940 be enabled. 1941 1942 If the feature is present on the boot CPU but not on a late CPU, then 1943 the late CPU will be parked. Also, if the boot CPU does not have 1944 address auth and the late CPU has then the late CPU will still boot 1945 but with the feature disabled. On such a system, this option should 1946 not be selected. 1947 1948config ARM64_PTR_AUTH_KERNEL 1949 bool "Use pointer authentication for kernel" 1950 default y 1951 depends on ARM64_PTR_AUTH 1952 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1953 # Modern compilers insert a .note.gnu.property section note for PAC 1954 # which is only understood by binutils starting with version 2.33.1. 1955 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1956 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1957 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1958 help 1959 If the compiler supports the -mbranch-protection or 1960 -msign-return-address flag (e.g. GCC 7 or later), then this option 1961 will cause the kernel itself to be compiled with return address 1962 protection. In this case, and if the target hardware is known to 1963 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1964 disabled with minimal loss of protection. 1965 1966 This feature works with FUNCTION_GRAPH_TRACER option only if 1967 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1968 1969config CC_HAS_BRANCH_PROT_PAC_RET 1970 # GCC 9 or later, clang 8 or later 1971 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1972 1973config CC_HAS_SIGN_RETURN_ADDRESS 1974 # GCC 7, 8 1975 def_bool $(cc-option,-msign-return-address=all) 1976 1977config AS_HAS_ARMV8_3 1978 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1979 1980config AS_HAS_CFI_NEGATE_RA_STATE 1981 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1982 1983config AS_HAS_LDAPR 1984 def_bool $(as-instr,.arch_extension rcpc) 1985 1986endmenu # "ARMv8.3 architectural features" 1987 1988menu "ARMv8.4 architectural features" 1989 1990config ARM64_AMU_EXTN 1991 bool "Enable support for the Activity Monitors Unit CPU extension" 1992 default y 1993 help 1994 The activity monitors extension is an optional extension introduced 1995 by the ARMv8.4 CPU architecture. This enables support for version 1 1996 of the activity monitors architecture, AMUv1. 1997 1998 To enable the use of this extension on CPUs that implement it, say Y. 1999 2000 Note that for architectural reasons, firmware _must_ implement AMU 2001 support when running on CPUs that present the activity monitors 2002 extension. The required support is present in: 2003 * Version 1.5 and later of the ARM Trusted Firmware 2004 2005 For kernels that have this configuration enabled but boot with broken 2006 firmware, you may need to say N here until the firmware is fixed. 2007 Otherwise you may experience firmware panics or lockups when 2008 accessing the counter registers. Even if you are not observing these 2009 symptoms, the values returned by the register reads might not 2010 correctly reflect reality. Most commonly, the value read will be 0, 2011 indicating that the counter is not enabled. 2012 2013config AS_HAS_ARMV8_4 2014 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2015 2016config ARM64_TLB_RANGE 2017 bool "Enable support for tlbi range feature" 2018 default y 2019 depends on AS_HAS_ARMV8_4 2020 help 2021 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2022 range of input addresses. 2023 2024 The feature introduces new assembly instructions, and they were 2025 support when binutils >= 2.30. 2026 2027endmenu # "ARMv8.4 architectural features" 2028 2029menu "ARMv8.5 architectural features" 2030 2031config AS_HAS_ARMV8_5 2032 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2033 2034config ARM64_BTI 2035 bool "Branch Target Identification support" 2036 default y 2037 help 2038 Branch Target Identification (part of the ARMv8.5 Extensions) 2039 provides a mechanism to limit the set of locations to which computed 2040 branch instructions such as BR or BLR can jump. 2041 2042 To make use of BTI on CPUs that support it, say Y. 2043 2044 BTI is intended to provide complementary protection to other control 2045 flow integrity protection mechanisms, such as the Pointer 2046 authentication mechanism provided as part of the ARMv8.3 Extensions. 2047 For this reason, it does not make sense to enable this option without 2048 also enabling support for pointer authentication. Thus, when 2049 enabling this option you should also select ARM64_PTR_AUTH=y. 2050 2051 Userspace binaries must also be specifically compiled to make use of 2052 this mechanism. If you say N here or the hardware does not support 2053 BTI, such binaries can still run, but you get no additional 2054 enforcement of branch destinations. 2055 2056config ARM64_BTI_KERNEL 2057 bool "Use Branch Target Identification for kernel" 2058 default y 2059 depends on ARM64_BTI 2060 depends on ARM64_PTR_AUTH_KERNEL 2061 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2062 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2063 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2064 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2065 depends on !CC_IS_GCC 2066 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2067 help 2068 Build the kernel with Branch Target Identification annotations 2069 and enable enforcement of this for kernel code. When this option 2070 is enabled and the system supports BTI all kernel code including 2071 modular code must have BTI enabled. 2072 2073config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2074 # GCC 9 or later, clang 8 or later 2075 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2076 2077config ARM64_E0PD 2078 bool "Enable support for E0PD" 2079 default y 2080 help 2081 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2082 that EL0 accesses made via TTBR1 always fault in constant time, 2083 providing similar benefits to KASLR as those provided by KPTI, but 2084 with lower overhead and without disrupting legitimate access to 2085 kernel memory such as SPE. 2086 2087 This option enables E0PD for TTBR1 where available. 2088 2089config ARM64_AS_HAS_MTE 2090 # Initial support for MTE went in binutils 2.32.0, checked with 2091 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2092 # as a late addition to the final architecture spec (LDGM/STGM) 2093 # is only supported in the newer 2.32.x and 2.33 binutils 2094 # versions, hence the extra "stgm" instruction check below. 2095 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2096 2097config ARM64_MTE 2098 bool "Memory Tagging Extension support" 2099 default y 2100 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2101 depends on AS_HAS_ARMV8_5 2102 depends on AS_HAS_LSE_ATOMICS 2103 # Required for tag checking in the uaccess routines 2104 depends on ARM64_PAN 2105 select ARCH_HAS_SUBPAGE_FAULTS 2106 select ARCH_USES_HIGH_VMA_FLAGS 2107 select ARCH_USES_PG_ARCH_X 2108 help 2109 Memory Tagging (part of the ARMv8.5 Extensions) provides 2110 architectural support for run-time, always-on detection of 2111 various classes of memory error to aid with software debugging 2112 to eliminate vulnerabilities arising from memory-unsafe 2113 languages. 2114 2115 This option enables the support for the Memory Tagging 2116 Extension at EL0 (i.e. for userspace). 2117 2118 Selecting this option allows the feature to be detected at 2119 runtime. Any secondary CPU not implementing this feature will 2120 not be allowed a late bring-up. 2121 2122 Userspace binaries that want to use this feature must 2123 explicitly opt in. The mechanism for the userspace is 2124 described in: 2125 2126 Documentation/arch/arm64/memory-tagging-extension.rst. 2127 2128endmenu # "ARMv8.5 architectural features" 2129 2130menu "ARMv8.7 architectural features" 2131 2132config ARM64_EPAN 2133 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2134 default y 2135 depends on ARM64_PAN 2136 help 2137 Enhanced Privileged Access Never (EPAN) allows Privileged 2138 Access Never to be used with Execute-only mappings. 2139 2140 The feature is detected at runtime, and will remain disabled 2141 if the cpu does not implement the feature. 2142endmenu # "ARMv8.7 architectural features" 2143 2144menu "ARMv8.9 architectural features" 2145 2146config ARM64_POE 2147 prompt "Permission Overlay Extension" 2148 def_bool y 2149 select ARCH_USES_HIGH_VMA_FLAGS 2150 select ARCH_HAS_PKEYS 2151 help 2152 The Permission Overlay Extension is used to implement Memory 2153 Protection Keys. Memory Protection Keys provides a mechanism for 2154 enforcing page-based protections, but without requiring modification 2155 of the page tables when an application changes protection domains. 2156 2157 For details, see Documentation/core-api/protection-keys.rst 2158 2159 If unsure, say y. 2160 2161config ARCH_PKEY_BITS 2162 int 2163 default 3 2164 2165endmenu # "ARMv8.9 architectural features" 2166 2167config ARM64_SVE 2168 bool "ARM Scalable Vector Extension support" 2169 default y 2170 help 2171 The Scalable Vector Extension (SVE) is an extension to the AArch64 2172 execution state which complements and extends the SIMD functionality 2173 of the base architecture to support much larger vectors and to enable 2174 additional vectorisation opportunities. 2175 2176 To enable use of this extension on CPUs that implement it, say Y. 2177 2178 On CPUs that support the SVE2 extensions, this option will enable 2179 those too. 2180 2181 Note that for architectural reasons, firmware _must_ implement SVE 2182 support when running on SVE capable hardware. The required support 2183 is present in: 2184 2185 * version 1.5 and later of the ARM Trusted Firmware 2186 * the AArch64 boot wrapper since commit 5e1261e08abf 2187 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2188 2189 For other firmware implementations, consult the firmware documentation 2190 or vendor. 2191 2192 If you need the kernel to boot on SVE-capable hardware with broken 2193 firmware, you may need to say N here until you get your firmware 2194 fixed. Otherwise, you may experience firmware panics or lockups when 2195 booting the kernel. If unsure and you are not observing these 2196 symptoms, you should assume that it is safe to say Y. 2197 2198config ARM64_SME 2199 bool "ARM Scalable Matrix Extension support" 2200 default y 2201 depends on ARM64_SVE 2202 help 2203 The Scalable Matrix Extension (SME) is an extension to the AArch64 2204 execution state which utilises a substantial subset of the SVE 2205 instruction set, together with the addition of new architectural 2206 register state capable of holding two dimensional matrix tiles to 2207 enable various matrix operations. 2208 2209config ARM64_PSEUDO_NMI 2210 bool "Support for NMI-like interrupts" 2211 select ARM_GIC_V3 2212 help 2213 Adds support for mimicking Non-Maskable Interrupts through the use of 2214 GIC interrupt priority. This support requires version 3 or later of 2215 ARM GIC. 2216 2217 This high priority configuration for interrupts needs to be 2218 explicitly enabled by setting the kernel parameter 2219 "irqchip.gicv3_pseudo_nmi" to 1. 2220 2221 If unsure, say N 2222 2223if ARM64_PSEUDO_NMI 2224config ARM64_DEBUG_PRIORITY_MASKING 2225 bool "Debug interrupt priority masking" 2226 help 2227 This adds runtime checks to functions enabling/disabling 2228 interrupts when using priority masking. The additional checks verify 2229 the validity of ICC_PMR_EL1 when calling concerned functions. 2230 2231 If unsure, say N 2232endif # ARM64_PSEUDO_NMI 2233 2234config RELOCATABLE 2235 bool "Build a relocatable kernel image" if EXPERT 2236 select ARCH_HAS_RELR 2237 default y 2238 help 2239 This builds the kernel as a Position Independent Executable (PIE), 2240 which retains all relocation metadata required to relocate the 2241 kernel binary at runtime to a different virtual address than the 2242 address it was linked at. 2243 Since AArch64 uses the RELA relocation format, this requires a 2244 relocation pass at runtime even if the kernel is loaded at the 2245 same address it was linked at. 2246 2247config RANDOMIZE_BASE 2248 bool "Randomize the address of the kernel image" 2249 select RELOCATABLE 2250 help 2251 Randomizes the virtual address at which the kernel image is 2252 loaded, as a security feature that deters exploit attempts 2253 relying on knowledge of the location of kernel internals. 2254 2255 It is the bootloader's job to provide entropy, by passing a 2256 random u64 value in /chosen/kaslr-seed at kernel entry. 2257 2258 When booting via the UEFI stub, it will invoke the firmware's 2259 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2260 to the kernel proper. In addition, it will randomise the physical 2261 location of the kernel Image as well. 2262 2263 If unsure, say N. 2264 2265config RANDOMIZE_MODULE_REGION_FULL 2266 bool "Randomize the module region over a 2 GB range" 2267 depends on RANDOMIZE_BASE 2268 default y 2269 help 2270 Randomizes the location of the module region inside a 2 GB window 2271 covering the core kernel. This way, it is less likely for modules 2272 to leak information about the location of core kernel data structures 2273 but it does imply that function calls between modules and the core 2274 kernel will need to be resolved via veneers in the module PLT. 2275 2276 When this option is not set, the module region will be randomized over 2277 a limited range that contains the [_stext, _etext] interval of the 2278 core kernel, so branch relocations are almost always in range unless 2279 the region is exhausted. In this particular case of region 2280 exhaustion, modules might be able to fall back to a larger 2GB area. 2281 2282config CC_HAVE_STACKPROTECTOR_SYSREG 2283 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2284 2285config STACKPROTECTOR_PER_TASK 2286 def_bool y 2287 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2288 2289config UNWIND_PATCH_PAC_INTO_SCS 2290 bool "Enable shadow call stack dynamically using code patching" 2291 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2292 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2293 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2294 depends on SHADOW_CALL_STACK 2295 select UNWIND_TABLES 2296 select DYNAMIC_SCS 2297 2298config ARM64_CONTPTE 2299 bool "Contiguous PTE mappings for user memory" if EXPERT 2300 depends on TRANSPARENT_HUGEPAGE 2301 default y 2302 help 2303 When enabled, user mappings are configured using the PTE contiguous 2304 bit, for any mappings that meet the size and alignment requirements. 2305 This reduces TLB pressure and improves performance. 2306 2307endmenu # "Kernel Features" 2308 2309menu "Boot options" 2310 2311config ARM64_ACPI_PARKING_PROTOCOL 2312 bool "Enable support for the ARM64 ACPI parking protocol" 2313 depends on ACPI 2314 help 2315 Enable support for the ARM64 ACPI parking protocol. If disabled 2316 the kernel will not allow booting through the ARM64 ACPI parking 2317 protocol even if the corresponding data is present in the ACPI 2318 MADT table. 2319 2320config CMDLINE 2321 string "Default kernel command string" 2322 default "" 2323 help 2324 Provide a set of default command-line options at build time by 2325 entering them here. As a minimum, you should specify the the 2326 root device (e.g. root=/dev/nfs). 2327 2328choice 2329 prompt "Kernel command line type" 2330 depends on CMDLINE != "" 2331 default CMDLINE_FROM_BOOTLOADER 2332 help 2333 Choose how the kernel will handle the provided default kernel 2334 command line string. 2335 2336config CMDLINE_FROM_BOOTLOADER 2337 bool "Use bootloader kernel arguments if available" 2338 help 2339 Uses the command-line options passed by the boot loader. If 2340 the boot loader doesn't provide any, the default kernel command 2341 string provided in CMDLINE will be used. 2342 2343config CMDLINE_FORCE 2344 bool "Always use the default kernel command string" 2345 help 2346 Always use the default kernel command string, even if the boot 2347 loader passes other arguments to the kernel. 2348 This is useful if you cannot or don't want to change the 2349 command-line options your boot loader passes to the kernel. 2350 2351endchoice 2352 2353config EFI_STUB 2354 bool 2355 2356config EFI 2357 bool "UEFI runtime support" 2358 depends on OF && !CPU_BIG_ENDIAN 2359 depends on KERNEL_MODE_NEON 2360 select ARCH_SUPPORTS_ACPI 2361 select LIBFDT 2362 select UCS2_STRING 2363 select EFI_PARAMS_FROM_FDT 2364 select EFI_RUNTIME_WRAPPERS 2365 select EFI_STUB 2366 select EFI_GENERIC_STUB 2367 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2368 default y 2369 help 2370 This option provides support for runtime services provided 2371 by UEFI firmware (such as non-volatile variables, realtime 2372 clock, and platform reset). A UEFI stub is also provided to 2373 allow the kernel to be booted as an EFI application. This 2374 is only useful on systems that have UEFI firmware. 2375 2376config COMPRESSED_INSTALL 2377 bool "Install compressed image by default" 2378 help 2379 This makes the regular "make install" install the compressed 2380 image we built, not the legacy uncompressed one. 2381 2382 You can check that a compressed image works for you by doing 2383 "make zinstall" first, and verifying that everything is fine 2384 in your environment before making "make install" do this for 2385 you. 2386 2387config DMI 2388 bool "Enable support for SMBIOS (DMI) tables" 2389 depends on EFI 2390 default y 2391 help 2392 This enables SMBIOS/DMI feature for systems. 2393 2394 This option is only useful on systems that have UEFI firmware. 2395 However, even with this option, the resultant kernel should 2396 continue to boot on existing non-UEFI platforms. 2397 2398endmenu # "Boot options" 2399 2400menu "Power management options" 2401 2402source "kernel/power/Kconfig" 2403 2404config ARCH_HIBERNATION_POSSIBLE 2405 def_bool y 2406 depends on CPU_PM 2407 2408config ARCH_HIBERNATION_HEADER 2409 def_bool y 2410 depends on HIBERNATION 2411 2412config ARCH_SUSPEND_POSSIBLE 2413 def_bool y 2414 2415endmenu # "Power management options" 2416 2417menu "CPU Power Management" 2418 2419source "drivers/cpuidle/Kconfig" 2420 2421source "drivers/cpufreq/Kconfig" 2422 2423endmenu # "CPU Power Management" 2424 2425source "drivers/acpi/Kconfig" 2426 2427source "arch/arm64/kvm/Kconfig" 2428 2429