xref: /illumos-gate/usr/src/uts/intel/io/scsi/adapters/arcmsr/arcmsr.h (revision 7d14b8f218dc86a431d15e352b4bf15fbb1b3596)
1 /*
2  *
3  *	  O.S	: Solaris
4  *	FILE NAME  : arcmsr.h
5  *	  BY	: Erich Chen
6  *	Description: SCSI RAID Device Driver for
7  *			ARECA RAID Host adapter
8  *
9  * Copyright (C) 2002,2007 Areca Technology Corporation All rights reserved.
10  * Copyright (C) 2002,2007 Erich Chen
11  *		Web site: www.areca.com.tw
12  *		E-mail: erich@areca.com.tw
13  *
14  *	Redistribution and use in source and binary forms, with or without
15  *	modification, are permitted provided that the following conditions
16  *	are met:
17  *	1. Redistributions of source code must retain the above copyright
18  *	 notice, this list of conditions and the following disclaimer.
19  *	2. Redistributions in binary form must reproduce the above copyright
20  *	 notice, this list of conditions and the following disclaimer in the
21  *	 documentation and/or other materials provided with the distribution.
22  *	3. The party using or redistributing the source code and binary forms
23  *	 agrees to the disclaimer below and the terms and conditions set forth
24  *	 herein.
25  *
26  *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27  *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29  *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
30  *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31  *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32  *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  *  SUCH DAMAGE.
37  *
38  */
39 /*
40  * CDDL HEADER START
41  *
42  * The contents of this file are subject to the terms of the
43  * Common Development and Distribution License (the "License").
44  * You may not use this file except in compliance with the License.
45  *
46  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
47  * or http://www.opensolaris.org/os/licensing.
48  * See the License for the specific language governing permissions
49  * and limitations under the License.
50  *
51  * When distributing Covered Code, include this CDDL HEADER in each
52  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
53  * If applicable, add the following below this CDDL HEADER, with the
54  * fields enclosed by brackets "[]" replaced with your own identifying
55  * information: Portions Copyright [yyyy] [name of copyright owner]
56  *
57  * CDDL HEADER END
58  */
59 /*
60  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
61  * Use is subject to license terms.
62  */
63 /*
64  * Copyright 2011 Nexenta Systems, Inc.  All rights reserved.
65  */
66 
67 #ifndef _SYS_SCSI_ADAPTERS_ARCMSR_H
68 #define	_SYS_SCSI_ADAPTERS_ARCMSR_H
69 
70 #ifdef	__cplusplus
71 	extern "C" {
72 #endif
73 
74 #include <sys/sysmacros.h>
75 
76 #ifndef	TRUE
77 #define	TRUE	1
78 #define	FALSE	0
79 #endif
80 
81 
82 typedef	struct	CCB		*PCCB;
83 typedef	struct	ACB		*PACB;
84 
85 #define	ARCMSR_SCSI_INITIATOR_ID	255
86 #define	ARCMSR_DEV_SECTOR_SIZE		512
87 #define	ARCMSR_MAX_XFER_SECTORS		256
88 #define	ARCMSR_MAX_SG_ENTRIES		38		/* max 38 */
89 #define	ARCMSR_MAX_XFER_LEN		0x00200000 /* 2M */
90 #define	ARCMSR_MAX_TARGETID		17		/* 0-16 */
91 #define	ARCMSR_MAX_TARGETLUN		8		/* 0-7 */
92 #define	ARCMSR_MAX_DPC			16	/* defer procedure call */
93 #define	ARCMSR_MAX_QBUFFER		4096	/* ioctl QBUFFER */
94 #define	ARCMSR_MAX_HBB_POSTQUEUE	264	/* MAX_OUTSTANDING_CMD+8 */
95 
96 #define	ARCMSR_MAX_OUTSTANDING_CMD	256
97 #define	ARCMSR_MAX_FREECCB_NUM		384
98 #define	ARCMSR_TIMEOUT_WATCH		60
99 #define	ARCMSR_DEV_MAP_WATCH		5
100 #define	ARCMSR_CCB_EXPIRED_TIME		600		/* 10 min */
101 
102 #define	CHIP_REG_READ8(handle, a)	\
103 	(ddi_get8(handle, (uint8_t *)(a)))
104 #define	CHIP_REG_READ16(handle, a)	\
105 	(ddi_get16(handle, (uint16_t *)(a)))
106 #define	CHIP_REG_READ32(handle, a)	\
107 	(ddi_get32(handle, (uint32_t *)(a)))
108 #define	CHIP_REG_READ64(handle, a)	\
109 	(ddi_get64(handle, (uint64_t *)(a)))
110 #define	CHIP_REG_WRITE8(handle, a, d)	\
111 	ddi_put8(handle, (uint8_t *)(a), (uint8_t)(d))
112 #define	CHIP_REG_WRITE16(handle, a, d)	\
113 	ddi_put16(handle, (uint16_t *)(a), (uint16_t)(d))
114 #define	CHIP_REG_WRITE32(handle, a, d)	\
115 	ddi_put32(handle, (uint32_t *)(a), (uint32_t)(d))
116 #define	CHIP_REG_WRITE64(handle, a, d)	\
117 	ddi_put64(handle, (uint64_t *)(a), (uint64_t)(d))
118 
119 
120 /* NOTE: GETG4ADDRTL(cdbp) is int32_t */
121 #define	ARCMSR_GETGXADDR(cmdlen, cdbp) \
122 	((cmdlen == 6) ? GETG0ADDR(cdbp) : \
123 	(cmdlen == 10) ? (uint32_t)GETG1ADDR(cdbp) : \
124 	((uint64_t)GETG4ADDR(cdbp) << 32) | (uint32_t)GETG4ADDRTL(cdbp))
125 
126 #define	PCI_VENDOR_ID_ARECA	 0x17D3	/* Vendor ID	*/
127 #define	PCI_DEVICE_ID_ARECA_1110 0x1110	/* Device ID	*/
128 #define	PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID	*/
129 #define	PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID	*/
130 #define	PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID	*/
131 #define	PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID	*/
132 #define	PCI_DEVICE_ID_ARECA_1210 0x1210	/* Device ID	*/
133 #define	PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID	*/
134 #define	PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID	*/
135 #define	PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID	*/
136 #define	PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID	*/
137 #define	PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID	*/
138 #define	PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID	*/
139 #define	PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID	*/
140 #define	PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID	*/
141 #define	PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID	*/
142 #define	PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID	*/
143 #define	PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID	*/
144 #define	PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID	*/
145 #define	PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID	*/
146 #define	PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID	*/
147 #define	PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID	*/
148 #define	PCI_DEVICE_ID_ARECA_1882 0x1882 /* Device ID	*/
149 
150 #define	dma_addr_hi32(addr)	(uint32_t)((addr>>16)>>16)
151 #define	dma_addr_lo32(addr)	(uint32_t)(addr & 0xffffffff)
152 
153 /*
154  *	  IOCTL CONTROL CODE
155  */
156 struct CMD_MESSAGE {
157 	uint32_t HeaderLength;
158 	uint8_t  Signature[8];
159 	uint32_t Timeout;
160 	uint32_t ControlCode;
161 	uint32_t ReturnCode;
162 	uint32_t Length;
163 };
164 
165 
166 #define	MSGDATABUFLEN	1031
167 struct CMD_MESSAGE_FIELD {
168 	struct CMD_MESSAGE cmdmessage;	/* 28 byte ioctl header */
169 	uint8_t messagedatabuffer[MSGDATABUFLEN];	/* 1032 */
170 	/* areca gui program does not accept more than 1031 byte */
171 };
172 
173 /* IOP message transfer */
174 #define	ARCMSR_MESSAGE_FAIL			0x0001
175 
176 /* error code for StorPortLogError,ScsiPortLogError */
177 #define	ARCMSR_IOP_ERROR_ILLEGALPCI		0x0001
178 #define	ARCMSR_IOP_ERROR_VENDORID		0x0002
179 #define	ARCMSR_IOP_ERROR_DEVICEID		0x0002
180 #define	ARCMSR_IOP_ERROR_ILLEGALCDB		0x0003
181 #define	ARCMSR_IOP_ERROR_UNKNOW_CDBERR		0x0004
182 #define	ARCMSR_SYS_ERROR_MEMORY_ALLOCATE	0x0005
183 #define	ARCMSR_SYS_ERROR_MEMORY_CROSS4G		0x0006
184 #define	ARCMSR_SYS_ERROR_MEMORY_LACK		0x0007
185 #define	ARCMSR_SYS_ERROR_MEMORY_RANGE		0x0008
186 #define	ARCMSR_SYS_ERROR_DEVICE_BASE		0x0009
187 #define	ARCMSR_SYS_ERROR_PORT_VALIDATE		0x000A
188 /* DeviceType */
189 #define	ARECA_SATA_RAID				0x90000000
190 /* FunctionCode */
191 #define	FUNCTION_READ_RQBUFFER			0x0801
192 #define	FUNCTION_WRITE_WQBUFFER			0x0802
193 #define	FUNCTION_CLEAR_RQBUFFER			0x0803
194 #define	FUNCTION_CLEAR_WQBUFFER			0x0804
195 #define	FUNCTION_CLEAR_ALLQBUFFER		0x0805
196 #define	FUNCTION_REQUEST_RETURN_CODE_3F		0x0806
197 #define	FUNCTION_SAY_HELLO			0x0807
198 #define	FUNCTION_SAY_GOODBYE			0x0808
199 #define	FUNCTION_FLUSH_ADAPTER_CACHE		0x0809
200 
201 /* ARECA IO CONTROL CODE */
202 #define	ARCMSR_MESSAGE_READ_RQBUFFER			\
203 	ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
204 #define	ARCMSR_MESSAGE_WRITE_WQBUFFER			\
205 	ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
206 #define	ARCMSR_MESSAGE_CLEAR_RQBUFFER			\
207 	ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
208 #define	ARCMSR_MESSAGE_CLEAR_WQBUFFER			\
209 	ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
210 #define	ARCMSR_MESSAGE_CLEAR_ALLQBUFFER			\
211 	ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
212 #define	ARCMSR_MESSAGE_REQUEST_RETURN_CODE_3F		\
213 	ARECA_SATA_RAID | FUNCTION_REQUEST_RETURN_CODE_3F
214 #define	ARCMSR_MESSAGE_SAY_HELLO			\
215 	ARECA_SATA_RAID | FUNCTION_SAY_HELLO
216 #define	ARCMSR_MESSAGE_SAY_GOODBYE			\
217 	ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
218 #define	ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE		\
219 	ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
220 
221 /* ARECA IOCTL ReturnCode */
222 #define	ARCMSR_MESSAGE_RETURNCODE_OK		0x00000001
223 #define	ARCMSR_MESSAGE_RETURNCODE_ERROR		0x00000006
224 #define	ARCMSR_MESSAGE_RETURNCODE_3F		0x0000003F
225 
226 /*
227  *  SPEC. for Areca HBB adapter
228  */
229 /* ARECA HBB COMMAND for its FIRMWARE */
230 /* window of "instruction flags" from driver to iop */
231 #define	ARCMSR_DRV2IOP_DOORBELL			0x00020400
232 #define	ARCMSR_DRV2IOP_DOORBELL_MASK		0x00020404
233 /* window of "instruction flags" from iop to driver */
234 #define	ARCMSR_IOP2DRV_DOORBELL			0x00020408
235 #define	ARCMSR_IOP2DRV_DOORBELL_MASK		0x0002040C
236 
237 
238 /* ARECA FLAG LANGUAGE */
239 #define	ARCMSR_IOP2DRV_DATA_WRITE_OK		0x00000001 /* ioctl xfer */
240 #define	ARCMSR_IOP2DRV_DATA_READ_OK		0x00000002 /* ioctl xfer */
241 #define	ARCMSR_IOP2DRV_CDB_DONE			0x00000004
242 #define	ARCMSR_IOP2DRV_MESSAGE_CMD_DONE		0x00000008
243 
244 #define	ARCMSR_DOORBELL_HANDLE_INT		0x0000000F
245 #define	ARCMSR_DOORBELL_INT_CLEAR_PATTERN	0xFF00FFF0
246 #define	ARCMSR_MESSAGE_INT_CLEAR_PATTERN	0xFF00FFF7
247 
248 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
249 #define	ARCMSR_MESSAGE_GET_CONFIG		0x00010008
250 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
251 #define	ARCMSR_MESSAGE_SET_CONFIG		0x00020008
252 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
253 #define	ARCMSR_MESSAGE_ABORT_CMD		0x00030008
254 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
255 #define	ARCMSR_MESSAGE_STOP_BGRB		0x00040008
256 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
257 #define	ARCMSR_MESSAGE_FLUSH_CACHE		0x00050008
258 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
259 #define	ARCMSR_MESSAGE_START_BGRB		0x00060008
260 #define	ARCMSR_MESSAGE_START_DRIVER_MODE	0x000E0008
261 #define	ARCMSR_MESSAGE_SET_POST_WINDOW		0x000F0008
262 #define	ARCMSR_MESSAGE_ACTIVE_EOI_MODE		0x00100008
263 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
264 #define	ARCMSR_MESSAGE_FIRMWARE_OK		0x80000000
265 
266 #define	ARCMSR_DRV2IOP_DATA_WRITE_OK		0x00000001 /* ioctl xfer */
267 #define	ARCMSR_DRV2IOP_DATA_READ_OK		0x00000002 /* ioctl xfer */
268 #define	ARCMSR_DRV2IOP_CDB_POSTED		0x00000004
269 #define	ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED	0x00000008
270 #define	ARCMSR_DRV2IOP_END_OF_INTERRUPT		0x00000010
271 
272 #define	ARCMSR_HBC_ISR_THROTTLING_LEVEL		12
273 #define	ARCMSR_HBC_ISR_MAX_DONE_QUEUE		20
274 /* Host Interrupt Mask */
275 #define	ARCMSR_HBCMU_UTILITY_A_ISR_MASK			0x00000001
276 #define	ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 	0x00000004
277 #define	ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK	0x00000008
278 #define	ARCMSR_HBCMU_ALL_INTMASKENABLE			0x0000000D
279 
280 /* Host Interrupt Status */
281 #define	ARCMSR_HBCMU_UTILITY_A_ISR			0x00000001
282 	/*
283 	 * Set when the Utility_A Interrupt bit is set in the Outbound
284 	 * Doorbell Register.  It clears by writing a 1 to the
285 	 * Utility_A bit in the Outbound Doorbell Clear Register or
286 	 * through automatic clearing (if enabled).
287 	 */
288 #define	ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR		0x00000004
289 	/*
290 	 * Set if Outbound Doorbell register bits 30:1 have a non-zero
291 	 * value. This bit clears only when Outbound Doorbell bits
292 	 * 30:1 are ALL clear. Only a write to the Outbound Doorbell
293 	 * Clear register clears bits in the Outbound Doorbell
294 	 * register.
295 	 */
296 #define	ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR		0x00000008
297 	/*
298 	 * Set whenever the Outbound Post List Producer/Consumer
299 	 * Register (FIFO) is not empty. It clears when the Outbound
300 	 * Post List FIFO is empty.
301 	 */
302 #define	ARCMSR_HBCMU_SAS_ALL_INT			0x00000010
303 	/*
304 	 * This bit indicates a SAS interrupt from a source external to
305 	 * the PCIe core. This bit is not maskable.
306 	 */
307 /* DoorBell */
308 #define	ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK			0x00000002
309 #define	ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK			0x00000004
310 #define	ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE			0x00000008
311 #define	ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING		0x00000010
312 #define	ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK			0x00000002
313 #define	ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR		0x00000002
314 #define	ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK			0x00000004
315 #define	ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR		0x00000004
316 #define	ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE			0x00000008
317 #define	ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR	0x00000008
318 #define	ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK			0x80000000
319 
320 /* data tunnel buffer between user space program and its firmware */
321 /* iop msgcode_rwbuffer for message command */
322 #define	ARCMSR_MSGCODE_RWBUFFER			0x0000fa00
323 /* user space data to iop 128bytes */
324 #define	ARCMSR_IOCTL_WBUFFER			0x0000fe00
325 /* iop data to user space 128bytes */
326 #define	ARCMSR_IOCTL_RBUFFER			0x0000ff00
327 #define	ARCMSR_HBB_BASE0_OFFSET			0x00000010
328 #define	ARCMSR_HBB_BASE1_OFFSET			0x00000018
329 #define	ARCMSR_HBB_BASE0_LEN			0x00021000
330 #define	ARCMSR_HBB_BASE1_LEN			0x00010000
331 
332 /*
333  *	structure for holding DMA address data
334  */
335 #define	IS_SG64_ADDR				0x01000000 /* bit24 */
336 
337 /* 32bit Scatter-Gather list */
338 struct  SG32ENTRY {
339 	/* bit 24 = 0, high 8 bit = flag, low 24 bit = length */
340 	uint32_t	length;
341 	uint32_t	address;
342 };
343 
344 /* 64bit Scatter-Gather list */
345 struct  SG64ENTRY {
346 	/* bit 24 = 1, high 8 bit = flag, low 24 bit = length */
347 	uint32_t	length;
348 	uint32_t	address;
349 	uint32_t	addresshigh;
350 };
351 
352 
353 struct QBUFFER {
354 	uint32_t	data_len;
355 	uint8_t		data[124];
356 };
357 
358 struct list_head {
359 	struct list_head *next, *prev;
360 };
361 
362 /*
363  *	FIRMWARE INFO
364  */
365 #define	ARCMSR_FW_MODEL_OFFSET	0x0f
366 #define	ARCMSR_FW_VERS_OFFSET	0x11
367 #define	ARCMSR_FW_MAP_OFFSET	0x15
368 
369 struct FIRMWARE_INFO {
370 	uint32_t	signature;
371 	uint32_t	request_len;
372 	uint32_t	numbers_queue;
373 	uint32_t	sdram_size;
374 	uint32_t	ide_channels;
375 	char		vendor[40];
376 	char		model[8];
377 	char		firmware_ver[16];
378 	char		device_map[16];
379 };
380 
381 /*
382  * ARECA FIRMWARE SPEC
383  *
384  * Usage of IOP331 adapter
385  *
386  * (All In/Out is in IOP331's view)
387  *	1. Message 0 --> InitThread message and retrun code
388  *	2. Doorbell is used for RS-232 emulation
389  *		InDoorBell :
390  *			bit0 -- data in ready (DRIVER DATA WRITE OK)
391  *			bit1 -- data out has been read
392  *						(DRIVER DATA READ OK)
393  *		outDoorBell:
394  *			bit0 -- data out ready (IOP331 DATA WRITE OK)
395  *			bit1 -- data in has been read
396  * 						(IOP331 DATA READ OK)
397  *	3. Index Memory Usage
398  *		offset 0xf00 : for RS232 out (request buffer)
399  *		offset 0xe00 : for RS232 in  (scratch buffer)
400  *		offset 0xa00 : for inbound message code msgcode_rwbuffer
401  *				(driver send to IOP331)
402  *		offset 0xa00 : for outbound message code msgcode_rwbuffer
403  * 				(IOP331 send to driver)
404  *	4. RS-232 emulation
405  *		Currently 128 byte buffer is used:
406  *		1st uint32_t : Data length (1--124)
407  *			Byte 4--127 : Max 124 bytes of data
408  *	5. PostQ
409  *		All SCSI Command must be sent through postQ:
410  *		(inbound queue port) Request frame must be 32 bytes aligned
411  *			# bits 31:27 => flag for post ccb
412  *		# bits 26:00 => real address (bit 31:27) of post arcmsr_cdb
413  *		bit31 : 0 : 256 bytes frame
414  *		1 : 512 bytes frame
415  *		bit30 : 0 : normal request
416  *		1 : BIOS request
417  *		bit29 : reserved
418  *		bit28 : reserved
419  *		bit27 : reserved
420  *  -----------------------------------------------------------------------
421  * 		(outbount queue port)	Request reply
422  *				# bits 31:27 => flag for reply
423  *		# bits 26:00 => real address (bits 31:27) of reply arcmsr_cdb
424  *		# bit31 : must be 0 (for this type of reply)
425  *		# bit30 : reserved for BIOS handshake
426  *		# bit29 : reserved
427  *		# bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData
428  *			  1 : Error, see in AdapStatus/DevStatus/SenseData
429  *		# bit27 : reserved
430  *	6. BIOS request
431  *		All BIOS request is the same with request from PostQ
432  *		Except :
433  *		Request frame is sent from configuration space
434  *			offset: 0x78 : Request Frame (bit30 == 1)
435  *			offset: 0x18 : writeonly to generate IRQ to IOP331
436  *		Completion of request:
437  *				(bit30 == 0, bit28==err flag)
438  *	7. Definition of SGL entry (structure)
439  *	8. Message1 Out - Diag Status Code (????)
440  *	9. Message0 message code :
441  *		0x00 : NOP
442  *		0x01 : Get Config ->offset 0xa00
443  *			 : for outbound message code msgcode_rwbuffer
444  *			(IOP331 send to driver)
445  * 		Signature 0x87974060(4)
446  *		Request len		0x00000200(4)
447  *		numbers of queue	0x00000100(4)
448  *		SDRAM Size		0x00000100(4)-->256 MB
449  *		IDE Channels	  0x00000008(4)
450  *		vendor		40 bytes char
451  *		model		  8 bytes char
452  *		FirmVer		 16 bytes char
453  *		Device Map		16 bytes char
454  *
455  *		FirmwareVersion DWORD
456  *			<== Added for checking of new firmware capability
457  *		0x02 : Set Config ->offset 0xa00
458  *			:for inbound message code msgcode_rwbuffer
459  *				(driver send to IOP331)
460  *		Signature		 0x87974063(4)
461  *		UPPER32 of Request Frame  (4)-->Driver Only
462  *		0x03 : Reset (Abort all queued Command)
463  *		0x04 : Stop Background Activity
464  *		0x05 : Flush Cache
465  *		0x06 : Start Background Activity
466  *			(re-start if background is halted)
467  *		0x07 : Check If Host Command Pending
468  *			(Novell May Need This Function)
469  *		0x08 : Set controller time ->offset 0xa00 (driver to IOP331)
470  *			: for inbound message code msgcode_rwbuffer
471  *		byte 0 : 0xaa <-- signature
472  *		byte 1 : 0x55 <-- signature
473  *		byte 2 : year (04)
474  *		byte 3 : month (1..12)
475  *		byte 4 : date (1..31)
476  *		byte 5 : hour (0..23)
477  *		byte 6 : minute (0..59)
478  *		byte 7 : second (0..59)
479  *
480  */
481 
482 
483 /* signature of set and get firmware config */
484 #define	ARCMSR_SIGNATURE_GET_CONFIG			0x87974060
485 #define	ARCMSR_SIGNATURE_SET_CONFIG			0x87974063
486 
487 
488 /* message code of inbound message register */
489 #define	ARCMSR_INBOUND_MESG0_NOP			0x00000000
490 #define	ARCMSR_INBOUND_MESG0_GET_CONFIG			0x00000001
491 #define	ARCMSR_INBOUND_MESG0_SET_CONFIG			0x00000002
492 #define	ARCMSR_INBOUND_MESG0_ABORT_CMD			0x00000003
493 #define	ARCMSR_INBOUND_MESG0_STOP_BGRB			0x00000004
494 #define	ARCMSR_INBOUND_MESG0_FLUSH_CACHE		0x00000005
495 #define	ARCMSR_INBOUND_MESG0_START_BGRB			0x00000006
496 #define	ARCMSR_INBOUND_MESG0_CHK331PENDING		0x00000007
497 #define	ARCMSR_INBOUND_MESG0_SYNC_TIMER			0x00000008
498 /* doorbell interrupt generator */
499 #define	ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK		0x00000001
500 #define	ARCMSR_INBOUND_DRIVER_DATA_READ_OK		0x00000002
501 #define	ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK		0x00000001
502 #define	ARCMSR_OUTBOUND_IOP331_DATA_READ_OK		0x00000002
503 /* ccb areca ccb flag */
504 #define	ARCMSR_CCBPOST_FLAG_SGL_BSIZE			0x80000000
505 #define	ARCMSR_CCBPOST_FLAG_IAM_BIOS			0x40000000
506 #define	ARCMSR_CCBREPLY_FLAG_IAM_BIOS			0x40000000
507 #define	ARCMSR_CCBREPLY_FLAG_ERROR			0x10000000
508 #define	ARCMSR_CCBREPLY_FLAG_ERROR_MODE0		0x10000000
509 #define	ARCMSR_CCBREPLY_FLAG_ERROR_MODE1		0x00000001
510 /* outbound firmware ok */
511 #define	ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK		0x80000000
512 
513 /* dma burst sizes */
514 #ifndef BURSTSIZE
515 #define	BURSTSIZE
516 #define	BURST1			0x01
517 #define	BURST2			0x02
518 #define	BURST4			0x04
519 #define	BURST8			0x08
520 #define	BURST16			0x10
521 #define	BURST32			0x20
522 #define	BURST64			0x40
523 #define	BURSTSIZE_MASK		0x7f
524 #define	DEFAULT_BURSTSIZE	BURST16|BURST8|BURST4|BURST2|BURST1
525 #endif  /* BURSTSIZE */
526 
527 #define	PtrToNum(p)		(uintptr_t)((void *)p)
528 #define	NumToPtr(ul)		(void *)((uintptr_t)ul)
529 
530 /*
531  *
532  */
533 struct ARCMSR_CDB {
534 	uint8_t		Bus;		/* should be 0 */
535 	uint8_t		TargetID;	/* should be 0..15 */
536 	uint8_t		LUN;		/* should be 0..7 */
537 	uint8_t		Function;	/* should be 1 */
538 
539 	uint8_t		CdbLength;	/* set in arcmsr_tran_init_pkt */
540 	uint8_t		sgcount;
541 	uint8_t		Flags;
542 
543 	/* bit 0: 0(256) / 1(512) bytes	 */
544 #define	ARCMSR_CDB_FLAG_SGL_BSIZE		0x01
545 	/* bit 1: 0(from driver) / 1(from BIOS) */
546 #define	ARCMSR_CDB_FLAG_BIOS			0x02
547 	/* bit 2: 0(Data in) / 1(Data out)	*/
548 #define	ARCMSR_CDB_FLAG_WRITE			0x04
549 	/* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */
550 #define	ARCMSR_CDB_FLAG_SIMPLEQ			0x00
551 #define	ARCMSR_CDB_FLAG_HEADQ			0x08
552 #define	ARCMSR_CDB_FLAG_ORDEREDQ		0x10
553 
554 	uint8_t		Reserved1;
555 
556 	uint32_t	Context;	/* Address of this request */
557 	uint32_t	DataLength;	/* currently unused */
558 
559 	uint8_t		Cdb[16];	/* SCSI CDB */
560 	/*
561 	 * Device Status : the same from SCSI bus if error occur
562 	 * SCSI bus status codes.
563 	 */
564 	uint8_t		DeviceStatus;
565 
566 #define	SCSISTAT_GOOD				0x00
567 #define	SCSISTAT_CHECK_CONDITION		0x02
568 #define	SCSISTAT_CONDITION_MET			0x04
569 #define	SCSISTAT_BUSY				0x08
570 #define	SCSISTAT_INTERMEDIATE			0x10
571 #define	SCSISTAT_INTERMEDIATE_COND_MET		0x14
572 #define	SCSISTAT_RESERVATION_CONFLICT		0x18
573 #define	SCSISTAT_COMMAND_TERMINATED		0x22
574 #define	SCSISTAT_QUEUE_FULL			0x28
575 
576 #define	ARCMSR_DEV_SELECT_TIMEOUT		0xF0
577 #define	ARCMSR_DEV_ABORTED			0xF1
578 #define	ARCMSR_DEV_INIT_FAIL			0xF2
579 
580 	uint8_t		SenseData[15];
581 
582 	/* Scatter gather address */
583 	union {
584 		struct SG32ENTRY	sg32entry[ARCMSR_MAX_SG_ENTRIES];
585 		struct SG64ENTRY	sg64entry[ARCMSR_MAX_SG_ENTRIES];
586 	} sgu;
587 };
588 
589 
590 struct HBA_msgUnit {
591 	uint32_t	resrved0[4];
592 	uint32_t	inbound_msgaddr0;
593 	uint32_t	inbound_msgaddr1;
594 	uint32_t	outbound_msgaddr0;
595 	uint32_t	outbound_msgaddr1;
596 	uint32_t	inbound_doorbell;
597 	uint32_t	inbound_intstatus;
598 	uint32_t	inbound_intmask;
599 	uint32_t	outbound_doorbell;
600 	uint32_t	outbound_intstatus;
601 	uint32_t	outbound_intmask;
602 	uint32_t	reserved1[2];
603 	uint32_t	inbound_queueport;
604 	uint32_t	outbound_queueport;
605 	uint32_t	reserved2[2];
606 	/* ......local_buffer */
607 	uint32_t	reserved3[492];
608 	uint32_t	reserved4[128];
609 	uint32_t	msgcode_rwbuffer[256];
610 	uint32_t	message_wbuffer[32];
611 	uint32_t	reserved5[32];
612 	uint32_t	message_rbuffer[32];
613 	uint32_t	reserved6[32];
614 };
615 
616 
617 struct HBB_DOORBELL {
618 	uint8_t		doorbell_reserved[132096];
619 	/*
620 	 * offset 0x00020400:00,01,02,03: window of "instruction flags"
621 	 * from driver to iop
622 	 */
623 	uint32_t	drv2iop_doorbell;
624 	/* 04,05,06,07: doorbell mask */
625 	uint32_t	drv2iop_doorbell_mask;
626 	/* 08,09,10,11: window of "instruction flags" from iop to driver */
627 	uint32_t	iop2drv_doorbell;
628 	/* 12,13,14,15: doorbell mask */
629 	uint32_t	iop2drv_doorbell_mask;
630 };
631 
632 
633 struct HBB_RWBUFFER {
634 	uint8_t		message_reserved0[64000];
635 	/* offset 0x0000fa00:	0..1023: message code read write 1024bytes */
636 	uint32_t	msgcode_rwbuffer[256];
637 	/* offset 0x0000fe00:1024...1151: user space data to iop 128bytes */
638 	uint32_t	message_wbuffer[32];
639 	/* 1152...1279: message reserved */
640 	uint32_t	message_reserved1[32];
641 	/* offset 0x0000ff00:1280...1407: iop data to user space 128bytes */
642 	uint32_t	message_rbuffer[32];
643 };
644 
645 struct HBB_msgUnit {
646 	uint32_t		post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
647 	uint32_t		done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
648 
649 	int32_t			postq_index;	/* post queue index */
650 	int32_t			doneq_index;	/* done queue index */
651 	struct HBB_DOORBELL	*hbb_doorbell;
652 	struct HBB_RWBUFFER	*hbb_rwbuffer;
653 };
654 
655 struct HBC_msgUnit {
656 	uint32_t	message_unit_status;			/* 0000 0003 */
657 	uint32_t	slave_error_attribute;			/* 0004 0007 */
658 	uint32_t	slave_error_address;			/* 0008 000B */
659 	uint32_t	posted_outbound_doorbell;		/* 000C 000F */
660 	uint32_t	master_error_attribute;			/* 0010 0013 */
661 	uint32_t	master_error_address_low;		/* 0014 0017 */
662 	uint32_t	master_error_address_high;		/* 0018 001B */
663 	uint32_t	hcb_size;				/* 001C 001F */
664 	uint32_t	inbound_doorbell;			/* 0020 0023 */
665 	uint32_t	diagnostic_rw_data;			/* 0024 0027 */
666 	uint32_t	diagnostic_rw_address_low;		/* 0028 002B */
667 	uint32_t	diagnostic_rw_address_high;		/* 002C 002F */
668 	uint32_t	host_int_status;			/* 0030 0033 */
669 	uint32_t	host_int_mask;				/* 0034 0037 */
670 	uint32_t	dcr_data;				/* 0038 003B */
671 	uint32_t	dcr_address;				/* 003C 003F */
672 	uint32_t	inbound_queueport;			/* 0040 0043 */
673 	uint32_t	outbound_queueport;			/* 0044 0047 */
674 	uint32_t	hcb_pci_address_low;			/* 0048 004B */
675 	uint32_t	hcb_pci_address_high;			/* 004C 004F */
676 	uint32_t	iop_int_status;				/* 0050 0053 */
677 	uint32_t	iop_int_mask;				/* 0054 0057 */
678 	uint32_t	iop_inbound_queue_port;			/* 0058 005B */
679 	uint32_t	iop_outbound_queue_port;		/* 005C 005F */
680 	uint32_t	inbound_free_list_index;		/* 0060 0063 */
681 	uint32_t	inbound_post_list_index;		/* 0064 0067 */
682 	uint32_t	outbound_free_list_index;		/* 0068 006B */
683 	uint32_t	outbound_post_list_index;		/* 006C 006F */
684 	uint32_t	inbound_doorbell_clear;			/* 0070 0073 */
685 	uint32_t	i2o_message_unit_control;		/* 0074 0077 */
686 	uint32_t	last_used_message_source_address_low;	/* 0078 007B */
687 	uint32_t	last_used_message_source_address_high;	/* 007C 007F */
688 	uint32_t	pull_mode_data_byte_count[4];		/* 0080 008F */
689 	uint32_t	message_dest_address_index;		/* 0090 0093 */
690 	uint32_t	done_queue_not_empty_int_counter_timer;	/* 0094 0097 */
691 	uint32_t	utility_A_int_counter_timer;		/* 0098 009B */
692 	uint32_t	outbound_doorbell;			/* 009C 009F */
693 	uint32_t	outbound_doorbell_clear;		/* 00A0 00A3 */
694 	uint32_t	message_source_address_index;		/* 00A4 00A7 */
695 	uint32_t	message_done_queue_index;		/* 00A8 00AB */
696 	uint32_t	reserved0;				/* 00AC 00AF */
697 	uint32_t	inbound_msgaddr0;			/* 00B0 00B3 */
698 	uint32_t	inbound_msgaddr1;			/* 00B4 00B7 */
699 	uint32_t	outbound_msgaddr0;			/* 00B8 00BB */
700 	uint32_t	outbound_msgaddr1;			/* 00BC 00BF */
701 	uint32_t	inbound_queueport_low;			/* 00C0 00C3 */
702 	uint32_t	inbound_queueport_high;			/* 00C4 00C7 */
703 	uint32_t	outbound_queueport_low;			/* 00C8 00CB */
704 	uint32_t	outbound_queueport_high;		/* 00CC 00CF */
705 	uint32_t	iop_inbound_queue_port_low;		/* 00D0 00D3 */
706 	uint32_t	iop_inbound_queue_port_high;		/* 00D4 00D7 */
707 	uint32_t	iop_outbound_queue_port_low;		/* 00D8 00DB */
708 	uint32_t	iop_outbound_queue_port_high;		/* 00DC 00DF */
709 	uint32_t	message_dest_queue_port_low;		/* 00E0 00E3 */
710 	uint32_t	message_dest_queue_port_high;		/* 00E4 00E7 */
711 	uint32_t	last_used_message_dest_address_low;	/* 00E8 00EB */
712 	uint32_t	last_used_message_dest_address_high;	/* 00EC 00EF */
713 	uint32_t	message_done_queue_base_address_low;	/* 00F0 00F3 */
714 	uint32_t	message_done_queue_base_address_high;	/* 00F4 00F7 */
715 	uint32_t	host_diagnostic;			/* 00F8 00FB */
716 	uint32_t	write_sequence;				/* 00FC 00FF */
717 	uint32_t	reserved1[34];				/* 0100 0187 */
718 	uint32_t	reserved2[1950];			/* 0188 1FFF */
719 	uint32_t	message_wbuffer[32];			/* 2000 207F */
720 	uint32_t	reserved3[32];				/* 2080 20FF */
721 	uint32_t	message_rbuffer[32];			/* 2100 217F */
722 	uint32_t	reserved4[32];				/* 2180 21FF */
723 	uint32_t	msgcode_rwbuffer[256];			/* 2200 23FF */
724 };
725 
726 struct msgUnit {
727 	union	{
728 		struct HBA_msgUnit	hbamu;
729 		struct HBB_msgUnit	hbbmu;
730 		struct HBC_msgUnit	hbcmu;
731 	} muu;
732 };
733 
734 
735 /*
736  * Adapter Control Block
737  */
738 struct ACB {
739 	uint32_t		adapter_type; /* A/B/C/D */
740 
741 #define	ACB_ADAPTER_TYPE_A	0x00000001	/* hba (Intel) IOP */
742 #define	ACB_ADAPTER_TYPE_B	0x00000002	/* hbb (Marvell) IOP */
743 #define	ACB_ADAPTER_TYPE_C	0x00000004	/* hbc (Lsi) IOP */
744 #define	ACB_ADAPTER_TYPE_D	0x00000008	/* hbd A IOP */
745 
746 	scsi_hba_tran_t		*scsi_hba_transport;
747 	dev_info_t		*dev_info;
748 	ddi_acc_handle_t	reg_mu_acc_handle0;
749 	ddi_acc_handle_t	reg_mu_acc_handle1;
750 	ddi_acc_handle_t	ccbs_acc_handle;
751 	ddi_dma_handle_t	ccbs_pool_handle;
752 	ddi_dma_cookie_t	ccb_cookie;
753 	ddi_device_acc_attr_t	dev_acc_attr;
754 	kmutex_t		isr_mutex;
755 	kmutex_t		acb_mutex;
756 	kmutex_t		postq_mutex;
757 	kmutex_t		workingQ_mutex;
758 	kmutex_t		ioctl_mutex;
759 	kmutex_t		ccb_complete_list_mutex;
760 	timeout_id_t		timeout_id;
761 	timeout_id_t		timeout_sc_id;
762 	ddi_taskq_t		*taskq;
763 	ddi_intr_handle_t	*phandle;
764 	uint_t			intr_size;
765 	int			intr_count;
766 	uint_t			intr_pri;
767 	int			intr_cap;
768 
769 	/* Offset for arc cdb physical to virtual calculations */
770 	uint64_t		vir2phy_offset;
771 	uint32_t		outbound_int_enable;
772 	uint32_t		cdb_phyaddr_hi32;
773 	/* message unit ATU inbound base address0 virtual */
774 	struct msgUnit		*pmu;
775 	struct list_head	ccb_complete_list;
776 
777 	uint8_t			adapter_index;
778 	uint16_t		acb_flags;
779 
780 #define	ACB_F_SCSISTOPADAPTER			0x0001
781 /* stop RAID background rebuild */
782 #define	ACB_F_MSG_STOP_BGRB			0x0002
783 /* stop RAID background rebuild */
784 #define	ACB_F_MSG_START_BGRB			0x0004
785 /* iop ioctl data rqbuffer overflow */
786 #define	ACB_F_IOPDATA_OVERFLOW			0x0008
787 /* ioctl clear wqbuffer */
788 #define	ACB_F_MESSAGE_WQBUFFER_CLEARED  	0x0010
789 /* ioctl clear rqbuffer */
790 #define	ACB_F_MESSAGE_RQBUFFER_CLEARED  	0x0020
791 /* ioctl iop wqbuffer data readed */
792 #define	ACB_F_MESSAGE_WQBUFFER_READ		0x0040
793 #define	ACB_F_BUS_RESET				0x0080
794 /* iop init */
795 #define	ACB_F_IOP_INITED			0x0100
796 /* need hardware reset bus */
797 #define	ACB_F_BUS_HANG_ON			0x0800
798 
799 	/* serial ccb pointer array */
800 	struct CCB		*pccb_pool[ARCMSR_MAX_FREECCB_NUM];
801 	/* working ccb pointer array */
802 	struct CCB		*ccbworkingQ[ARCMSR_MAX_FREECCB_NUM];
803 	/* done ccb array index */
804 	int32_t			ccb_put_index;
805 	/* start ccb array index  */
806 	int32_t			ccb_get_index;
807 	volatile uint32_t	ccboutstandingcount;
808 
809 	/* data collection buffer for read from 80331 */
810 	uint8_t			rqbuffer[ARCMSR_MAX_QBUFFER];
811 	/* first of read buffer  */
812 	int32_t			rqbuf_firstidx;
813 	/* last of read buffer	*/
814 	int32_t			rqbuf_lastidx;
815 
816 	/* data collection buffer for write to 80331  */
817 	uint8_t			wqbuffer[ARCMSR_MAX_QBUFFER];
818 	/* first of write buffer */
819 	int32_t			wqbuf_firstidx;
820 	/* last of write buffer  */
821 	int32_t			wqbuf_lastidx;
822 	/* id0 ..... id15,lun0...lun7 */
823 	uint8_t		devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
824 #define	ARECA_RAID_GONE		0x55
825 #define	ARECA_RAID_GOOD		0xaa
826 
827 	uint32_t		timeout_count;
828 	uint32_t		num_resets;
829 	uint32_t		num_aborts;
830 	uint32_t		firm_request_len;
831 	uint32_t		firm_numbers_queue;
832 	uint32_t		firm_sdram_size;
833 	uint32_t		firm_ide_channels;
834 	uint32_t		firm_cfg_version;
835 	char			firm_model[12];
836 	char			firm_version[20];
837 	char			device_map[20];	/* 21,84-99 */
838 	ddi_acc_handle_t	pci_acc_handle;
839 };
840 
841 
842 /*
843  * Command Control Block (SrbExtension)
844  *
845  * CCB must be not cross page boundary,and the order from offset 0
846  * structure describing an ATA disk request this CCB length must be
847  * 32 bytes boundary
848  *
849  */
850 struct CCB
851 {
852 	struct  ARCMSR_CDB	arcmsr_cdb;
853     struct  list_head	complete_queue_pointer;
854 	uint32_t			cdb_phyaddr_pattern;
855 	uint16_t			ccb_flags;
856 #define	CCB_FLAG_READ			0x0000
857 #define	CCB_FLAG_WRITE			0x0001
858 #define	CCB_FLAG_ERROR			0x0002
859 #define	CCB_FLAG_FLUSHCACHE		0x0004
860 #define	CCB_FLAG_MASTER_ABORTED 	0x0008
861 #define	CCB_FLAG_DMAVALID		0x0010
862 #define	CCB_FLAG_DMACONSISTENT  	0x0020
863 #define	CCB_FLAG_DMAWRITE		0x0040
864 #define	CCB_FLAG_PKTBIND		0x0080
865 	uint16_t			ccb_state;
866 #define	ARCMSR_CCB_FREE			0x0000
867 #define	ARCMSR_CCB_UNBUILD 		0x0100
868 #define	ARCMSR_CCB_START		0x0001
869 #define	ARCMSR_CCB_RETRY 		0x0002
870 #define	ARCMSR_CCB_TIMEOUT 		0x0004
871 #define	ARCMSR_CCB_ABORTED		0x0008
872 #define	ARCMSR_CCB_RESET		0x0010
873 #define	ARCMSR_CCB_DONE			0x0020
874 #define	ARCMSR_CCB_WAIT4_FREE		0x0040
875 #define	ARCMSR_CCB_BACK			0x0080
876 #define	ARCMSR_CCB_ILLEGAL		0xFFFF
877 #define	ARCMSR_ABNORMAL_MASK	\
878 	(ARCMSR_CCB_TIMEOUT | ARCMSR_CCB_ABORTED | ARCMSR_CCB_RESET)
879 #define	ARCMSR_CCB_CAN_BE_FREE	(ARCMSR_CCB_WAIT4_FREE | ARCMSR_CCB_BACK)
880 	struct scsi_pkt			*pkt;
881 	struct ACB			*acb;
882 	ddi_dma_cookie_t		pkt_dmacookies[ARCMSR_MAX_SG_ENTRIES];
883 	ddi_dma_handle_t		pkt_dma_handle;
884 	uint_t				pkt_cookie;
885 	uint_t				pkt_ncookies;
886 	uint_t				pkt_nwin;
887 	uint_t				pkt_curwin;
888 	off_t				pkt_dma_offset;
889 	size_t				pkt_dma_len;
890 	size_t				total_dmac_size;
891 	time_t				ccb_time;
892 	struct buf			*bp;
893 	ddi_dma_cookie_t		resid_dmacookie;
894 	uint32_t			arc_cdb_size;
895 };
896 
897 
898 /* SenseData[15] */
899 struct SENSE_DATA {
900 	DECL_BITFIELD3(
901 	    ErrorCode		:4,	/* Vendor Unique error code */
902 	    ErrorClass		:3,	/* Error Class- fixed at 0x7 */
903 	    Valid		:1);	/* sense data is valid */
904 
905 	uint8_t SegmentNumber;	/* segment number: for COPY cmd */
906 
907 	DECL_BITFIELD5(
908 	    SenseKey		:4,	/* Sense key (see below) */
909 	    Reserved		:1,	/* reserved */
910 	    IncorrectLength	:1,	/* Incorrect Length Indicator */
911 	    EndOfMedia		:1,	/* End of Media */
912 	    FileMark		:1);	/* File Mark Detected */
913 
914 	uint8_t Information[4];
915 	uint8_t AdditionalSenseLength;
916 	uint8_t CommandSpecificInformation[4];
917 	uint8_t AdditionalSenseCode;
918 	uint8_t AdditionalSenseCodeQualifier;
919 	uint8_t FieldReplaceableUnitCode;
920 };
921 
922 #define	VIDLEN	8
923 #define	PIDLEN	16
924 #define	REVLEN	4
925 struct	SCSIInqData {
926 	uint8_t	DevType;	/* Periph Qualifier & Periph Dev Type */
927 	uint8_t	RMB_TypeMod;	/* rem media bit & Dev Type Modifier */
928 	uint8_t	Vers;		/* ISO, ECMA, & ANSI versions */
929 	uint8_t	RDF;		/* AEN, TRMIOP, & response data format */
930 	uint8_t	AddLen;		/* length of additional data */
931 	uint8_t	Res1;		/* reserved */
932 	uint8_t	Res2;		/* reserved */
933 	uint8_t	Flags; 		/* RelADr, Wbus32, Wbus16, Sync etc */
934 	uint8_t	VendorID[VIDLEN];	/* Vendor Identification */
935 	uint8_t	ProductID[PIDLEN]; 	/* Product Identification */
936 	uint8_t	ProductRev[REVLEN]; /* Product Revision */
937 };
938 
939 
940 
941 /*
942  * These definitions are the register offsets as defined in the Intel
943  * IOP manuals. See (correct as of 18 January 2008)
944  * http://developer.intel.com/design/iio/index.htm?iid=ncdcnav2+stor_ioproc
945  * for more details
946  */
947 
948 
949 #define	ARCMSR_MU_INBOUND_MESSAGE_REG0				0x10
950 #define	ARCMSR_MU_INBOUND_MESSAGE_REG1				0x14
951 #define	ARCMSR_MU_OUTBOUND_MESSAGE_REG0				0x18
952 #define	ARCMSR_MU_OUTBOUND_MESSAGE_REG1				0x1C
953 #define	ARCMSR_MU_INBOUND_DOORBELL_REG				0x20
954 #define	ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG			0x24
955 #define	ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG			0x28
956 #define	ARCMSR_MU_OUTBOUND_DOORBELL_REG				0x2C
957 #define	ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG			0x30
958 #define	ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG			0x34
959 #define	ARCMSR_MU_INBOUND_QUEUE_PORT_REG			0x40
960 #define	ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG			0x44
961 
962 
963 
964 #define	ARCMSR_MU_INBOUND_MESSAGE0_INT				0x01
965 #define	ARCMSR_MU_INBOUND_MESSAGE1_INT				0x02
966 #define	ARCMSR_MU_INBOUND_DOORBELL_INT				0x04
967 #define	ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT			0x08
968 #define	ARCMSR_MU_INBOUND_POSTQUEUE_INT				0x10
969 #define	ARCMSR_MU_INBOUND_QUEUEFULL_INT				0x20
970 #define	ARCMSR_MU_INBOUND_INDEX_INT				0x40
971 
972 #define	ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE		0x01
973 #define	ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE		0x02
974 #define	ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE		0x04
975 #define	ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE		0x08
976 #define	ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE		0x10
977 #define	ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE		0x20
978 #define	ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE			0x40
979 
980 #define	ARCMSR_MU_OUTBOUND_MESSAGE0_INT 			0x01
981 #define	ARCMSR_MU_OUTBOUND_MESSAGE1_INT 			0x02
982 #define	ARCMSR_MU_OUTBOUND_DOORBELL_INT 			0x04
983 #define	ARCMSR_MU_OUTBOUND_POSTQUEUE_INT			0x08
984 #define	ARCMSR_MU_OUTBOUND_PCI_INT				0x10
985 
986 
987 #define	ARCMSR_MU_OUTBOUND_HANDLE_INT	(	\
988 	ARCMSR_MU_OUTBOUND_MESSAGE0_INT|	\
989 	ARCMSR_MU_OUTBOUND_MESSAGE1_INT|	\
990 	ARCMSR_MU_OUTBOUND_DOORBELL_INT|	\
991 	ARCMSR_MU_OUTBOUND_POSTQUEUE_INT|	\
992 	ARCMSR_MU_OUTBOUND_PCI_INT)
993 
994 #define	ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE		0x01
995 #define	ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE		0x02
996 #define	ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE		0x04
997 #define	ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE		0x08
998 #define	ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE			0x10
999 
1000 #define	ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE			0x1F
1001 
1002 #define	ARCMSR_MU_CONFIGURATION_REG				0xFFFFE350
1003 #define	ARCMSR_MU_QUEUE_BASE_ADDRESS_REG			0xFFFFE354
1004 #define	ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG			0xFFFFE360
1005 #define	ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG			0xFFFFE364
1006 #define	ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG			0xFFFFE368
1007 #define	ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG			0xFFFFE36C
1008 #define	ARCMSR_MU_LOCAL_MEMORY_INDEX_REG			0xFFFFE380
1009 
1010 #define	ARCMSR_MU_CIRCULAR_QUEUE_ENABLE				0x0001
1011 #define	ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K				0x0002
1012 #define	ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K				0x0004
1013 #define	ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K			0x0008
1014 #define	ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K			0x0010
1015 #define	ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K			0x0020
1016 
1017 
1018 
1019 #ifdef	__cplusplus
1020 }
1021 #endif
1022 
1023 #endif /* _SYS_SCSI_ADAPTERS_ARCMSR_H */
1024