1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise ARM hardware features
10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_TARGETPARSER_ARMTARGETPARSER_H
15 #define LLVM_TARGETPARSER_ARMTARGETPARSER_H
16
17 #include "llvm/ADT/StringMap.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/Support/ARMBuildAttributes.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/TargetParser/ARMTargetParserCommon.h"
22 #include <vector>
23
24 namespace llvm {
25
26 class Triple;
27
28 namespace ARM {
29
30 enum ARMABI {
31 ARM_ABI_UNKNOWN,
32 ARM_ABI_APCS,
33 ARM_ABI_AAPCS, // ARM EABI
34 ARM_ABI_AAPCS16
35 };
36
37 // Arch extension modifiers for CPUs.
38 // Note that this is not the same as the AArch64 list
39 enum ArchExtKind : uint64_t {
40 AEK_INVALID = 0,
41 AEK_NONE = 1,
42 AEK_CRC = 1 << 1,
43 AEK_CRYPTO = 1 << 2,
44 AEK_FP = 1 << 3,
45 AEK_HWDIVTHUMB = 1 << 4,
46 AEK_HWDIVARM = 1 << 5,
47 AEK_MP = 1 << 6,
48 AEK_SIMD = 1 << 7,
49 AEK_SEC = 1 << 8,
50 AEK_VIRT = 1 << 9,
51 AEK_DSP = 1 << 10,
52 AEK_FP16 = 1 << 11,
53 AEK_RAS = 1 << 12,
54 AEK_DOTPROD = 1 << 13,
55 AEK_SHA2 = 1 << 14,
56 AEK_AES = 1 << 15,
57 AEK_FP16FML = 1 << 16,
58 AEK_SB = 1 << 17,
59 AEK_FP_DP = 1 << 18,
60 AEK_LOB = 1 << 19,
61 AEK_BF16 = 1 << 20,
62 AEK_I8MM = 1 << 21,
63 AEK_CDECP0 = 1 << 22,
64 AEK_CDECP1 = 1 << 23,
65 AEK_CDECP2 = 1 << 24,
66 AEK_CDECP3 = 1 << 25,
67 AEK_CDECP4 = 1 << 26,
68 AEK_CDECP5 = 1 << 27,
69 AEK_CDECP6 = 1 << 28,
70 AEK_CDECP7 = 1 << 29,
71 AEK_PACBTI = 1 << 30,
72 AEK_MVE = 1ULL << 31,
73 // Unsupported extensions.
74 AEK_OS = 1ULL << 59,
75 AEK_IWMMXT = 1ULL << 60,
76 AEK_IWMMXT2 = 1ULL << 61,
77 AEK_MAVERICK = 1ULL << 62,
78 AEK_XSCALE = 1ULL << 63,
79 };
80
81 // List of Arch Extension names.
82 struct ExtName {
83 StringRef Name;
84 uint64_t ID;
85 StringRef Feature;
86 StringRef NegFeature;
87 };
88
89 constexpr ExtName ARCHExtNames[] = {
90 #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
91 {NAME, ID, FEATURE, NEGFEATURE},
92 #include "ARMTargetParser.def"
93 };
94
95 // List of HWDiv names (use getHWDivSynonym) and which architectural
96 // features they correspond to (use getHWDivFeatures).
97 constexpr struct {
98 StringRef Name;
99 uint64_t ID;
100 } HWDivNames[] = {
101 #define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID},
102 #include "ARMTargetParser.def"
103 };
104
105 // Arch names.
106 enum class ArchKind {
107 #define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \
108 ARCH_BASE_EXT) \
109 ID,
110 #include "ARMTargetParser.def"
111 };
112
113 // List of CPU names and their arches.
114 // The same CPU can have multiple arches and can be default on multiple arches.
115 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
116 // When this becomes table-generated, we'd probably need two tables.
117 struct CpuNames {
118 StringRef Name;
119 ArchKind ArchID;
120 bool Default; // is $Name the default CPU for $ArchID ?
121 uint64_t DefaultExtensions;
122 };
123
124 constexpr CpuNames CPUNames[] = {
125 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
126 {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
127 #include "ARMTargetParser.def"
128 };
129
130 // FPU names.
131 enum FPUKind {
132 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
133 #include "ARMTargetParser.def"
134 FK_LAST
135 };
136
137 // FPU Version
138 enum class FPUVersion {
139 NONE,
140 VFPV2,
141 VFPV3,
142 VFPV3_FP16,
143 VFPV4,
144 VFPV5,
145 VFPV5_FULLFP16,
146 };
147
148 // An FPU name restricts the FPU in one of three ways:
149 enum class FPURestriction {
150 None = 0, ///< No restriction
151 D16, ///< Only 16 D registers
152 SP_D16 ///< Only single-precision instructions, with 16 D registers
153 };
154
isDoublePrecision(const FPURestriction restriction)155 inline bool isDoublePrecision(const FPURestriction restriction) {
156 return restriction != FPURestriction::SP_D16;
157 }
158
has32Regs(const FPURestriction restriction)159 inline bool has32Regs(const FPURestriction restriction) {
160 return restriction == FPURestriction::None;
161 }
162
163 // An FPU name implies one of three levels of Neon support:
164 enum class NeonSupportLevel {
165 None = 0, ///< No Neon
166 Neon, ///< Neon
167 Crypto ///< Neon with Crypto
168 };
169
170 // v6/v7/v8 Profile
171 enum class ProfileKind { INVALID = 0, A, R, M };
172
173 // List of canonical FPU names (use getFPUSynonym) and which architectural
174 // features they correspond to (use getFPUFeatures).
175 // The entries must appear in the order listed in ARM::FPUKind for correct
176 // indexing
177 struct FPUName {
178 StringRef Name;
179 FPUKind ID;
180 FPUVersion FPUVer;
181 NeonSupportLevel NeonSupport;
182 FPURestriction Restriction;
183 };
184
185 static constexpr FPUName FPUNames[] = {
186 #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
187 {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION},
188 #include "llvm/TargetParser/ARMTargetParser.def"
189 };
190
191 // List of canonical arch names (use getArchSynonym).
192 // This table also provides the build attribute fields for CPU arch
193 // and Arch ID, according to the Addenda to the ARM ABI, chapters
194 // 2.4 and 2.3.5.2 respectively.
195 // FIXME: SubArch values were simplified to fit into the expectations
196 // of the triples and are not conforming with their official names.
197 // Check to see if the expectation should be changed.
198 struct ArchNames {
199 StringRef Name;
200 StringRef CPUAttr; // CPU class in build attributes.
201 StringRef ArchFeature;
202 FPUKind DefaultFPU;
203 uint64_t ArchBaseExtensions;
204 ArchKind ID;
205 ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
206
207 // Return ArchFeature without the leading "+".
getSubArchArchNames208 StringRef getSubArch() const { return ArchFeature.substr(1); }
209 };
210
211 static constexpr ArchNames ARMArchNames[] = {
212 #define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \
213 ARCH_BASE_EXT) \
214 {NAME, CPU_ATTR, ARCH_FEATURE, ARCH_FPU, \
215 ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR},
216 #include "llvm/TargetParser/ARMTargetParser.def"
217 };
218
219 inline ArchKind &operator--(ArchKind &Kind) {
220 assert((Kind >= ArchKind::ARMV8A && Kind <= ArchKind::ARMV9_3A) &&
221 "We only expect operator-- to be called with ARMV8/V9");
222 if (Kind == ArchKind::INVALID || Kind == ArchKind::ARMV8A ||
223 Kind == ArchKind::ARMV8_1A || Kind == ArchKind::ARMV9A ||
224 Kind == ArchKind::ARMV8R)
225 Kind = ArchKind::INVALID;
226 else {
227 unsigned KindAsInteger = static_cast<unsigned>(Kind);
228 Kind = static_cast<ArchKind>(--KindAsInteger);
229 }
230 return Kind;
231 }
232
233 // Information by ID
234 LLVM_ABI StringRef getFPUName(FPUKind FPUKind);
235 LLVM_ABI FPUVersion getFPUVersion(FPUKind FPUKind);
236 LLVM_ABI NeonSupportLevel getFPUNeonSupportLevel(FPUKind FPUKind);
237 LLVM_ABI FPURestriction getFPURestriction(FPUKind FPUKind);
238
239 LLVM_ABI bool getFPUFeatures(FPUKind FPUKind, std::vector<StringRef> &Features);
240 LLVM_ABI bool getHWDivFeatures(uint64_t HWDivKind,
241 std::vector<StringRef> &Features);
242 LLVM_ABI bool getExtensionFeatures(uint64_t Extensions,
243 std::vector<StringRef> &Features);
244
245 LLVM_ABI StringRef getArchName(ArchKind AK);
246 LLVM_ABI unsigned getArchAttr(ArchKind AK);
247 LLVM_ABI StringRef getCPUAttr(ArchKind AK);
248 LLVM_ABI StringRef getSubArch(ArchKind AK);
249 LLVM_ABI StringRef getArchExtName(uint64_t ArchExtKind);
250 LLVM_ABI StringRef getArchExtFeature(StringRef ArchExt);
251 LLVM_ABI bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK,
252 StringRef ArchExt,
253 std::vector<StringRef> &Features,
254 FPUKind &ArgFPUKind);
255 LLVM_ABI ArchKind convertV9toV8(ArchKind AK);
256
257 // Information by Name
258 LLVM_ABI FPUKind getDefaultFPU(StringRef CPU, ArchKind AK);
259 LLVM_ABI uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK);
260 LLVM_ABI StringRef getDefaultCPU(StringRef Arch);
261 LLVM_ABI StringRef getFPUSynonym(StringRef FPU);
262
263 // Parser
264 LLVM_ABI uint64_t parseHWDiv(StringRef HWDiv);
265 LLVM_ABI FPUKind parseFPU(StringRef FPU);
266 LLVM_ABI ArchKind parseArch(StringRef Arch);
267 LLVM_ABI uint64_t parseArchExt(StringRef ArchExt);
268 LLVM_ABI ArchKind parseCPUArch(StringRef CPU);
269 LLVM_ABI ProfileKind parseArchProfile(StringRef Arch);
270 LLVM_ABI unsigned parseArchVersion(StringRef Arch);
271
272 LLVM_ABI void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
273 LLVM_ABI StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
274
275 LLVM_ABI ARMABI computeTargetABI(const Triple &TT, StringRef CPU,
276 StringRef ABIName = "");
277
278 /// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
279 ///
280 /// \param Arch the architecture name (e.g., "armv7s"). If it is an empty
281 /// string then the triple's arch name is used.
282 LLVM_ABI StringRef getARMCPUForArch(const llvm::Triple &Triple,
283 StringRef MArch = {});
284
285 LLVM_ABI void PrintSupportedExtensions(StringMap<StringRef> DescMap);
286
287 } // namespace ARM
288 } // namespace llvm
289
290 #endif
291