xref: /illumos-gate/usr/src/uts/intel/io/vmm/io/vlapic_priv.h (revision 32640292339b07090f10ce34d455f98711077343)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 /*
29  * This file and its contents are supplied under the terms of the
30  * Common Development and Distribution License ("CDDL"), version 1.0.
31  * You may only use this file in accordance with the terms of version
32  * 1.0 of the CDDL.
33  *
34  * A full copy of the text of the CDDL should have accompanied this
35  * source.  A copy of the CDDL is also available via the Internet at
36  * http://www.illumos.org/license/CDDL.
37  *
38  * Copyright 2023 Oxide Computer Company
39  */
40 
41 #ifndef _VLAPIC_PRIV_H_
42 #define	_VLAPIC_PRIV_H_
43 
44 #include <x86/apicreg.h>
45 
46 /*
47  * APIC Register:		Offset	   Description
48  */
49 #define	APIC_OFFSET_ID		0x20	/* Local APIC ID		*/
50 #define	APIC_OFFSET_VER		0x30	/* Local APIC Version		*/
51 #define	APIC_OFFSET_TPR		0x80	/* Task Priority Register	*/
52 #define	APIC_OFFSET_APR		0x90	/* Arbitration Priority		*/
53 #define	APIC_OFFSET_PPR		0xA0	/* Processor Priority Register	*/
54 #define	APIC_OFFSET_EOI		0xB0	/* EOI Register			*/
55 #define	APIC_OFFSET_RRR		0xC0	/* Remote read			*/
56 #define	APIC_OFFSET_LDR		0xD0	/* Logical Destination		*/
57 #define	APIC_OFFSET_DFR		0xE0	/* Destination Format Register	*/
58 #define	APIC_OFFSET_SVR		0xF0	/* Spurious Vector Register	*/
59 #define	APIC_OFFSET_ISR0	0x100	/* In Service Register		*/
60 #define	APIC_OFFSET_ISR1	0x110
61 #define	APIC_OFFSET_ISR2	0x120
62 #define	APIC_OFFSET_ISR3	0x130
63 #define	APIC_OFFSET_ISR4	0x140
64 #define	APIC_OFFSET_ISR5	0x150
65 #define	APIC_OFFSET_ISR6	0x160
66 #define	APIC_OFFSET_ISR7	0x170
67 #define	APIC_OFFSET_TMR0	0x180	/* Trigger Mode Register	*/
68 #define	APIC_OFFSET_TMR1	0x190
69 #define	APIC_OFFSET_TMR2	0x1A0
70 #define	APIC_OFFSET_TMR3	0x1B0
71 #define	APIC_OFFSET_TMR4	0x1C0
72 #define	APIC_OFFSET_TMR5	0x1D0
73 #define	APIC_OFFSET_TMR6	0x1E0
74 #define	APIC_OFFSET_TMR7	0x1F0
75 #define	APIC_OFFSET_IRR0	0x200	/* Interrupt Request Register	*/
76 #define	APIC_OFFSET_IRR1	0x210
77 #define	APIC_OFFSET_IRR2	0x220
78 #define	APIC_OFFSET_IRR3	0x230
79 #define	APIC_OFFSET_IRR4	0x240
80 #define	APIC_OFFSET_IRR5	0x250
81 #define	APIC_OFFSET_IRR6	0x260
82 #define	APIC_OFFSET_IRR7	0x270
83 #define	APIC_OFFSET_ESR		0x280	/* Error Status Register	*/
84 #define	APIC_OFFSET_CMCI_LVT	0x2F0	/* Local Vector Table (CMCI)	*/
85 #define	APIC_OFFSET_ICR_LOW	0x300	/* Interrupt Command Register	*/
86 #define	APIC_OFFSET_ICR_HI	0x310
87 #define	APIC_OFFSET_TIMER_LVT	0x320	/* Local Vector Table (Timer)	*/
88 #define	APIC_OFFSET_THERM_LVT	0x330	/* Local Vector Table (Thermal)	*/
89 #define	APIC_OFFSET_PERF_LVT	0x340	/* Local Vector Table (PMC)	*/
90 #define	APIC_OFFSET_LINT0_LVT	0x350	/* Local Vector Table (LINT0)	*/
91 #define	APIC_OFFSET_LINT1_LVT	0x360	/* Local Vector Table (LINT1)	*/
92 #define	APIC_OFFSET_ERROR_LVT	0x370	/* Local Vector Table (ERROR)	*/
93 #define	APIC_OFFSET_TIMER_ICR	0x380	/* Timer's Initial Count	*/
94 #define	APIC_OFFSET_TIMER_CCR	0x390	/* Timer's Current Count	*/
95 #define	APIC_OFFSET_TIMER_DCR	0x3E0	/* Timer's Divide Configuration	*/
96 #define	APIC_OFFSET_SELF_IPI	0x3F0	/* Self IPI register */
97 
98 /*
99  * 16 priority levels with at most one vector injected per level.
100  */
101 #define	ISRVEC_STK_SIZE		(16 + 1)
102 
103 #define	VLAPIC_MAXLVT_INDEX	APIC_LVT_CMCI
104 
105 #define	VLAPIC_TMR_CNT		8
106 
107 struct vlapic;
108 
109 struct vlapic_ops {
110 	vcpu_notify_t (*set_intr_ready)(struct vlapic *vlapic, int vector,
111 	    bool level);
112 	void (*sync_state)(struct vlapic *vlapic);
113 	void (*intr_accepted)(struct vlapic *vlapic, int vector);
114 	void (*post_intr)(struct vlapic *vlapic, int hostcpu);
115 	void (*enable_x2apic_mode)(struct vlapic *vlapic);
116 };
117 
118 struct vlapic_stats {
119 	/* Result of a CCR read was clamped due to being > ICR */
120 	uint64_t	vs_clamp_ccr;
121 	/* Imported timer expiration further in future than ICR equiv */
122 	uint64_t	vs_import_timer_overage;
123 };
124 
125 struct vlapic {
126 	struct vm		*vm;
127 	int			vcpuid;
128 	struct LAPIC		*apic_page;
129 	struct vlapic_ops	ops;
130 
131 	uint32_t		esr_pending;
132 
133 	struct callout	callout;	/* vlapic timer */
134 	hrtime_t	timer_fire_when;
135 	hrtime_t	timer_period;
136 	uint32_t	timer_cur_freq;
137 
138 	kmutex_t	timer_lock;
139 
140 	uint64_t	msr_apicbase;
141 
142 	/*
143 	 * Copies of some registers in the virtual APIC page. We do this for
144 	 * a couple of different reasons:
145 	 * - to be able to detect what changed (e.g. svr_last)
146 	 * - to maintain a coherent snapshot of the register (e.g. lvt_last)
147 	 */
148 	uint32_t	svr_last;
149 	uint32_t	lvt_last[VLAPIC_MAXLVT_INDEX + 1];
150 
151 	/* Occurrences of unusual events are tracked in this stats struct. */
152 	struct vlapic_stats	stats;
153 };
154 
155 void vlapic_init(struct vlapic *vlapic);
156 void vlapic_cleanup(struct vlapic *vlapic);
157 
158 #endif	/* _VLAPIC_PRIV_H_ */
159