1 /*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (C) 2019 Advanced Micro Devices, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * BSD LICENSE 14 * 15 * Copyright (C) 2019 Advanced Micro Devices, Inc. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copy 23 * notice, this list of conditions and the following disclaimer in 24 * the documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of AMD corporation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Contact Information : 42 * Rajesh Kumar <rajesh1.kumar@amd.com> 43 */ 44 45 #ifndef NTB_HW_AMD_H 46 #define NTB_HW_AMD_H 47 48 #define NTB_HW_AMD_VENDOR_ID 0x1022 49 #define NTB_HW_AMD_DEVICE_ID1 0x145B 50 #define NTB_HW_AMD_DEVICE_ID2 0x148B 51 52 #define NTB_HW_HYGON_VENDOR_ID 0x19D4 53 #define NTB_HW_HYGON_DEVICE_ID1 0x145B 54 55 #define NTB_DEF_PEER_CNT 1 56 #define NTB_DEF_PEER_IDX 0 57 58 #define BIT(n) (1 << n) 59 #define AMD_LINK_HB_TIMEOUT (1 * hz) 60 61 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002 62 #define NTB_LNK_STA_SPEED_MASK 0x000F0000 63 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000 64 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LIN_STA_ACTIVE_BIT)) 65 #define NTB_LNK_STA_SPEED(x) (((x) & NTB_LNK_STA_SPEED_MASK) >> 16) 66 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20) 67 68 #define amd_ntb_bar_read(SIZE, bar, offset) \ 69 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 70 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 71 #define amd_ntb_bar_write(SIZE, bar, offset, val) \ 72 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 73 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 74 #define amd_ntb_reg_read(SIZE, offset) \ 75 amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 76 #define amd_ntb_reg_write(SIZE, offset, val) \ 77 amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 78 #define amd_ntb_peer_reg_read(SIZE, offset) \ 79 amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET) 80 #define amd_ntb_peer_reg_write(SIZE, offset, val) \ 81 amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET, val) 82 83 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 84 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 85 #define DB_MASK_ASSERT(sc, f) mtx_assert(&(sc)->db_mask_lock, (f)) 86 87 #define QUIRK_MW0_32BIT 0x01 88 89 /* amd_ntb_conn_type are hardware numbers, cannot change. */ 90 enum amd_ntb_conn_type { 91 NTB_CONN_NONE = -1, 92 NTB_CONN_PRI, 93 NTB_CONN_SEC, 94 }; 95 96 enum ntb_default_port { 97 NTB_PORT_PRI_USD, 98 NTB_PORT_SEC_DSD 99 }; 100 101 enum amd_ntb_bar { 102 NTB_CONFIG_BAR = 0, 103 NTB_BAR_1, 104 NTB_BAR_2, 105 NTB_BAR_3, 106 NTB_MAX_BARS 107 }; 108 109 struct amd_ntb_hw_info { 110 uint16_t vendor_id; 111 uint16_t device_id; 112 uint8_t mw_count; 113 uint8_t bar_start_idx; 114 uint8_t spad_count; 115 uint8_t db_count; 116 uint8_t msix_vector_count; 117 uint8_t quirks; 118 char *desc; 119 }; 120 121 struct amd_ntb_pci_bar_info { 122 bus_space_tag_t pci_bus_tag; 123 bus_space_handle_t pci_bus_handle; 124 struct resource *pci_resource; 125 vm_paddr_t pbase; 126 caddr_t vbase; 127 vm_size_t size; 128 vm_memattr_t map_mode; 129 int pci_resource_id; 130 131 /* Configuration register offsets */ 132 uint32_t xlat_off; 133 uint32_t limit_off; 134 }; 135 136 struct amd_ntb_int_info { 137 struct resource *res; 138 void *tag; 139 int rid; 140 }; 141 142 struct amd_ntb_vec { 143 struct amd_ntb_softc *ntb; 144 uint32_t num; 145 unsigned masked; 146 }; 147 148 enum { 149 /* AMD NTB Link Status Offset */ 150 AMD_LINK_STATUS_OFFSET = 0x68, 151 152 /* AMD NTB register offset */ 153 AMD_CNTL_OFFSET = 0x200, 154 155 /* NTB control register bits */ 156 PMM_REG_CTL = BIT(21), 157 SMM_REG_CTL = BIT(20), 158 SMM_REG_ACC_PATH = BIT(18), 159 PMM_REG_ACC_PATH = BIT(17), 160 NTB_CLK_EN = BIT(16), 161 162 AMD_STA_OFFSET = 0x204, 163 AMD_PGSLV_OFFSET = 0x208, 164 AMD_SPAD_MUX_OFFSET = 0x20C, 165 AMD_SPAD_OFFSET = 0x210, 166 AMD_RSMU_HCID = 0x250, 167 AMD_RSMU_SIID = 0x254, 168 AMD_PSION_OFFSET = 0x300, 169 AMD_SSION_OFFSET = 0x330, 170 AMD_MMINDEX_OFFSET = 0x400, 171 AMD_MMDATA_OFFSET = 0x404, 172 AMD_SIDEINFO_OFFSET = 0x408, 173 174 AMD_SIDE_MASK = BIT(0), 175 AMD_SIDE_READY = BIT(1), 176 177 /* limit register */ 178 AMD_ROMBARLMT_OFFSET = 0x410, 179 AMD_BAR1LMT_OFFSET = 0x414, 180 AMD_BAR23LMT_OFFSET = 0x418, 181 AMD_BAR45LMT_OFFSET = 0x420, 182 183 /* xlat address */ 184 AMD_ROMBARXLAT_OFFSET = 0x428, 185 AMD_BAR1XLAT_OFFSET = 0x430, 186 AMD_BAR23XLAT_OFFSET = 0x438, 187 AMD_BAR45XLAT_OFFSET = 0x440, 188 189 /* doorbell and interrupt */ 190 AMD_DBFM_OFFSET = 0x450, 191 AMD_DBREQ_OFFSET = 0x454, 192 AMD_MIRRDBSTAT_OFFSET = 0x458, 193 AMD_DBMASK_OFFSET = 0x45C, 194 AMD_DBSTAT_OFFSET = 0x460, 195 AMD_INTMASK_OFFSET = 0x470, 196 AMD_INTSTAT_OFFSET = 0x474, 197 198 /* event type */ 199 AMD_PEER_FLUSH_EVENT = BIT(0), 200 AMD_PEER_RESET_EVENT = BIT(1), 201 AMD_PEER_D3_EVENT = BIT(2), 202 AMD_PEER_PMETO_EVENT = BIT(3), 203 AMD_PEER_D0_EVENT = BIT(4), 204 AMD_LINK_UP_EVENT = BIT(5), 205 AMD_LINK_DOWN_EVENT = BIT(6), 206 AMD_EVENT_INTMASK = (AMD_PEER_FLUSH_EVENT | 207 AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT | 208 AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT | 209 AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT), 210 211 AMD_PMESTAT_OFFSET = 0x480, 212 AMD_PMSGTRIG_OFFSET = 0x490, 213 AMD_LTRLATENCY_OFFSET = 0x494, 214 AMD_FLUSHTRIG_OFFSET = 0x498, 215 216 /* SMU register*/ 217 AMD_SMUACK_OFFSET = 0x4A0, 218 AMD_SINRST_OFFSET = 0x4A4, 219 AMD_RSPNUM_OFFSET = 0x4A8, 220 AMD_SMU_SPADMUTEX = 0x4B0, 221 AMD_SMU_SPADOFFSET = 0x4B4, 222 223 AMD_PEER_OFFSET = 0x400, 224 }; 225 226 struct amd_ntb_softc { 227 /* ntb.c context. Do not move! Must go first! */ 228 void *ntb_store; 229 230 device_t device; 231 enum amd_ntb_conn_type conn_type; 232 233 struct amd_ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 234 struct amd_ntb_int_info int_info[16]; 235 struct amd_ntb_vec *msix_vec; 236 uint16_t allocated_interrupts; 237 238 struct callout hb_timer; 239 240 struct amd_ntb_hw_info *hw_info; 241 uint8_t spad_count; 242 uint8_t msix_vec_count; 243 244 struct mtx db_mask_lock; 245 246 volatile uint32_t ntb_ctl; 247 volatile uint32_t lnk_sta; 248 volatile uint32_t peer_sta; 249 volatile uint32_t cntl_sta; 250 251 uint16_t db_valid_mask; 252 uint16_t db_mask; 253 uint32_t int_mask; 254 255 unsigned int self_spad; 256 unsigned int peer_spad; 257 }; 258 259 static void amd_init_side_info(struct amd_ntb_softc *ntb); 260 static void amd_deinit_side_info(struct amd_ntb_softc *ntb); 261 static int amd_ntb_detach(device_t device); 262 263 #endif 264