xref: /titanic_52/usr/src/uts/intel/sys/mca_amd.h (revision 25f476773dea2a0ee593dcf662a38d5f02487196)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_MCA_AMD_H
28 #define	_SYS_MCA_AMD_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #include <sys/mca_x86.h>
33 
34 /*
35  * Constants for the Machine Check Architecture as implemented on AMD CPUs.
36  */
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 #define	AMD_MSR_MCG_CAP			0x179
43 #define	AMD_MSR_MCG_STATUS		0x17a
44 #define	AMD_MSR_MCG_CTL			0x17b
45 
46 #define	AMD_MCA_BANK_DC			0	/* Data Cache */
47 #define	AMD_MCA_BANK_IC			1	/* Instruction Cache */
48 #define	AMD_MCA_BANK_BU			2	/* Bus Unit */
49 #define	AMD_MCA_BANK_LS			3	/* Load/Store Unit */
50 #define	AMD_MCA_BANK_NB			4	/* Northbridge */
51 #define	AMD_MCA_BANK_COUNT		5
52 
53 #define	AMD_MSR_DC_CTL			0x400
54 #define	AMD_MSR_DC_MASK			0xc0010044
55 #define	AMD_MSR_DC_STATUS		0x401
56 #define	AMD_MSR_DC_ADDR			0x402
57 #define	AMD_MSR_DC_MISC			0x403
58 
59 #define	AMD_MSR_IC_CTL			0x404
60 #define	AMD_MSR_IC_MASK			0xc0010045
61 #define	AMD_MSR_IC_STATUS		0x405
62 #define	AMD_MSR_IC_ADDR			0x406
63 #define	AMD_MSR_IC_MISC			0x407
64 
65 #define	AMD_MSR_BU_CTL			0x408
66 #define	AMD_MSR_BU_MASK			0xc0010046
67 #define	AMD_MSR_BU_STATUS		0x409
68 #define	AMD_MSR_BU_ADDR			0x40a
69 #define	AMD_MSR_BU_MISC			0x40b
70 
71 #define	AMD_MSR_LS_CTL			0x40c
72 #define	AMD_MSR_LS_MASK			0xc0010047
73 #define	AMD_MSR_LS_STATUS		0x40d
74 #define	AMD_MSR_LS_ADDR			0x40e
75 #define	AMD_MSR_LS_MISC			0x40f
76 
77 #define	AMD_MSR_NB_CTL			0x410
78 #define	AMD_MSR_NB_MASK			0xc0010048
79 #define	AMD_MSR_NB_STATUS		0x411
80 #define	AMD_MSR_NB_ADDR			0x412
81 #define	AMD_MSR_NB_MISC			0x413
82 
83 #define	AMD_MCG_EN_DC			0x01
84 #define	AMD_MCG_EN_IC			0x02
85 #define	AMD_MCG_EN_BU			0x04
86 #define	AMD_MCG_EN_LS			0x08
87 #define	AMD_MCG_EN_NB			0x10
88 
89 /*
90  * Data Cache (DC) bank error-detection enabling bits and CTL register
91  * initializer value.
92  */
93 
94 #define	AMD_DC_EN_ECCI			0x00000001ULL
95 #define	AMD_DC_EN_ECCM			0x00000002ULL
96 #define	AMD_DC_EN_DECC			0x00000004ULL
97 #define	AMD_DC_EN_DMTP			0x00000008ULL
98 #define	AMD_DC_EN_DSTP			0x00000010ULL
99 #define	AMD_DC_EN_L1TP			0x00000020ULL
100 #define	AMD_DC_EN_L2TP			0x00000040ULL
101 
102 #define	AMD_DC_CTL_INIT_CMN \
103 	(AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \
104 	AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP)
105 
106 /*
107  * Instruction Cache (IC) bank error-detection enabling bits and CTL register
108  * initializer value.
109  *
110  * The Northbridge will handle Read Data errors.  Our initializer will enable
111  * all but the RDDE detector.
112  */
113 
114 #define	AMD_IC_EN_ECCI			0x00000001ULL
115 #define	AMD_IC_EN_ECCM			0x00000002ULL
116 #define	AMD_IC_EN_IDP			0x00000004ULL
117 #define	AMD_IC_EN_IMTP			0x00000008ULL
118 #define	AMD_IC_EN_ISTP			0x00000010ULL
119 #define	AMD_IC_EN_L1TP			0x00000020ULL
120 #define	AMD_IC_EN_L2TP			0x00000040ULL
121 #define	AMD_IC_EN_RDDE			0x00000200ULL
122 
123 #define	AMD_IC_CTL_INIT_CMN \
124 	(AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \
125 	AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP)
126 
127 /*
128  * Bus Unit (BU) bank error-detection enabling bits and CTL register
129  * initializer value.
130  *
131  * The Northbridge will handle Read Data errors.  Our initializer will enable
132  * all but the S_RDE_* detectors.
133  */
134 
135 #define	AMD_BU_EN_S_RDE_HP		0x00000001ULL
136 #define	AMD_BU_EN_S_RDE_TLB		0x00000002ULL
137 #define	AMD_BU_EN_S_RDE_ALL		0x00000004ULL
138 #define	AMD_BU_EN_S_ECC1_TLB		0x00000008ULL
139 #define	AMD_BU_EN_S_ECC1_HP		0x00000010ULL
140 #define	AMD_BU_EN_S_ECCM_TLB		0x00000020ULL
141 #define	AMD_BU_EN_S_ECCM_HP		0x00000040ULL
142 #define	AMD_BU_EN_L2T_PAR_ICDC		0x00000080ULL
143 #define	AMD_BU_EN_L2T_PAR_TLB		0x00000100ULL
144 #define	AMD_BU_EN_L2T_PAR_SNP		0x00000200ULL
145 #define	AMD_BU_EN_L2T_PAR_CPB		0x00000400ULL
146 #define	AMD_BU_EN_L2T_PAR_SCR		0x00000800ULL
147 #define	AMD_BU_EN_L2D_ECC1_TLB		0x00001000ULL
148 #define	AMD_BU_EN_L2D_ECC1_SNP		0x00002000ULL
149 #define	AMD_BU_EN_L2D_ECC1_CPB		0x00004000ULL
150 #define	AMD_BU_EN_L2D_ECCM_TLB		0x00008000ULL
151 #define	AMD_BU_EN_L2D_ECCM_SNP		0x00010000ULL
152 #define	AMD_BU_EN_L2D_ECCM_CPB		0x00020000ULL
153 #define	AMD_BU_EN_L2T_ECC1_SCR		0x00040000ULL
154 #define	AMD_BU_EN_L2T_ECCM_SCR		0x00080000ULL
155 
156 #define	AMD_BU_CTL_INIT_CMN \
157 	(AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \
158 	AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \
159 	AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \
160 	AMD_BU_EN_L2T_PAR_SNP |	AMD_BU_EN_L2T_PAR_CPB | \
161 	AMD_BU_EN_L2T_PAR_SCR |	AMD_BU_EN_L2D_ECC1_TLB | \
162 	AMD_BU_EN_L2D_ECC1_SNP | AMD_BU_EN_L2D_ECC1_CPB | \
163 	AMD_BU_EN_L2D_ECCM_TLB | AMD_BU_EN_L2D_ECCM_SNP | \
164 	AMD_BU_EN_L2D_ECCM_CPB | AMD_BU_EN_L2T_ECC1_SCR | \
165 	AMD_BU_EN_L2T_ECCM_SCR)
166 
167 /*
168  * Load/Store (LS) bank error-detection enabling bits and CTL register
169  * initializer value.
170  *
171  * The Northbridge will handle Read Data errors.  That's the only type of
172  * error the LS unit can detect at present, so we won't be enabling any
173  * LS detectors.
174  */
175 
176 #define	AMD_LS_EN_S_RDE_S		0x00000001ULL
177 #define	AMD_LS_EN_S_RDE_L		0x00000002ULL
178 
179 #define	AMD_LS_CTL_INIT_CMN			0ULL
180 
181 /*
182  * NorthBridge (NB) MCi_MISC - DRAM Errors Threshold Register.
183  */
184 #define	AMD_NB_MISC_VALID		(0x1ULL << 63)
185 #define	AMD_NB_MISC_CTRP		(0x1ULL << 62)
186 #define	AMD_NB_MISC_LOCKED		(0x1ULL << 61)
187 #define	AMD_NB_MISC_CNTEN		(0x1ULL << 51)
188 #define	AMD_NB_MISC_INTTYPE		(0x1ULL << 49)
189 #define	AMD_NB_MISC_INTTYPE_MASK	(0x3ULL << 49)
190 #define	AMD_NB_MISC_OVRFLW		(0x1ULL << 48)
191 #define	AMD_NB_MISC_ERRCOUNT_MASK	(0xfffULL << 32)
192 
193 /*
194  * The Northbridge (NB) is configured using both the standard MCA CTL register
195  * and a NB-specific configuration register (NB CFG).  The AMD_NB_EN_* macros
196  * are the detector enabling bits for the NB MCA CTL register.  The
197  * AMD_NB_CFG_* bits are for the NB CFG register.
198  *
199  * The CTL register can be initialized statically, but portions of the NB CFG
200  * register must be initialized based on the current machine's configuration.
201  *
202  * The MCA NB Control Register maps to MC4_CTL[31:0], but we initialize it
203  * via and MSR write of 64 bits so define all as ULL.
204  *
205  */
206 #define	AMD_NB_EN_CORRECC		0x00000001ULL
207 #define	AMD_NB_EN_UNCORRECC		0x00000002ULL
208 #define	AMD_NB_EN_CRCERR0		0x00000004ULL
209 #define	AMD_NB_EN_CRCERR1		0x00000008ULL
210 #define	AMD_NB_EN_CRCERR2		0x00000010ULL
211 #define	AMD_NB_EN_SYNCPKT0		0x00000020ULL
212 #define	AMD_NB_EN_SYNCPKT1		0x00000040ULL
213 #define	AMD_NB_EN_SYNCPKT2		0x00000080ULL
214 #define	AMD_NB_EN_MSTRABRT		0x00000100ULL
215 #define	AMD_NB_EN_TGTABRT		0x00000200ULL
216 #define	AMD_NB_EN_GARTTBLWK		0x00000400ULL
217 #define	AMD_NB_EN_ATOMICRMW		0x00000800ULL
218 #define	AMD_NB_EN_WCHDOGTMR		0x00001000ULL
219 #define	AMD_NB_EN_DRAMPAR		0x00040000ULL	/* revs F and G */
220 
221 #define	AMD_NB_CTL_INIT_CMN /* Revs B to G; All but GARTTBLWK */ \
222 	(AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \
223 	AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \
224 	AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \
225 	AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \
226 	AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR)
227 
228 #define	AMD_NB_CTL_INIT_REV_FG /* Additional bits for revs F and G */ \
229 	AMD_NB_EN_DRAMPAR
230 
231 /*
232  * NB MCA Configuration register
233  */
234 #define	AMD_NB_CFG_CPUECCERREN			0x00000001
235 #define	AMD_NB_CFG_CPURDDATERREN		0x00000002
236 #define	AMD_NB_CFG_SYNCONUCECCEN		0x00000004
237 #define	AMD_NB_CFG_SYNCPKTGENDIS		0x00000008
238 #define	AMD_NB_CFG_SYNCPKTPROPDIS		0x00000010
239 #define	AMD_NB_CFG_IOMSTABORTDIS		0x00000020
240 #define	AMD_NB_CFG_CPUERRDIS			0x00000040
241 #define	AMD_NB_CFG_IOERRDIS			0x00000080
242 #define	AMD_NB_CFG_WDOGTMRDIS			0x00000100
243 #define	AMD_NB_CFG_SYNCONWDOGEN			0x00100000
244 #define	AMD_NB_CFG_SYNCONANYERREN		0x00200000
245 #define	AMD_NB_CFG_ECCEN			0x00400000
246 #define	AMD_NB_CFG_CHIPKILLECCEN		0x00800000
247 #define	AMD_NB_CFG_IORDDATERREN			0x01000000
248 #define	AMD_NB_CFG_DISPCICFGCPUERRRSP		0x02000000
249 #define	AMD_NB_CFG_NBMCATOMSTCPUEN		0x08000000
250 #define	AMD_NB_CFG_DISTGTABTCPUERRRSP		0x10000000
251 #define	AMD_NB_CFG_DISMSTABTCPUERRRSP		0x20000000
252 #define	AMD_NB_CFG_SYNCONDRAMADRPARERREN	0x40000000 /* Revs F & G */
253 
254 /*
255  * We do not initialize the NB config with an absolute value; instead we
256  * selectively add some bits and remove others.  Note that
257  * AMD_NB_CFG_{ADD,REMOVE}_{CMN,REV_FG} below are not the whole
258  * story here - additional config is performed regarding the watchdog (see
259  * ao_mca.c for details).
260  */
261 #define	AMD_NB_CFG_ADD_CMN		/* Revs B to G */ \
262 	(AMD_NB_CFG_DISPCICFGCPUERRRSP | AMD_NB_CFG_SYNCONUCECCEN | \
263 	AMD_NB_CFG_CPUECCERREN)
264 
265 #define	AMD_NB_CFG_REMOVE_CMN		/* Revs B to G */ \
266 	(AMD_NB_CFG_NBMCATOMSTCPUEN | \
267 	AMD_NB_CFG_IORDDATERREN | AMD_NB_CFG_SYNCONANYERREN | \
268 	AMD_NB_CFG_SYNCONWDOGEN | AMD_NB_CFG_IOERRDIS | \
269 	AMD_NB_CFG_IOMSTABORTDIS | AMD_NB_CFG_SYNCPKTPROPDIS | \
270 	AMD_NB_CFG_SYNCPKTGENDIS)
271 
272 #define	AMD_NB_CFG_ADD_REV_FG		/* Revs F and G */ \
273 	AMD_NB_CFG_SYNCONDRAMADRPARERREN
274 
275 #define	AMD_NB_CFG_REMOVE_REV_FG 0x0	/* Revs F and G */
276 
277 #define	AMD_NB_CFG_WDOGTMRCNTSEL_4095	0x00000000
278 #define	AMD_NB_CFG_WDOGTMRCNTSEL_2047	0x00000200
279 #define	AMD_NB_CFG_WDOGTMRCNTSEL_1023	0x00000400
280 #define	AMD_NB_CFG_WDOGTMRCNTSEL_511	0x00000600
281 #define	AMD_NB_CFG_WDOGTMRCNTSEL_255	0x00000800
282 #define	AMD_NB_CFG_WDOGTMRCNTSEL_127	0x00000a00
283 #define	AMD_NB_CFG_WDOGTMRCNTSEL_63	0x00000c00
284 #define	AMD_NB_CFG_WDOGTMRCNTSEL_31	0x00000e00
285 #define	AMD_NB_CFG_WDOGTMRCNTSEL_MASK	0x00000e00
286 #define	AMD_NB_CFG_WDOGTMRCNTSEL_SHIFT	9
287 
288 #define	AMD_NB_CFG_WDOGTMRBASESEL_1MS	0x00000000
289 #define	AMD_NB_CFG_WDOGTMRBASESEL_1US	0x00001000
290 #define	AMD_NB_CFG_WDOGTMRBASESEL_5NS	0x00002000
291 #define	AMD_NB_CFG_WDOGTMRBASESEL_MASK	0x00003000
292 #define	AMD_NB_CFG_WDOGTMRBASESEL_SHIFT	12
293 
294 #define	AMD_NB_CFG_LDTLINKSEL_MASK	0x0000c000
295 #define	AMD_NB_CFG_LDTLINKSEL_SHIFT	14
296 
297 #define	AMD_NB_CFG_GENCRCERRBYTE0	0x00010000
298 #define	AMD_NB_CFG_GENCRCERRBYTE1	0x00020000
299 
300 /*
301  * The AMD extended error code is just one nibble of the upper 16 bits
302  * of the bank status (the resy being used for syndrome etc).  So we use
303  * AMD_EXT_ERRCODE to retrieve that extended error code, not the generic
304  * MCAX86_MSERRCODE.
305  */
306 #define	_AMD_ERREXT_MASK		0x00000000000f0000ULL
307 #define	_AMD_ERREXT_SHIFT		16
308 #define	AMD_EXT_ERRCODE(stat) \
309 	(((stat) & _AMD_ERREXT_MASK) >> _AMD_ERREXT_SHIFT)
310 #define	AMD_EXT_MKERRCODE(errcode) \
311 	(((errcode) << _AMD_ERREXT_SHIFT) & _AMD_ERREXT_MASK)
312 
313 #define	AMD_BANK_STAT_CECC		0x0000400000000000ULL
314 #define	AMD_BANK_STAT_UECC		0x0000200000000000ULL
315 #define	AMD_BANK_STAT_SCRUB		0x0000010000000000ULL
316 
317 	/* syndrome[7:0] */
318 #define	AMD_BANK_STAT_SYND_MASK		0x007f800000000000ULL
319 #define	AMD_BANK_STAT_SYND_SHIFT	47
320 
321 #define	AMD_BANK_SYND(stat) \
322 	(((stat) & AMD_BANK_STAT_SYND_MASK) >> AMD_BANK_STAT_SYND_SHIFT)
323 #define	AMD_BANK_MKSYND(synd) \
324 	(((uint64_t)(synd) << AMD_BANK_STAT_SYND_SHIFT) & \
325 	AMD_BANK_STAT_SYND_MASK)
326 
327 #define	AMD_NB_STAT_DRAMCHANNEL		0x0000020000000000ULL
328 #define	AMD_NB_STAT_LDTLINK_MASK	0x0000007000000000ULL
329 #define	AMD_NB_STAT_LDTLINK_SHIFT	4
330 #define	AMD_NB_STAT_ERRCPU1		0x0000000200000000ULL
331 #define	AMD_NB_STAT_ERRCPU0		0x0000000100000000ULL
332 
333 #define	AMD_NB_STAT_CKSYND_MASK		0x00000000ff000000 /* syndrome[15:8] */
334 #define	AMD_NB_STAT_CKSYND_SHIFT	(24 - 8) /* shift [31:24] to [15:8] */
335 
336 #define	AMD_NB_STAT_CKSYND(stat) \
337 	((((stat) & AMD_NB_STAT_CKSYND_MASK) >> AMD_NB_STAT_CKSYND_SHIFT) | \
338 	AMD_BANK_SYND((stat)))
339 
340 #define	AMD_NB_STAT_MKCKSYND(synd) \
341 	((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \
342 	AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd))
343 
344 #define	AMD_ERREXT_MASK			0x00000000000f0000ULL
345 #define	AMD_ERREXT_SHIFT		16
346 
347 #define	AMD_ERRCODE_TLB_BIT		4
348 #define	AMD_ERRCODE_MEM_BIT		8
349 #define	AMD_ERRCODE_BUS_BIT		11
350 
351 #define	AMD_ERRCODE_TLB_MASK		0xfff0
352 #define	AMD_ERRCODE_MEM_MASK		0xff00
353 #define	AMD_ERRCODE_BUS_MASK		0xf800
354 
355 #define	AMD_ERRCODE_MKTLB(tt, ll) MCAX86_MKERRCODE_TLB(tt, ll)
356 #define	AMD_ERRCODE_ISTLB(code) MCAX86_ERRCODE_ISTLB(code)
357 
358 #define	AMD_ERRCODE_MKMEM(r4, tt, ll) MCAX86_MKERRCODE_MEMHIER(r4, tt, ll)
359 #define	AMD_ERRCODE_ISMEM(code) MCAX86_ERRCODE_ISMEMHIER(code)
360 
361 #define	AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \
362 	MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, r4, ii, ll)
363 #define	AMD_ERRCODE_ISBUS(code) MCAX86_ERRCODE_ISBUS_INTERCONNECT(code)
364 
365 #define	AMD_NB_ADDRLO_MASK		0xfffffff8
366 #define	AMD_NB_ADDRHI_MASK		0x000000ff
367 
368 #define	AMD_SYNDTYPE_ECC		0
369 #define	AMD_SYNDTYPE_CHIPKILL		1
370 
371 #define	AMD_NB_SCRUBCTL_DRAM_MASK	0x0000001f
372 #define	AMD_NB_SCRUBCTL_DRAM_SHIFT	0
373 #define	AMD_NB_SCRUBCTL_L2_MASK		0x00001f00
374 #define	AMD_NB_SCRUBCTL_L2_SHIFT	8
375 #define	AMD_NB_SCRUBCTL_DC_MASK		0x001f0000
376 #define	AMD_NB_SCRUBCTL_DC_SHIFT	16
377 #define	AMD_NB_SCRUBCTL_L3_MASK		0x1f000000
378 #define	AMD_NB_SCRUBCTL_L3_SHIFT	24
379 
380 #define	AMD_NB_SCRUBCTL_RATE_NONE	0
381 #define	AMD_NB_SCRUBCTL_RATE_MAX	0x16
382 
383 #define	AMD_NB_SCRUBADDR_LO_MASK	0xffffffc0
384 #define	AMD_NB_SCRUBADDR_LO_SHIFT	6
385 #define	AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1
386 #define	AMD_NB_SCRUBADDR_HI_MASK	0x000000ff
387 
388 #define	AMD_NB_SCRUBADDR_MKLO(addr) \
389 	(((addr) & AMD_NB_SCRUBADDR_LO_MASK) >> AMD_NB_SCRUBADDR_LO_SHIFT)
390 
391 #define	AMD_NB_SCRUBADDR_MKHI(addr) \
392 	(((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK)
393 
394 #define	AMD_NB_MKSCRUBCTL(l3, dc, l2, dr) ( \
395 	(((l3) << AMD_NB_SCRUBCTL_L3_SHIFT) & AMD_NB_SCRUBCTL_L3_MASK) | \
396 	(((dc) << AMD_NB_SCRUBCTL_DC_SHIFT) & AMD_NB_SCRUBCTL_DC_MASK) | \
397 	(((l2) << AMD_NB_SCRUBCTL_L2_SHIFT) & AMD_NB_SCRUBCTL_L2_MASK) | \
398 	(((dr) << AMD_NB_SCRUBCTL_DRAM_SHIFT) & AMD_NB_SCRUBCTL_DRAM_MASK))
399 
400 #ifdef __cplusplus
401 }
402 #endif
403 
404 #endif /* _SYS_MCA_AMD_H */
405