1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _AMD_IOMMU_LOG_H 27 #define _AMD_IOMMU_LOG_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/amd_iommu.h> 34 35 #ifdef _KERNEL 36 37 #define EV2OFF(e) ((e) << 4) 38 #define OFF2EV(o) ((o) >> 4) 39 40 typedef enum { 41 AMD_IOMMU_EVENT_INVALID = 0, 42 AMD_IOMMU_EVENT_DEVTAB_ILLEGAL_ENTRY = 1, 43 AMD_IOMMU_EVENT_IO_PAGE_FAULT = 2, 44 AMD_IOMMU_EVENT_DEVTAB_HW_ERROR = 3, 45 AMD_IOMMU_EVENT_PGTABLE_HW_ERROR = 4, 46 AMD_IOMMU_EVENT_CMDBUF_ILLEGAL_CMD = 5, 47 AMD_IOMMU_EVENT_CMDBUF_HW_ERROR = 6, 48 AMD_IOMMU_EVENT_IOTLB_INVAL_TO = 7, 49 AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ = 8 50 } amd_iommu_event_t; 51 52 /* Common to all events */ 53 #define AMD_IOMMU_EVENT_TYPE (31 << 16 | 28) 54 55 /* Illegal device Table Entry Event bits */ 56 #define AMD_IOMMU_EVENT_DEVTAB_ILL_DEVICEID (15 << 16 | 0) 57 #define AMD_IOMMU_EVENT_DEVTAB_ILL_TR (24 << 16 | 24) 58 #define AMD_IOMMU_EVENT_DEVTAB_ILL_RZ (23 << 16 | 23) 59 #define AMD_IOMMU_EVENT_DEVTAB_ILL_RW (21 << 16 | 21) 60 #define AMD_IOMMU_EVENT_DEVTAB_ILL_INTR (19 << 16 | 19) 61 #define AMD_IOMMU_EVENT_DEVTAB_ILL_VADDR_LO (31 << 16 | 2) 62 63 /* IO Page Fault event bits */ 64 #define AMD_IOMMU_EVENT_IO_PGFAULT_DEVICEID (15 << 16 | 0) 65 #define AMD_IOMMU_EVENT_IO_PGFAULT_TR (24 << 16 | 24) 66 #define AMD_IOMMU_EVENT_IO_PGFAULT_RZ (23 << 16 | 23) 67 #define AMD_IOMMU_EVENT_IO_PGFAULT_PE (22 << 16 | 22) 68 #define AMD_IOMMU_EVENT_IO_PGFAULT_RW (21 << 16 | 21) 69 #define AMD_IOMMU_EVENT_IO_PGFAULT_PR (20 << 16 | 20) 70 #define AMD_IOMMU_EVENT_IO_PGFAULT_INTR (19 << 16 | 19) 71 #define AMD_IOMMU_EVENT_IO_PGFAULT_DOMAINID (15 << 16 | 0) 72 73 74 /* Device Table HW Error event bits */ 75 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_DEVICEID (15 << 16 | 0) 76 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_TYPE (26 << 16 | 25) 77 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_TR (24 << 16 | 24) 78 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_RW (21 << 16 | 21) 79 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_INTR (19 << 16 | 19) 80 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_PHYSADDR_LO (31 << 16 | 4) 81 82 83 /* Page Table HW Error event bits */ 84 #define AMD_IOMMU_EVENT_PGTABLE_HWERR_DEVICEID (15 << 16 | 0) 85 #define AMD_IOMMU_EVENT_DEVTAB_HWERR_TYPE (26 << 16 | 25) 86 #define AMD_IOMMU_EVENT_PGTABLE_HWERR_TR (24 << 16 | 24) 87 #define AMD_IOMMU_EVENT_PGTABLE_HWERR_RW (21 << 16 | 21) 88 #define AMD_IOMMU_EVENT_PGTABLE_HWERR_INTR (19 << 16 | 19) 89 #define AMD_IOMMU_EVENT_PGTABLE_HWERR_DOMAINID (15 << 16 | 0) 90 #define AMD_IOMMU_EVENT_PGTABLE_HWERR_PHYSADDR_LO (31 << 16 | 3) 91 92 /* Illegal Command Error event bits */ 93 #define AMD_IOMMU_EVENT_CMDBUF_ILLEGAL_CMD_PHYS_LO (31 << 16 | 4) 94 95 /* Command Buffer HW Error event bits */ 96 #define AMD_IOMMU_EVENT_CMDBUF_HWERR_TYPE (26 << 16 | 25) 97 #define AMD_IOMMU_EVENT_CMDBUF_HWERR_PHYS_LO (31 << 16 | 4) 98 99 100 /* IOTLB Invalidation TO event bits */ 101 #define AMD_IOMMU_EVENT_IOTLB_INVAL_TO_DEVICEID (15 << 16 | 0) 102 #define AMD_IOMMU_EVENT_IOTLB_INVAL_TO_TYPE (26 << 16 | 25) 103 #define AMD_IOMMU_EVENT_IOTLB_INVAL_TO_PHYS_LO (31 << 16 | 4) 104 105 /* Illegal Device request event bits */ 106 #define AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ_DEVICEID (15 << 16 | 0) 107 #define AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ_TYPE (27 << 16 | 25) 108 #define AMD_IOMMU_EVENT_DEVICE_ILLEGAL_REQ_TR (24 << 16 | 24) 109 110 #endif /* _KERNEL */ 111 112 #ifdef __cplusplus 113 } 114 #endif 115 116 #endif /* _AMD_IOMMU_LOG_H */ 117