1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_XGMI_H__ 23 #define __AMDGPU_XGMI_H__ 24 25 #include <drm/task_barrier.h> 26 #include "amdgpu_ras.h" 27 28 struct amdgpu_hive_info { 29 struct kobject kobj; 30 uint64_t hive_id; 31 struct list_head device_list; 32 struct list_head node; 33 atomic_t number_devices; 34 struct mutex hive_lock; 35 int hi_req_count; 36 struct amdgpu_device *hi_req_gpu; 37 struct task_barrier tb; 38 enum { 39 AMDGPU_XGMI_PSTATE_MIN, 40 AMDGPU_XGMI_PSTATE_MAX_VEGA20, 41 AMDGPU_XGMI_PSTATE_UNKNOWN 42 } pstate; 43 44 struct amdgpu_reset_domain *reset_domain; 45 atomic_t ras_recovery; 46 struct ras_event_manager event_mgr; 47 struct work_struct reset_on_init_work; 48 atomic_t requested_nps_mode; 49 }; 50 51 struct amdgpu_pcs_ras_field { 52 const char *err_name; 53 uint32_t pcs_err_mask; 54 uint32_t pcs_err_shift; 55 }; 56 57 /** 58 * Bandwidth range reporting comes in two modes. 59 * 60 * PER_LINK - range for any xgmi link 61 * PER_PEER - range of max of single xgmi link to max of multiple links based on source peer 62 */ 63 enum amdgpu_xgmi_bw_mode { 64 AMDGPU_XGMI_BW_MODE_PER_LINK = 0, 65 AMDGPU_XGMI_BW_MODE_PER_PEER 66 }; 67 68 enum amdgpu_xgmi_bw_unit { 69 AMDGPU_XGMI_BW_UNIT_GBYTES = 0, 70 AMDGPU_XGMI_BW_UNIT_MBYTES 71 }; 72 73 struct amdgpu_xgmi_ras { 74 struct amdgpu_ras_block_object ras_block; 75 }; 76 extern struct amdgpu_xgmi_ras xgmi_ras; 77 78 struct amdgpu_xgmi { 79 /* from psp */ 80 u64 node_id; 81 u64 hive_id; 82 /* fixed per family */ 83 u64 node_segment_size; 84 /* physical node (0-3) */ 85 unsigned physical_node_id; 86 /* number of nodes (0-4) */ 87 unsigned num_physical_nodes; 88 /* gpu list in the same hive */ 89 struct list_head head; 90 bool supported; 91 struct ras_common_if *ras_if; 92 bool connected_to_cpu; 93 struct amdgpu_xgmi_ras *ras; 94 uint16_t max_speed; 95 uint8_t max_width; 96 }; 97 98 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev); 99 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive); 100 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev); 101 int amdgpu_xgmi_add_device(struct amdgpu_device *adev); 102 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev); 103 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate); 104 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, struct amdgpu_device *peer_adev); 105 int amdgpu_xgmi_get_bandwidth(struct amdgpu_device *adev, struct amdgpu_device *peer_adev, 106 enum amdgpu_xgmi_bw_mode bw_mode, enum amdgpu_xgmi_bw_unit bw_unit, 107 uint32_t *min_bw, uint32_t *max_bw); 108 bool amdgpu_xgmi_get_is_sharing_enabled(struct amdgpu_device *adev, 109 struct amdgpu_device *peer_adev); 110 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 111 uint64_t addr); 112 bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev, 113 struct amdgpu_device *bo_adev); 114 int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev); 115 int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev); 116 117 int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev, 118 struct amdgpu_hive_info *hive, 119 int req_nps_mode); 120 int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, 121 int global_link_num); 122 int amdgpu_xgmi_get_ext_link(struct amdgpu_device *adev, int link_num); 123 124 void amdgpu_xgmi_early_init(struct amdgpu_device *adev); 125 uint32_t amdgpu_xgmi_get_max_bandwidth(struct amdgpu_device *adev); 126 127 void amgpu_xgmi_set_max_speed_width(struct amdgpu_device *adev, 128 uint16_t max_speed, uint8_t max_width); 129 #endif 130