1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24 #ifndef _AMDGPU_RAS_H
25 #define _AMDGPU_RAS_H
26
27 #include <linux/debugfs.h>
28 #include <linux/list.h>
29 #include <linux/kfifo.h>
30 #include <linux/radix-tree.h>
31 #include "ta_ras_if.h"
32 #include "amdgpu_ras_eeprom.h"
33 #include "amdgpu_smuio.h"
34 #include "amdgpu_aca.h"
35
36 struct amdgpu_iv_entry;
37
38 #define AMDGPU_RAS_GPU_ERR_MEM_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 0, 0)
39 #define AMDGPU_RAS_GPU_ERR_FW_LOAD(x) AMDGPU_GET_REG_FIELD(x, 1, 1)
40 #define AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 2, 2)
41 #define AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 3, 3)
42 #define AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 4, 4)
43 #define AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(x) AMDGPU_GET_REG_FIELD(x, 5, 5)
44 #define AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(x) AMDGPU_GET_REG_FIELD(x, 6, 6)
45 #define AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(x) AMDGPU_GET_REG_FIELD(x, 7, 7)
46 #define AMDGPU_RAS_GPU_ERR_SOCKET_ID(x) AMDGPU_GET_REG_FIELD(x, 10, 8)
47 #define AMDGPU_RAS_GPU_ERR_AID_ID(x) AMDGPU_GET_REG_FIELD(x, 12, 11)
48 #define AMDGPU_RAS_GPU_ERR_HBM_ID(x) AMDGPU_GET_REG_FIELD(x, 14, 13)
49 #define AMDGPU_RAS_GPU_ERR_DATA_ABORT(x) AMDGPU_GET_REG_FIELD(x, 29, 29)
50 #define AMDGPU_RAS_GPU_ERR_UNKNOWN(x) AMDGPU_GET_REG_FIELD(x, 30, 30)
51
52 #define AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT 100
53 #define AMDGPU_RAS_BOOT_STEADY_STATUS 0xBA
54 #define AMDGPU_RAS_BOOT_STATUS_MASK 0xFF
55
56 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0)
57 /* position of instance value in sub_block_index of
58 * ta_ras_trigger_error_input, the sub block uses lower 12 bits
59 */
60 #define AMDGPU_RAS_INST_MASK 0xfffff000
61 #define AMDGPU_RAS_INST_SHIFT 0xc
62
63 #define AMDGPU_RAS_FEATURES_SOCKETID_SHIFT 29
64 #define AMDGPU_RAS_FEATURES_SOCKETID_MASK 0xe0000000
65
66 /* Reserve 8 physical dram row for possible retirement.
67 * In worst cases, it will lose 8 * 2MB memory in vram domain */
68 #define AMDGPU_RAS_RESERVED_VRAM_SIZE (16ULL << 20)
69 /* The high three bits indicates socketid */
70 #define AMDGPU_RAS_GET_FEATURES(val) ((val) & ~AMDGPU_RAS_FEATURES_SOCKETID_MASK)
71
72 #define RAS_EVENT_INVALID_ID (BIT_ULL(63))
73 #define RAS_EVENT_ID_IS_VALID(x) (!((x) & BIT_ULL(63)))
74
75 #define RAS_EVENT_LOG(adev, id, fmt, ...) \
76 amdgpu_ras_event_log_print((adev), (id), (fmt), ##__VA_ARGS__)
77
78 #define amdgpu_ras_mark_ras_event(adev, type) \
79 (amdgpu_ras_mark_ras_event_caller((adev), (type), __builtin_return_address(0)))
80
81 enum amdgpu_ras_block {
82 AMDGPU_RAS_BLOCK__UMC = 0,
83 AMDGPU_RAS_BLOCK__SDMA,
84 AMDGPU_RAS_BLOCK__GFX,
85 AMDGPU_RAS_BLOCK__MMHUB,
86 AMDGPU_RAS_BLOCK__ATHUB,
87 AMDGPU_RAS_BLOCK__PCIE_BIF,
88 AMDGPU_RAS_BLOCK__HDP,
89 AMDGPU_RAS_BLOCK__XGMI_WAFL,
90 AMDGPU_RAS_BLOCK__DF,
91 AMDGPU_RAS_BLOCK__SMN,
92 AMDGPU_RAS_BLOCK__SEM,
93 AMDGPU_RAS_BLOCK__MP0,
94 AMDGPU_RAS_BLOCK__MP1,
95 AMDGPU_RAS_BLOCK__FUSE,
96 AMDGPU_RAS_BLOCK__MCA,
97 AMDGPU_RAS_BLOCK__VCN,
98 AMDGPU_RAS_BLOCK__JPEG,
99 AMDGPU_RAS_BLOCK__IH,
100 AMDGPU_RAS_BLOCK__MPIO,
101
102 AMDGPU_RAS_BLOCK__LAST,
103 AMDGPU_RAS_BLOCK__ANY = -1
104 };
105
106 enum amdgpu_ras_mca_block {
107 AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
108 AMDGPU_RAS_MCA_BLOCK__MP1,
109 AMDGPU_RAS_MCA_BLOCK__MPIO,
110 AMDGPU_RAS_MCA_BLOCK__IOHC,
111
112 AMDGPU_RAS_MCA_BLOCK__LAST
113 };
114
115 #define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
116 #define AMDGPU_RAS_MCA_BLOCK_COUNT AMDGPU_RAS_MCA_BLOCK__LAST
117 #define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
118
119 enum amdgpu_ras_gfx_subblock {
120 /* CPC */
121 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
122 AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
123 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
124 AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
125 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
126 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
127 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
128 AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
129 AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
130 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
131 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
132 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
133 /* CPF */
134 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
135 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
136 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
137 AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
138 AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
139 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
140 /* CPG */
141 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
142 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
143 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
144 AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
145 AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
146 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
147 /* GDS */
148 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
149 AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
150 AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
151 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
152 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
153 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
154 AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
155 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
156 /* SPI */
157 AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
158 /* SQ */
159 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
160 AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
161 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
162 AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
163 AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
164 AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
165 /* SQC (3 ranges) */
166 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
167 /* SQC range 0 */
168 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
169 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
170 AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
171 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
172 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
173 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
174 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
175 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
176 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
177 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
178 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
179 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
180 /* SQC range 1 */
181 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
182 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
183 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
184 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
185 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
186 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
187 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
188 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
189 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
190 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
191 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
192 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
193 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
194 /* SQC range 2 */
195 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
196 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
197 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
198 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
199 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
200 AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
201 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
202 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
203 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
204 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
205 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
206 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
207 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
208 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
209 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
210 /* TA */
211 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
212 AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
213 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
214 AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
215 AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
216 AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
217 AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
218 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
219 /* TCA */
220 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
221 AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
222 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
223 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
224 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
225 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
226 /* TCC (5 sub-ranges) */
227 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
228 /* TCC range 0 */
229 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
230 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
231 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
232 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
233 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
234 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
235 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
236 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
237 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
238 AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
239 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
240 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
241 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
242 /* TCC range 1 */
243 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
244 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
245 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
246 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
247 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
248 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
249 /* TCC range 2 */
250 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
251 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
252 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
253 AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
254 AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
255 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
256 AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
257 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
258 AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
259 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
260 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
261 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
262 /* TCC range 3 */
263 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
264 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
265 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
266 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
267 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
268 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
269 /* TCC range 4 */
270 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
271 AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
272 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
273 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
274 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
275 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
276 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
277 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
278 /* TCI */
279 AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
280 /* TCP */
281 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
282 AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
283 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
284 AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
285 AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
286 AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
287 AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
288 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
289 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
290 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
291 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
292 /* TD */
293 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
294 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
295 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
296 AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
297 AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
298 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
299 /* EA (3 sub-ranges) */
300 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
301 /* EA range 0 */
302 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
303 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
304 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
305 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
306 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
307 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
308 AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
309 AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
310 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
311 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
312 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
313 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
314 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
315 /* EA range 1 */
316 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
317 AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
318 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
319 AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
320 AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
321 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
322 AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
323 AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
324 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
325 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
326 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
327 /* EA range 2 */
328 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
329 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
330 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
331 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
332 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
333 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
334 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
335 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
336 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
337 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
338 /* UTC VM L2 bank */
339 AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
340 /* UTC VM walker */
341 AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
342 /* UTC ATC L2 2MB cache */
343 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
344 /* UTC ATC L2 4KB cache */
345 AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
346 AMDGPU_RAS_BLOCK__GFX_MAX
347 };
348
349 enum amdgpu_ras_error_type {
350 AMDGPU_RAS_ERROR__NONE = 0,
351 AMDGPU_RAS_ERROR__PARITY = 1,
352 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
353 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
354 AMDGPU_RAS_ERROR__POISON = 8,
355 };
356
357 enum amdgpu_ras_ret {
358 AMDGPU_RAS_SUCCESS = 0,
359 AMDGPU_RAS_FAIL,
360 AMDGPU_RAS_UE,
361 AMDGPU_RAS_CE,
362 AMDGPU_RAS_PT,
363 };
364
365 enum amdgpu_ras_error_query_mode {
366 AMDGPU_RAS_INVALID_ERROR_QUERY = 0,
367 AMDGPU_RAS_DIRECT_ERROR_QUERY = 1,
368 AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2,
369 AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY = 3,
370 };
371
372 /* ras error status reisger fields */
373 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0
374 #define ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L
375 #define ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18
376 #define ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L
377 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2
378 #define ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L
379 #define ERR_STATUS__ERR_CNT__SHIFT 0x17
380 #define ERR_STATUS__ERR_CNT_MASK 0x03800000L
381
382 #define AMDGPU_RAS_REG_ENTRY(ip, inst, reg_lo, reg_hi) \
383 ip##_HWIP, inst, reg_lo##_BASE_IDX, reg_lo, reg_hi##_BASE_IDX, reg_hi
384
385 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \
386 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
387
388 #define AMDGPU_RAS_ERR_INFO_VALID (1 << 0)
389 #define AMDGPU_RAS_ERR_STATUS_VALID (1 << 1)
390 #define AMDGPU_RAS_ERR_ADDRESS_VALID (1 << 2)
391
392 #define AMDGPU_RAS_GPU_RESET_MODE2_RESET (0x1 << 0)
393 #define AMDGPU_RAS_GPU_RESET_MODE1_RESET (0x1 << 1)
394
395 struct amdgpu_ras_err_status_reg_entry {
396 uint32_t hwip;
397 uint32_t ip_inst;
398 uint32_t seg_lo;
399 uint32_t reg_lo;
400 uint32_t seg_hi;
401 uint32_t reg_hi;
402 uint32_t reg_inst;
403 uint32_t flags;
404 const char *block_name;
405 };
406
407 struct amdgpu_ras_memory_id_entry {
408 uint32_t memory_id;
409 const char *name;
410 };
411
412 struct ras_common_if {
413 enum amdgpu_ras_block block;
414 enum amdgpu_ras_error_type type;
415 uint32_t sub_block_index;
416 char name[32];
417 };
418
419 #define MAX_UMC_CHANNEL_NUM 32
420
421 struct ecc_info_per_ch {
422 uint16_t ce_count_lo_chip;
423 uint16_t ce_count_hi_chip;
424 uint64_t mca_umc_status;
425 uint64_t mca_umc_addr;
426 uint64_t mca_ceumc_addr;
427 };
428
429 struct umc_ecc_info {
430 struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
431
432 /* Determine smu ecctable whether support
433 * record correctable error address
434 */
435 int record_ce_addr_supported;
436 };
437
438 enum ras_event_type {
439 RAS_EVENT_TYPE_INVALID = 0,
440 RAS_EVENT_TYPE_FATAL,
441 RAS_EVENT_TYPE_POISON_CREATION,
442 RAS_EVENT_TYPE_POISON_CONSUMPTION,
443 RAS_EVENT_TYPE_COUNT,
444 };
445
446 struct ras_event_state {
447 u64 last_seqno;
448 atomic64_t count;
449 };
450
451 struct ras_event_manager {
452 atomic64_t seqno;
453 struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT];
454 };
455
456 struct ras_event_id {
457 enum ras_event_type type;
458 u64 event_id;
459 };
460
461 struct ras_query_context {
462 struct ras_event_id evid;
463 };
464
465 typedef int (*pasid_notify)(struct amdgpu_device *adev,
466 uint16_t pasid, void *data);
467
468 struct ras_poison_msg {
469 enum amdgpu_ras_block block;
470 uint16_t pasid;
471 uint32_t reset;
472 pasid_notify pasid_fn;
473 void *data;
474 };
475
476 struct ras_err_pages {
477 uint32_t count;
478 uint64_t *pfn;
479 };
480
481 struct ras_ecc_err {
482 uint64_t status;
483 uint64_t ipid;
484 uint64_t addr;
485 uint64_t pa_pfn;
486 /* save global channel index across all UMC instances */
487 uint32_t channel_idx;
488 struct ras_err_pages err_pages;
489 };
490
491 struct ras_ecc_log_info {
492 struct mutex lock;
493 struct radix_tree_root de_page_tree;
494 uint64_t de_queried_count;
495 uint64_t prev_de_queried_count;
496 };
497
498 struct amdgpu_ras {
499 /* ras infrastructure */
500 /* for ras itself. */
501 uint32_t features;
502 uint32_t schema;
503 struct list_head head;
504 /* sysfs */
505 struct device_attribute features_attr;
506 struct device_attribute version_attr;
507 struct device_attribute schema_attr;
508 struct device_attribute event_state_attr;
509 struct bin_attribute badpages_attr;
510 struct dentry *de_ras_eeprom_table;
511 /* block array */
512 struct ras_manager *objs;
513
514 /* gpu recovery */
515 struct work_struct recovery_work;
516 atomic_t in_recovery;
517 struct amdgpu_device *adev;
518 /* error handler data */
519 struct ras_err_handler_data *eh_data;
520 struct mutex recovery_lock;
521
522 uint32_t flags;
523 bool reboot;
524 struct amdgpu_ras_eeprom_control eeprom_control;
525
526 bool error_query_ready;
527
528 /* bad page count threshold */
529 uint32_t bad_page_cnt_threshold;
530
531 /* disable ras error count harvest in recovery */
532 bool disable_ras_err_cnt_harvest;
533
534 /* is poison mode supported */
535 bool poison_supported;
536
537 /* RAS count errors delayed work */
538 struct delayed_work ras_counte_delay_work;
539 atomic_t ras_ue_count;
540 atomic_t ras_ce_count;
541
542 /* record umc error info queried from smu */
543 struct umc_ecc_info umc_ecc;
544
545 /* Indicates smu whether need update bad channel info */
546 bool update_channel_flag;
547 /* Record status of smu mca debug mode */
548 bool is_aca_debug_mode;
549 bool is_rma;
550
551 /* Record special requirements of gpu reset caller */
552 uint32_t gpu_reset_flags;
553
554 struct task_struct *page_retirement_thread;
555 wait_queue_head_t page_retirement_wq;
556 struct mutex page_retirement_lock;
557 atomic_t page_retirement_req_cnt;
558 atomic_t poison_creation_count;
559 struct mutex page_rsv_lock;
560 DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, 128);
561 struct ras_ecc_log_info umc_ecc_log;
562 struct delayed_work page_retirement_dwork;
563
564 /* ras errors detected */
565 unsigned long ras_err_state;
566
567 /* RAS event manager */
568 struct ras_event_manager __event_mgr;
569 struct ras_event_manager *event_mgr;
570
571 uint64_t reserved_pages_in_bytes;
572 };
573
574 struct ras_fs_data {
575 char sysfs_name[48];
576 char debugfs_name[32];
577 };
578
579 struct ras_err_info {
580 struct amdgpu_smuio_mcm_config_info mcm_info;
581 u64 ce_count;
582 u64 ue_count;
583 u64 de_count;
584 };
585
586 struct ras_err_node {
587 struct list_head node;
588 struct ras_err_info err_info;
589 };
590
591 struct ras_err_data {
592 unsigned long ue_count;
593 unsigned long ce_count;
594 unsigned long de_count;
595 unsigned long err_addr_cnt;
596 struct eeprom_table_record *err_addr;
597 unsigned long err_addr_len;
598 u32 err_list_count;
599 struct list_head err_node_list;
600 };
601
602 #define for_each_ras_error(err_node, err_data) \
603 list_for_each_entry(err_node, &(err_data)->err_node_list, node)
604
605 struct ras_err_handler_data {
606 /* point to bad page records array */
607 struct eeprom_table_record *bps;
608 /* the count of entries */
609 int count;
610 /* the space can place new entries */
611 int space_left;
612 };
613
614 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
615 void *err_data,
616 struct amdgpu_iv_entry *entry);
617
618 struct ras_ih_data {
619 /* interrupt bottom half */
620 struct work_struct ih_work;
621 int inuse;
622 /* IP callback */
623 ras_ih_cb cb;
624 /* full of entries */
625 unsigned char *ring;
626 unsigned int ring_size;
627 unsigned int element_size;
628 unsigned int aligned_element_size;
629 unsigned int rptr;
630 unsigned int wptr;
631 };
632
633 struct ras_manager {
634 struct ras_common_if head;
635 /* reference count */
636 int use;
637 /* ras block link */
638 struct list_head node;
639 /* the device */
640 struct amdgpu_device *adev;
641 /* sysfs */
642 struct device_attribute sysfs_attr;
643 int attr_inuse;
644
645 /* fs node name */
646 struct ras_fs_data fs_data;
647
648 /* IH data */
649 struct ras_ih_data ih_data;
650
651 struct ras_err_data err_data;
652
653 struct aca_handle aca_handle;
654 };
655
656 struct ras_badpage {
657 unsigned int bp;
658 unsigned int size;
659 unsigned int flags;
660 };
661
662 /* interfaces for IP */
663 struct ras_fs_if {
664 struct ras_common_if head;
665 const char* sysfs_name;
666 char debugfs_name[32];
667 };
668
669 struct ras_query_if {
670 struct ras_common_if head;
671 unsigned long ue_count;
672 unsigned long ce_count;
673 unsigned long de_count;
674 };
675
676 struct ras_inject_if {
677 struct ras_common_if head;
678 uint64_t address;
679 uint64_t value;
680 uint32_t instance_mask;
681 };
682
683 struct ras_cure_if {
684 struct ras_common_if head;
685 uint64_t address;
686 };
687
688 struct ras_ih_if {
689 struct ras_common_if head;
690 ras_ih_cb cb;
691 };
692
693 struct ras_dispatch_if {
694 struct ras_common_if head;
695 struct amdgpu_iv_entry *entry;
696 };
697
698 struct ras_debug_if {
699 union {
700 struct ras_common_if head;
701 struct ras_inject_if inject;
702 };
703 int op;
704 };
705
706 struct amdgpu_ras_block_object {
707 struct ras_common_if ras_comm;
708
709 int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
710 enum amdgpu_ras_block block, uint32_t sub_block_index);
711 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
712 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
713 ras_ih_cb ras_cb;
714 const struct amdgpu_ras_block_hw_ops *hw_ops;
715 };
716
717 struct amdgpu_ras_block_hw_ops {
718 int (*ras_error_inject)(struct amdgpu_device *adev,
719 void *inject_if, uint32_t instance_mask);
720 void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
721 void (*query_ras_error_status)(struct amdgpu_device *adev);
722 void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
723 void (*reset_ras_error_count)(struct amdgpu_device *adev);
724 void (*reset_ras_error_status)(struct amdgpu_device *adev);
725 bool (*query_poison_status)(struct amdgpu_device *adev);
726 bool (*handle_poison_consumption)(struct amdgpu_device *adev);
727 };
728
729 /* work flow
730 * vbios
731 * 1: ras feature enable (enabled by default)
732 * psp
733 * 2: ras framework init (in ip_init)
734 * IP
735 * 3: IH add
736 * 4: debugfs/sysfs create
737 * 5: query/inject
738 * 6: debugfs/sysfs remove
739 * 7: IH remove
740 * 8: feature disable
741 */
742
743 int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev);
744 int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info);
745
746 void amdgpu_ras_resume(struct amdgpu_device *adev);
747 void amdgpu_ras_suspend(struct amdgpu_device *adev);
748
749 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
750 unsigned long *ce_count,
751 unsigned long *ue_count,
752 struct ras_query_if *query_info);
753
754 /* error handling functions */
755 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
756 struct eeprom_table_record *bps, int pages, bool from_rom);
757
758 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
759 unsigned long *new_cnt);
760
761 static inline enum ta_ras_block
amdgpu_ras_block_to_ta(enum amdgpu_ras_block block)762 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
763 switch (block) {
764 case AMDGPU_RAS_BLOCK__UMC:
765 return TA_RAS_BLOCK__UMC;
766 case AMDGPU_RAS_BLOCK__SDMA:
767 return TA_RAS_BLOCK__SDMA;
768 case AMDGPU_RAS_BLOCK__GFX:
769 return TA_RAS_BLOCK__GFX;
770 case AMDGPU_RAS_BLOCK__MMHUB:
771 return TA_RAS_BLOCK__MMHUB;
772 case AMDGPU_RAS_BLOCK__ATHUB:
773 return TA_RAS_BLOCK__ATHUB;
774 case AMDGPU_RAS_BLOCK__PCIE_BIF:
775 return TA_RAS_BLOCK__PCIE_BIF;
776 case AMDGPU_RAS_BLOCK__HDP:
777 return TA_RAS_BLOCK__HDP;
778 case AMDGPU_RAS_BLOCK__XGMI_WAFL:
779 return TA_RAS_BLOCK__XGMI_WAFL;
780 case AMDGPU_RAS_BLOCK__DF:
781 return TA_RAS_BLOCK__DF;
782 case AMDGPU_RAS_BLOCK__SMN:
783 return TA_RAS_BLOCK__SMN;
784 case AMDGPU_RAS_BLOCK__SEM:
785 return TA_RAS_BLOCK__SEM;
786 case AMDGPU_RAS_BLOCK__MP0:
787 return TA_RAS_BLOCK__MP0;
788 case AMDGPU_RAS_BLOCK__MP1:
789 return TA_RAS_BLOCK__MP1;
790 case AMDGPU_RAS_BLOCK__FUSE:
791 return TA_RAS_BLOCK__FUSE;
792 case AMDGPU_RAS_BLOCK__MCA:
793 return TA_RAS_BLOCK__MCA;
794 case AMDGPU_RAS_BLOCK__VCN:
795 return TA_RAS_BLOCK__VCN;
796 case AMDGPU_RAS_BLOCK__JPEG:
797 return TA_RAS_BLOCK__JPEG;
798 default:
799 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
800 return TA_RAS_BLOCK__UMC;
801 }
802 }
803
804 static inline enum ta_ras_error_type
amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error)805 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
806 switch (error) {
807 case AMDGPU_RAS_ERROR__NONE:
808 return TA_RAS_ERROR__NONE;
809 case AMDGPU_RAS_ERROR__PARITY:
810 return TA_RAS_ERROR__PARITY;
811 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
812 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
813 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
814 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
815 case AMDGPU_RAS_ERROR__POISON:
816 return TA_RAS_ERROR__POISON;
817 default:
818 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
819 return TA_RAS_ERROR__NONE;
820 }
821 }
822
823 /* called in ip_init and ip_fini */
824 int amdgpu_ras_init(struct amdgpu_device *adev);
825 int amdgpu_ras_late_init(struct amdgpu_device *adev);
826 int amdgpu_ras_fini(struct amdgpu_device *adev);
827 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
828
829 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
830 struct ras_common_if *ras_block);
831
832 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
833 struct ras_common_if *ras_block);
834
835 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
836 struct ras_common_if *head, bool enable);
837
838 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
839 struct ras_common_if *head, bool enable);
840
841 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
842 struct ras_common_if *head);
843
844 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
845 struct ras_common_if *head);
846
847 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
848
849 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
850 struct ras_query_if *info);
851
852 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
853 enum amdgpu_ras_block block);
854 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
855 enum amdgpu_ras_block block);
856
857 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
858 struct ras_inject_if *info);
859
860 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
861 struct ras_common_if *head);
862
863 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
864 struct ras_common_if *head);
865
866 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
867 struct ras_dispatch_if *info);
868
869 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
870 struct ras_common_if *head);
871
872 extern atomic_t amdgpu_ras_in_intr;
873
amdgpu_ras_intr_triggered(void)874 static inline bool amdgpu_ras_intr_triggered(void)
875 {
876 return !!atomic_read(&amdgpu_ras_in_intr);
877 }
878
amdgpu_ras_intr_cleared(void)879 static inline void amdgpu_ras_intr_cleared(void)
880 {
881 atomic_set(&amdgpu_ras_in_intr, 0);
882 }
883
884 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
885
886 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
887
888 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
889
890 void amdgpu_release_ras_context(struct amdgpu_device *adev);
891
892 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
893
894 const char *get_ras_block_str(struct ras_common_if *ras_block);
895
896 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
897
898 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
899
900 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
901
902 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
903
904 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
905
906 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable);
907 int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable);
908 bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev);
909 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
910 unsigned int *mode);
911
912 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
913 struct amdgpu_ras_block_object *ras_block_obj);
914 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev);
915 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name);
916 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
917 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
918 uint32_t instance,
919 uint32_t *memory_id);
920 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
921 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
922 uint32_t instance,
923 unsigned long *err_cnt);
924 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
925 const struct amdgpu_ras_err_status_reg_entry *reg_list,
926 uint32_t reg_list_size,
927 const struct amdgpu_ras_memory_id_entry *mem_list,
928 uint32_t mem_list_size,
929 uint32_t instance,
930 uint32_t err_type,
931 unsigned long *err_count);
932 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
933 const struct amdgpu_ras_err_status_reg_entry *reg_list,
934 uint32_t reg_list_size,
935 uint32_t instance);
936
937 int amdgpu_ras_error_data_init(struct ras_err_data *err_data);
938 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data);
939 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
940 struct amdgpu_smuio_mcm_config_info *mcm_info,
941 u64 count);
942 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
943 struct amdgpu_smuio_mcm_config_info *mcm_info,
944 u64 count);
945 int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,
946 struct amdgpu_smuio_mcm_config_info *mcm_info,
947 u64 count);
948 void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances);
949 int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
950 const struct aca_info *aca_info, void *data);
951 int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk);
952
953 ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,
954 struct aca_handle *handle, char *buf, void *data);
955
956 void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status);
957 bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev);
958 void amdgpu_ras_set_err_poison(struct amdgpu_device *adev,
959 enum amdgpu_ras_block block);
960 void amdgpu_ras_clear_err_state(struct amdgpu_device *adev);
961 bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block);
962
963 u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type);
964 int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type,
965 const void *caller);
966
967 int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn);
968
969 int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,
970 enum amdgpu_ras_block block, uint16_t pasid,
971 pasid_notify pasid_fn, void *data, uint32_t reset);
972
973 bool amdgpu_ras_in_recovery(struct amdgpu_device *adev);
974
975 __printf(3, 4)
976 void amdgpu_ras_event_log_print(struct amdgpu_device *adev, u64 event_id,
977 const char *fmt, ...);
978
979 bool amdgpu_ras_is_rma(struct amdgpu_device *adev);
980 #endif
981