1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 PP_ISPICLK, 112 PP_ISPXCLK, 113 OD_SCLK, 114 OD_MCLK, 115 OD_VDDC_CURVE, 116 OD_RANGE, 117 OD_VDDGFX_OFFSET, 118 OD_CCLK, 119 OD_FAN_CURVE, 120 OD_ACOUSTIC_LIMIT, 121 OD_ACOUSTIC_TARGET, 122 OD_FAN_TARGET_TEMPERATURE, 123 OD_FAN_MINIMUM_PWM, 124 OD_FAN_ZERO_RPM_ENABLE, 125 OD_FAN_ZERO_RPM_STOP_TEMP, 126 }; 127 128 enum amd_pp_sensors { 129 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 130 AMDGPU_PP_SENSOR_CPU_CLK, 131 AMDGPU_PP_SENSOR_VDDNB, 132 AMDGPU_PP_SENSOR_VDDGFX, 133 AMDGPU_PP_SENSOR_VDDBOARD, 134 AMDGPU_PP_SENSOR_UVD_VCLK, 135 AMDGPU_PP_SENSOR_UVD_DCLK, 136 AMDGPU_PP_SENSOR_VCE_ECCLK, 137 AMDGPU_PP_SENSOR_GPU_LOAD, 138 AMDGPU_PP_SENSOR_MEM_LOAD, 139 AMDGPU_PP_SENSOR_GFX_MCLK, 140 AMDGPU_PP_SENSOR_GPU_TEMP, 141 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 142 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 143 AMDGPU_PP_SENSOR_MEM_TEMP, 144 AMDGPU_PP_SENSOR_VCE_POWER, 145 AMDGPU_PP_SENSOR_UVD_POWER, 146 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 147 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 148 AMDGPU_PP_SENSOR_SS_APU_SHARE, 149 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 150 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 151 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 152 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 153 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 154 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 155 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 156 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 157 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 158 AMDGPU_PP_SENSOR_VCN_LOAD, 159 }; 160 161 enum amd_pp_task { 162 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 163 AMD_PP_TASK_ENABLE_USER_STATE, 164 AMD_PP_TASK_READJUST_POWER_STATE, 165 AMD_PP_TASK_COMPLETE_INIT, 166 AMD_PP_TASK_MAX 167 }; 168 169 enum PP_SMC_POWER_PROFILE { 170 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 171 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 172 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 173 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 174 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 175 PP_SMC_POWER_PROFILE_VR = 0x4, 176 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 177 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 178 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 179 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 180 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 181 PP_SMC_POWER_PROFILE_COUNT, 182 }; 183 184 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 185 186 187 188 enum { 189 PP_GROUP_UNKNOWN = 0, 190 PP_GROUP_GFX = 1, 191 PP_GROUP_SYS, 192 PP_GROUP_MAX 193 }; 194 195 enum PP_OD_DPM_TABLE_COMMAND { 196 PP_OD_EDIT_SCLK_VDDC_TABLE, 197 PP_OD_EDIT_MCLK_VDDC_TABLE, 198 PP_OD_EDIT_CCLK_VDDC_TABLE, 199 PP_OD_EDIT_VDDC_CURVE, 200 PP_OD_RESTORE_DEFAULT_TABLE, 201 PP_OD_COMMIT_DPM_TABLE, 202 PP_OD_EDIT_VDDGFX_OFFSET, 203 PP_OD_EDIT_FAN_CURVE, 204 PP_OD_EDIT_ACOUSTIC_LIMIT, 205 PP_OD_EDIT_ACOUSTIC_TARGET, 206 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 207 PP_OD_EDIT_FAN_MINIMUM_PWM, 208 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 209 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 210 }; 211 212 struct pp_states_info { 213 uint32_t nums; 214 uint32_t states[16]; 215 }; 216 217 enum PP_HWMON_TEMP { 218 PP_TEMP_EDGE = 0, 219 PP_TEMP_JUNCTION, 220 PP_TEMP_MEM, 221 PP_TEMP_MAX 222 }; 223 224 enum pp_mp1_state { 225 PP_MP1_STATE_NONE, 226 PP_MP1_STATE_SHUTDOWN, 227 PP_MP1_STATE_UNLOAD, 228 PP_MP1_STATE_RESET, 229 PP_MP1_STATE_FLR, 230 }; 231 232 enum pp_df_cstate { 233 DF_CSTATE_DISALLOW = 0, 234 DF_CSTATE_ALLOW, 235 }; 236 237 /** 238 * DOC: amdgpu_pp_power 239 * 240 * APU power is managed to system-level requirements through the PPT 241 * (package power tracking) feature. PPT is intended to limit power to the 242 * requirements of the power source and could be dynamically updated to 243 * maximize APU performance within the system power budget. 244 * 245 * Two types of power measurement can be requested, where supported, with 246 * :c:type:`enum pp_power_type <pp_power_type>`. 247 */ 248 249 /** 250 * enum pp_power_limit_level - Used to query the power limits 251 * 252 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 253 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 254 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 255 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 256 */ 257 enum pp_power_limit_level { 258 PP_PWR_LIMIT_MIN = -1, 259 PP_PWR_LIMIT_CURRENT, 260 PP_PWR_LIMIT_DEFAULT, 261 PP_PWR_LIMIT_MAX, 262 }; 263 264 /** 265 * enum pp_power_type - Used to specify the type of the requested power 266 * 267 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 268 * moving average of APU power (default ~5000 ms). 269 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 270 * where supported. 271 */ 272 enum pp_power_type { 273 PP_PWR_TYPE_SUSTAINED, 274 PP_PWR_TYPE_FAST, 275 }; 276 277 enum pp_xgmi_plpd_mode { 278 XGMI_PLPD_NONE = -1, 279 XGMI_PLPD_DISALLOW, 280 XGMI_PLPD_DEFAULT, 281 XGMI_PLPD_OPTIMIZED, 282 XGMI_PLPD_COUNT, 283 }; 284 285 enum pp_pm_policy { 286 PP_PM_POLICY_NONE = -1, 287 PP_PM_POLICY_SOC_PSTATE = 0, 288 PP_PM_POLICY_XGMI_PLPD, 289 PP_PM_POLICY_NUM, 290 }; 291 292 enum pp_policy_soc_pstate { 293 SOC_PSTATE_DEFAULT = 0, 294 SOC_PSTATE_0, 295 SOC_PSTATE_1, 296 SOC_PSTATE_2, 297 SOC_PSTAT_COUNT, 298 }; 299 300 #define PP_POLICY_MAX_LEVELS 5 301 302 #define PP_GROUP_MASK 0xF0000000 303 #define PP_GROUP_SHIFT 28 304 305 #define PP_BLOCK_MASK 0x0FFFFF00 306 #define PP_BLOCK_SHIFT 8 307 308 #define PP_BLOCK_GFX_CG 0x01 309 #define PP_BLOCK_GFX_MG 0x02 310 #define PP_BLOCK_GFX_3D 0x04 311 #define PP_BLOCK_GFX_RLC 0x08 312 #define PP_BLOCK_GFX_CP 0x10 313 #define PP_BLOCK_SYS_BIF 0x01 314 #define PP_BLOCK_SYS_MC 0x02 315 #define PP_BLOCK_SYS_ROM 0x04 316 #define PP_BLOCK_SYS_DRM 0x08 317 #define PP_BLOCK_SYS_HDP 0x10 318 #define PP_BLOCK_SYS_SDMA 0x20 319 320 #define PP_STATE_MASK 0x0000000F 321 #define PP_STATE_SHIFT 0 322 #define PP_STATE_SUPPORT_MASK 0x000000F0 323 #define PP_STATE_SUPPORT_SHIFT 0 324 325 #define PP_STATE_CG 0x01 326 #define PP_STATE_LS 0x02 327 #define PP_STATE_DS 0x04 328 #define PP_STATE_SD 0x08 329 #define PP_STATE_SUPPORT_CG 0x10 330 #define PP_STATE_SUPPORT_LS 0x20 331 #define PP_STATE_SUPPORT_DS 0x40 332 #define PP_STATE_SUPPORT_SD 0x80 333 334 #define PP_CG_MSG_ID(group, block, support, state) \ 335 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 336 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 337 338 #define XGMI_MODE_PSTATE_D3 0 339 #define XGMI_MODE_PSTATE_D0 1 340 341 #define NUM_HBM_INSTANCES 4 342 #define NUM_XGMI_LINKS 8 343 #define MAX_GFX_CLKS 8 344 #define MAX_CLKS 4 345 #define NUM_VCN 4 346 #define NUM_JPEG_ENG 32 347 #define NUM_JPEG_ENG_V1 40 348 #define MAX_XCC 8 349 #define NUM_XCP 8 350 struct seq_file; 351 enum amd_pp_clock_type; 352 struct amd_pp_simple_clock_info; 353 struct amd_pp_display_configuration; 354 struct amd_pp_clock_info; 355 struct pp_display_clock_request; 356 struct pp_clock_levels_with_voltage; 357 struct pp_clock_levels_with_latency; 358 struct amd_pp_clocks; 359 struct pp_smu_wm_range_sets; 360 struct pp_smu_nv_clock_table; 361 struct dpm_clocks; 362 363 struct amdgpu_xcp_metrics { 364 /* Utilization Instantaneous (%) */ 365 uint32_t gfx_busy_inst[MAX_XCC]; 366 uint16_t jpeg_busy[NUM_JPEG_ENG]; 367 uint16_t vcn_busy[NUM_VCN]; 368 /* Utilization Accumulated (%) */ 369 uint64_t gfx_busy_acc[MAX_XCC]; 370 }; 371 372 struct amdgpu_xcp_metrics_v1_1 { 373 /* Utilization Instantaneous (%) */ 374 uint32_t gfx_busy_inst[MAX_XCC]; 375 uint16_t jpeg_busy[NUM_JPEG_ENG]; 376 uint16_t vcn_busy[NUM_VCN]; 377 /* Utilization Accumulated (%) */ 378 uint64_t gfx_busy_acc[MAX_XCC]; 379 /* Total App Clock Counter Accumulated */ 380 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 381 }; 382 383 struct amdgpu_xcp_metrics_v1_2 { 384 /* Utilization Instantaneous (%) */ 385 uint32_t gfx_busy_inst[MAX_XCC]; 386 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 387 uint16_t vcn_busy[NUM_VCN]; 388 /* Utilization Accumulated (%) */ 389 uint64_t gfx_busy_acc[MAX_XCC]; 390 /* Total App Clock Counter Accumulated */ 391 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 392 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 393 uint64_t gfx_low_utilization_acc[MAX_XCC]; 394 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 395 }; 396 397 struct amd_pm_funcs { 398 /* export for dpm on ci and si */ 399 int (*pre_set_power_state)(void *handle); 400 int (*set_power_state)(void *handle); 401 void (*post_set_power_state)(void *handle); 402 void (*display_configuration_changed)(void *handle); 403 void (*print_power_state)(void *handle, void *ps); 404 bool (*vblank_too_short)(void *handle); 405 void (*enable_bapm)(void *handle, bool enable); 406 int (*check_state_equal)(void *handle, 407 void *cps, 408 void *rps, 409 bool *equal); 410 /* export for sysfs */ 411 int (*set_fan_control_mode)(void *handle, u32 mode); 412 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 413 int (*set_fan_speed_pwm)(void *handle, u32 speed); 414 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 415 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 416 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 417 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 418 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 419 int (*get_sclk_od)(void *handle); 420 int (*set_sclk_od)(void *handle, uint32_t value); 421 int (*get_mclk_od)(void *handle); 422 int (*set_mclk_od)(void *handle, uint32_t value); 423 int (*read_sensor)(void *handle, int idx, void *value, int *size); 424 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 425 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 426 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 427 enum amd_pm_state_type (*get_current_power_state)(void *handle); 428 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 429 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 430 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 431 int (*get_pp_table)(void *handle, char **table); 432 int (*set_pp_table)(void *handle, const char *buf, size_t size); 433 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 434 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 435 int (*pause_power_profile)(void *handle, bool pause); 436 /* export to amdgpu */ 437 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 438 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 439 enum amd_pm_state_type *user_state); 440 int (*load_firmware)(void *handle); 441 int (*wait_for_fw_loading_complete)(void *handle); 442 int (*set_powergating_by_smu)(void *handle, 443 uint32_t block_type, 444 bool gate, 445 int inst); 446 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 447 int (*set_power_limit)(void *handle, uint32_t n); 448 int (*get_power_limit)(void *handle, uint32_t *limit, 449 enum pp_power_limit_level pp_limit_level, 450 enum pp_power_type power_type); 451 int (*get_power_profile_mode)(void *handle, char *buf); 452 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 453 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 454 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 455 long *input, uint32_t size); 456 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 457 int (*smu_i2c_bus_access)(void *handle, bool acquire); 458 int (*gfx_state_change_set)(void *handle, uint32_t state); 459 /* export to DC */ 460 u32 (*get_sclk)(void *handle, bool low); 461 u32 (*get_mclk)(void *handle, bool low); 462 int (*display_configuration_change)(void *handle, 463 const struct amd_pp_display_configuration *input); 464 int (*get_display_power_level)(void *handle, 465 struct amd_pp_simple_clock_info *output); 466 int (*get_current_clocks)(void *handle, 467 struct amd_pp_clock_info *clocks); 468 int (*get_clock_by_type)(void *handle, 469 enum amd_pp_clock_type type, 470 struct amd_pp_clocks *clocks); 471 int (*get_clock_by_type_with_latency)(void *handle, 472 enum amd_pp_clock_type type, 473 struct pp_clock_levels_with_latency *clocks); 474 int (*get_clock_by_type_with_voltage)(void *handle, 475 enum amd_pp_clock_type type, 476 struct pp_clock_levels_with_voltage *clocks); 477 int (*set_watermarks_for_clocks_ranges)(void *handle, 478 void *clock_ranges); 479 int (*display_clock_voltage_request)(void *handle, 480 struct pp_display_clock_request *clock); 481 int (*get_display_mode_validation_clocks)(void *handle, 482 struct amd_pp_simple_clock_info *clocks); 483 int (*notify_smu_enable_pwe)(void *handle); 484 int (*enable_mgpu_fan_boost)(void *handle); 485 int (*set_active_display_count)(void *handle, uint32_t count); 486 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 487 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 488 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 489 int (*get_asic_baco_capability)(void *handle); 490 int (*get_asic_baco_state)(void *handle, int *state); 491 int (*set_asic_baco_state)(void *handle, int state); 492 int (*get_ppfeature_status)(void *handle, char *buf); 493 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 494 int (*asic_reset_mode_2)(void *handle); 495 int (*asic_reset_enable_gfx_features)(void *handle); 496 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 497 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 498 ssize_t (*get_gpu_metrics)(void *handle, void **table); 499 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 500 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 501 int (*set_watermarks_for_clock_ranges)(void *handle, 502 struct pp_smu_wm_range_sets *ranges); 503 int (*display_disable_memory_clock_switch)(void *handle, 504 bool disable_memory_clock_switch); 505 int (*get_max_sustainable_clocks_by_dc)(void *handle, 506 struct pp_smu_nv_clock_table *max_clocks); 507 int (*get_uclk_dpm_states)(void *handle, 508 unsigned int *clock_values_in_khz, 509 unsigned int *num_states); 510 int (*get_dpm_clock_table)(void *handle, 511 struct dpm_clocks *clock_table); 512 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 513 void (*pm_compute_clocks)(void *handle); 514 int (*notify_rlc_state)(void *handle, bool en); 515 }; 516 517 struct metrics_table_header { 518 uint16_t structure_size; 519 uint8_t format_revision; 520 uint8_t content_revision; 521 }; 522 523 /* 524 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 525 * Use gpu_metrics_v1_1 or later instead. 526 */ 527 struct gpu_metrics_v1_0 { 528 struct metrics_table_header common_header; 529 530 /* Driver attached timestamp (in ns) */ 531 uint64_t system_clock_counter; 532 533 /* Temperature */ 534 uint16_t temperature_edge; 535 uint16_t temperature_hotspot; 536 uint16_t temperature_mem; 537 uint16_t temperature_vrgfx; 538 uint16_t temperature_vrsoc; 539 uint16_t temperature_vrmem; 540 541 /* Utilization */ 542 uint16_t average_gfx_activity; 543 uint16_t average_umc_activity; // memory controller 544 uint16_t average_mm_activity; // UVD or VCN 545 546 /* Power/Energy */ 547 uint16_t average_socket_power; 548 uint32_t energy_accumulator; 549 550 /* Average clocks */ 551 uint16_t average_gfxclk_frequency; 552 uint16_t average_socclk_frequency; 553 uint16_t average_uclk_frequency; 554 uint16_t average_vclk0_frequency; 555 uint16_t average_dclk0_frequency; 556 uint16_t average_vclk1_frequency; 557 uint16_t average_dclk1_frequency; 558 559 /* Current clocks */ 560 uint16_t current_gfxclk; 561 uint16_t current_socclk; 562 uint16_t current_uclk; 563 uint16_t current_vclk0; 564 uint16_t current_dclk0; 565 uint16_t current_vclk1; 566 uint16_t current_dclk1; 567 568 /* Throttle status */ 569 uint32_t throttle_status; 570 571 /* Fans */ 572 uint16_t current_fan_speed; 573 574 /* Link width/speed */ 575 uint8_t pcie_link_width; 576 uint8_t pcie_link_speed; // in 0.1 GT/s 577 }; 578 579 struct gpu_metrics_v1_1 { 580 struct metrics_table_header common_header; 581 582 /* Temperature */ 583 uint16_t temperature_edge; 584 uint16_t temperature_hotspot; 585 uint16_t temperature_mem; 586 uint16_t temperature_vrgfx; 587 uint16_t temperature_vrsoc; 588 uint16_t temperature_vrmem; 589 590 /* Utilization */ 591 uint16_t average_gfx_activity; 592 uint16_t average_umc_activity; // memory controller 593 uint16_t average_mm_activity; // UVD or VCN 594 595 /* Power/Energy */ 596 uint16_t average_socket_power; 597 uint64_t energy_accumulator; 598 599 /* Driver attached timestamp (in ns) */ 600 uint64_t system_clock_counter; 601 602 /* Average clocks */ 603 uint16_t average_gfxclk_frequency; 604 uint16_t average_socclk_frequency; 605 uint16_t average_uclk_frequency; 606 uint16_t average_vclk0_frequency; 607 uint16_t average_dclk0_frequency; 608 uint16_t average_vclk1_frequency; 609 uint16_t average_dclk1_frequency; 610 611 /* Current clocks */ 612 uint16_t current_gfxclk; 613 uint16_t current_socclk; 614 uint16_t current_uclk; 615 uint16_t current_vclk0; 616 uint16_t current_dclk0; 617 uint16_t current_vclk1; 618 uint16_t current_dclk1; 619 620 /* Throttle status */ 621 uint32_t throttle_status; 622 623 /* Fans */ 624 uint16_t current_fan_speed; 625 626 /* Link width/speed */ 627 uint16_t pcie_link_width; 628 uint16_t pcie_link_speed; // in 0.1 GT/s 629 630 uint16_t padding; 631 632 uint32_t gfx_activity_acc; 633 uint32_t mem_activity_acc; 634 635 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 636 }; 637 638 struct gpu_metrics_v1_2 { 639 struct metrics_table_header common_header; 640 641 /* Temperature */ 642 uint16_t temperature_edge; 643 uint16_t temperature_hotspot; 644 uint16_t temperature_mem; 645 uint16_t temperature_vrgfx; 646 uint16_t temperature_vrsoc; 647 uint16_t temperature_vrmem; 648 649 /* Utilization */ 650 uint16_t average_gfx_activity; 651 uint16_t average_umc_activity; // memory controller 652 uint16_t average_mm_activity; // UVD or VCN 653 654 /* Power/Energy */ 655 uint16_t average_socket_power; 656 uint64_t energy_accumulator; 657 658 /* Driver attached timestamp (in ns) */ 659 uint64_t system_clock_counter; 660 661 /* Average clocks */ 662 uint16_t average_gfxclk_frequency; 663 uint16_t average_socclk_frequency; 664 uint16_t average_uclk_frequency; 665 uint16_t average_vclk0_frequency; 666 uint16_t average_dclk0_frequency; 667 uint16_t average_vclk1_frequency; 668 uint16_t average_dclk1_frequency; 669 670 /* Current clocks */ 671 uint16_t current_gfxclk; 672 uint16_t current_socclk; 673 uint16_t current_uclk; 674 uint16_t current_vclk0; 675 uint16_t current_dclk0; 676 uint16_t current_vclk1; 677 uint16_t current_dclk1; 678 679 /* Throttle status (ASIC dependent) */ 680 uint32_t throttle_status; 681 682 /* Fans */ 683 uint16_t current_fan_speed; 684 685 /* Link width/speed */ 686 uint16_t pcie_link_width; 687 uint16_t pcie_link_speed; // in 0.1 GT/s 688 689 uint16_t padding; 690 691 uint32_t gfx_activity_acc; 692 uint32_t mem_activity_acc; 693 694 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 695 696 /* PMFW attached timestamp (10ns resolution) */ 697 uint64_t firmware_timestamp; 698 }; 699 700 struct gpu_metrics_v1_3 { 701 struct metrics_table_header common_header; 702 703 /* Temperature */ 704 uint16_t temperature_edge; 705 uint16_t temperature_hotspot; 706 uint16_t temperature_mem; 707 uint16_t temperature_vrgfx; 708 uint16_t temperature_vrsoc; 709 uint16_t temperature_vrmem; 710 711 /* Utilization */ 712 uint16_t average_gfx_activity; 713 uint16_t average_umc_activity; // memory controller 714 uint16_t average_mm_activity; // UVD or VCN 715 716 /* Power/Energy */ 717 uint16_t average_socket_power; 718 uint64_t energy_accumulator; 719 720 /* Driver attached timestamp (in ns) */ 721 uint64_t system_clock_counter; 722 723 /* Average clocks */ 724 uint16_t average_gfxclk_frequency; 725 uint16_t average_socclk_frequency; 726 uint16_t average_uclk_frequency; 727 uint16_t average_vclk0_frequency; 728 uint16_t average_dclk0_frequency; 729 uint16_t average_vclk1_frequency; 730 uint16_t average_dclk1_frequency; 731 732 /* Current clocks */ 733 uint16_t current_gfxclk; 734 uint16_t current_socclk; 735 uint16_t current_uclk; 736 uint16_t current_vclk0; 737 uint16_t current_dclk0; 738 uint16_t current_vclk1; 739 uint16_t current_dclk1; 740 741 /* Throttle status */ 742 uint32_t throttle_status; 743 744 /* Fans */ 745 uint16_t current_fan_speed; 746 747 /* Link width/speed */ 748 uint16_t pcie_link_width; 749 uint16_t pcie_link_speed; // in 0.1 GT/s 750 751 uint16_t padding; 752 753 uint32_t gfx_activity_acc; 754 uint32_t mem_activity_acc; 755 756 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 757 758 /* PMFW attached timestamp (10ns resolution) */ 759 uint64_t firmware_timestamp; 760 761 /* Voltage (mV) */ 762 uint16_t voltage_soc; 763 uint16_t voltage_gfx; 764 uint16_t voltage_mem; 765 766 uint16_t padding1; 767 768 /* Throttle status (ASIC independent) */ 769 uint64_t indep_throttle_status; 770 }; 771 772 struct gpu_metrics_v1_4 { 773 struct metrics_table_header common_header; 774 775 /* Temperature (Celsius) */ 776 uint16_t temperature_hotspot; 777 uint16_t temperature_mem; 778 uint16_t temperature_vrsoc; 779 780 /* Power (Watts) */ 781 uint16_t curr_socket_power; 782 783 /* Utilization (%) */ 784 uint16_t average_gfx_activity; 785 uint16_t average_umc_activity; // memory controller 786 uint16_t vcn_activity[NUM_VCN]; 787 788 /* Energy (15.259uJ (2^-16) units) */ 789 uint64_t energy_accumulator; 790 791 /* Driver attached timestamp (in ns) */ 792 uint64_t system_clock_counter; 793 794 /* Throttle status */ 795 uint32_t throttle_status; 796 797 /* Clock Lock Status. Each bit corresponds to clock instance */ 798 uint32_t gfxclk_lock_status; 799 800 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 801 uint16_t pcie_link_width; 802 uint16_t pcie_link_speed; 803 804 /* XGMI bus width and bitrate (in Gbps) */ 805 uint16_t xgmi_link_width; 806 uint16_t xgmi_link_speed; 807 808 /* Utilization Accumulated (%) */ 809 uint32_t gfx_activity_acc; 810 uint32_t mem_activity_acc; 811 812 /*PCIE accumulated bandwidth (GB/sec) */ 813 uint64_t pcie_bandwidth_acc; 814 815 /*PCIE instantaneous bandwidth (GB/sec) */ 816 uint64_t pcie_bandwidth_inst; 817 818 /* PCIE L0 to recovery state transition accumulated count */ 819 uint64_t pcie_l0_to_recov_count_acc; 820 821 /* PCIE replay accumulated count */ 822 uint64_t pcie_replay_count_acc; 823 824 /* PCIE replay rollover accumulated count */ 825 uint64_t pcie_replay_rover_count_acc; 826 827 /* XGMI accumulated data transfer size(KiloBytes) */ 828 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 829 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 830 831 /* PMFW attached timestamp (10ns resolution) */ 832 uint64_t firmware_timestamp; 833 834 /* Current clocks (Mhz) */ 835 uint16_t current_gfxclk[MAX_GFX_CLKS]; 836 uint16_t current_socclk[MAX_CLKS]; 837 uint16_t current_vclk0[MAX_CLKS]; 838 uint16_t current_dclk0[MAX_CLKS]; 839 uint16_t current_uclk; 840 841 uint16_t padding; 842 }; 843 844 struct gpu_metrics_v1_5 { 845 struct metrics_table_header common_header; 846 847 /* Temperature (Celsius) */ 848 uint16_t temperature_hotspot; 849 uint16_t temperature_mem; 850 uint16_t temperature_vrsoc; 851 852 /* Power (Watts) */ 853 uint16_t curr_socket_power; 854 855 /* Utilization (%) */ 856 uint16_t average_gfx_activity; 857 uint16_t average_umc_activity; // memory controller 858 uint16_t vcn_activity[NUM_VCN]; 859 uint16_t jpeg_activity[NUM_JPEG_ENG]; 860 861 /* Energy (15.259uJ (2^-16) units) */ 862 uint64_t energy_accumulator; 863 864 /* Driver attached timestamp (in ns) */ 865 uint64_t system_clock_counter; 866 867 /* Throttle status */ 868 uint32_t throttle_status; 869 870 /* Clock Lock Status. Each bit corresponds to clock instance */ 871 uint32_t gfxclk_lock_status; 872 873 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 874 uint16_t pcie_link_width; 875 uint16_t pcie_link_speed; 876 877 /* XGMI bus width and bitrate (in Gbps) */ 878 uint16_t xgmi_link_width; 879 uint16_t xgmi_link_speed; 880 881 /* Utilization Accumulated (%) */ 882 uint32_t gfx_activity_acc; 883 uint32_t mem_activity_acc; 884 885 /*PCIE accumulated bandwidth (GB/sec) */ 886 uint64_t pcie_bandwidth_acc; 887 888 /*PCIE instantaneous bandwidth (GB/sec) */ 889 uint64_t pcie_bandwidth_inst; 890 891 /* PCIE L0 to recovery state transition accumulated count */ 892 uint64_t pcie_l0_to_recov_count_acc; 893 894 /* PCIE replay accumulated count */ 895 uint64_t pcie_replay_count_acc; 896 897 /* PCIE replay rollover accumulated count */ 898 uint64_t pcie_replay_rover_count_acc; 899 900 /* PCIE NAK sent accumulated count */ 901 uint32_t pcie_nak_sent_count_acc; 902 903 /* PCIE NAK received accumulated count */ 904 uint32_t pcie_nak_rcvd_count_acc; 905 906 /* XGMI accumulated data transfer size(KiloBytes) */ 907 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 908 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 909 910 /* PMFW attached timestamp (10ns resolution) */ 911 uint64_t firmware_timestamp; 912 913 /* Current clocks (Mhz) */ 914 uint16_t current_gfxclk[MAX_GFX_CLKS]; 915 uint16_t current_socclk[MAX_CLKS]; 916 uint16_t current_vclk0[MAX_CLKS]; 917 uint16_t current_dclk0[MAX_CLKS]; 918 uint16_t current_uclk; 919 920 uint16_t padding; 921 }; 922 923 struct gpu_metrics_v1_6 { 924 struct metrics_table_header common_header; 925 926 /* Temperature (Celsius) */ 927 uint16_t temperature_hotspot; 928 uint16_t temperature_mem; 929 uint16_t temperature_vrsoc; 930 931 /* Power (Watts) */ 932 uint16_t curr_socket_power; 933 934 /* Utilization (%) */ 935 uint16_t average_gfx_activity; 936 uint16_t average_umc_activity; // memory controller 937 938 /* Energy (15.259uJ (2^-16) units) */ 939 uint64_t energy_accumulator; 940 941 /* Driver attached timestamp (in ns) */ 942 uint64_t system_clock_counter; 943 944 /* Accumulation cycle counter */ 945 uint32_t accumulation_counter; 946 947 /* Accumulated throttler residencies */ 948 uint32_t prochot_residency_acc; 949 uint32_t ppt_residency_acc; 950 uint32_t socket_thm_residency_acc; 951 uint32_t vr_thm_residency_acc; 952 uint32_t hbm_thm_residency_acc; 953 954 /* Clock Lock Status. Each bit corresponds to clock instance */ 955 uint32_t gfxclk_lock_status; 956 957 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 958 uint16_t pcie_link_width; 959 uint16_t pcie_link_speed; 960 961 /* XGMI bus width and bitrate (in Gbps) */ 962 uint16_t xgmi_link_width; 963 uint16_t xgmi_link_speed; 964 965 /* Utilization Accumulated (%) */ 966 uint32_t gfx_activity_acc; 967 uint32_t mem_activity_acc; 968 969 /*PCIE accumulated bandwidth (GB/sec) */ 970 uint64_t pcie_bandwidth_acc; 971 972 /*PCIE instantaneous bandwidth (GB/sec) */ 973 uint64_t pcie_bandwidth_inst; 974 975 /* PCIE L0 to recovery state transition accumulated count */ 976 uint64_t pcie_l0_to_recov_count_acc; 977 978 /* PCIE replay accumulated count */ 979 uint64_t pcie_replay_count_acc; 980 981 /* PCIE replay rollover accumulated count */ 982 uint64_t pcie_replay_rover_count_acc; 983 984 /* PCIE NAK sent accumulated count */ 985 uint32_t pcie_nak_sent_count_acc; 986 987 /* PCIE NAK received accumulated count */ 988 uint32_t pcie_nak_rcvd_count_acc; 989 990 /* XGMI accumulated data transfer size(KiloBytes) */ 991 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 992 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 993 994 /* PMFW attached timestamp (10ns resolution) */ 995 uint64_t firmware_timestamp; 996 997 /* Current clocks (Mhz) */ 998 uint16_t current_gfxclk[MAX_GFX_CLKS]; 999 uint16_t current_socclk[MAX_CLKS]; 1000 uint16_t current_vclk0[MAX_CLKS]; 1001 uint16_t current_dclk0[MAX_CLKS]; 1002 uint16_t current_uclk; 1003 1004 /* Number of current partition */ 1005 uint16_t num_partition; 1006 1007 /* XCP metrics stats */ 1008 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1009 1010 /* PCIE other end recovery counter */ 1011 uint32_t pcie_lc_perf_other_end_recovery; 1012 }; 1013 1014 struct gpu_metrics_v1_7 { 1015 struct metrics_table_header common_header; 1016 1017 /* Temperature (Celsius) */ 1018 uint16_t temperature_hotspot; 1019 uint16_t temperature_mem; 1020 uint16_t temperature_vrsoc; 1021 1022 /* Power (Watts) */ 1023 uint16_t curr_socket_power; 1024 1025 /* Utilization (%) */ 1026 uint16_t average_gfx_activity; 1027 uint16_t average_umc_activity; // memory controller 1028 1029 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1030 uint64_t mem_max_bandwidth; 1031 1032 /* Energy (15.259uJ (2^-16) units) */ 1033 uint64_t energy_accumulator; 1034 1035 /* Driver attached timestamp (in ns) */ 1036 uint64_t system_clock_counter; 1037 1038 /* Accumulation cycle counter */ 1039 uint32_t accumulation_counter; 1040 1041 /* Accumulated throttler residencies */ 1042 uint32_t prochot_residency_acc; 1043 uint32_t ppt_residency_acc; 1044 uint32_t socket_thm_residency_acc; 1045 uint32_t vr_thm_residency_acc; 1046 uint32_t hbm_thm_residency_acc; 1047 1048 /* Clock Lock Status. Each bit corresponds to clock instance */ 1049 uint32_t gfxclk_lock_status; 1050 1051 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1052 uint16_t pcie_link_width; 1053 uint16_t pcie_link_speed; 1054 1055 /* XGMI bus width and bitrate (in Gbps) */ 1056 uint16_t xgmi_link_width; 1057 uint16_t xgmi_link_speed; 1058 1059 /* Utilization Accumulated (%) */ 1060 uint32_t gfx_activity_acc; 1061 uint32_t mem_activity_acc; 1062 1063 /*PCIE accumulated bandwidth (GB/sec) */ 1064 uint64_t pcie_bandwidth_acc; 1065 1066 /*PCIE instantaneous bandwidth (GB/sec) */ 1067 uint64_t pcie_bandwidth_inst; 1068 1069 /* PCIE L0 to recovery state transition accumulated count */ 1070 uint64_t pcie_l0_to_recov_count_acc; 1071 1072 /* PCIE replay accumulated count */ 1073 uint64_t pcie_replay_count_acc; 1074 1075 /* PCIE replay rollover accumulated count */ 1076 uint64_t pcie_replay_rover_count_acc; 1077 1078 /* PCIE NAK sent accumulated count */ 1079 uint32_t pcie_nak_sent_count_acc; 1080 1081 /* PCIE NAK received accumulated count */ 1082 uint32_t pcie_nak_rcvd_count_acc; 1083 1084 /* XGMI accumulated data transfer size(KiloBytes) */ 1085 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1086 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1087 1088 /* XGMI link status(active/inactive) */ 1089 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1090 1091 uint16_t padding; 1092 1093 /* PMFW attached timestamp (10ns resolution) */ 1094 uint64_t firmware_timestamp; 1095 1096 /* Current clocks (Mhz) */ 1097 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1098 uint16_t current_socclk[MAX_CLKS]; 1099 uint16_t current_vclk0[MAX_CLKS]; 1100 uint16_t current_dclk0[MAX_CLKS]; 1101 uint16_t current_uclk; 1102 1103 /* Number of current partition */ 1104 uint16_t num_partition; 1105 1106 /* XCP metrics stats */ 1107 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1108 1109 /* PCIE other end recovery counter */ 1110 uint32_t pcie_lc_perf_other_end_recovery; 1111 }; 1112 1113 struct gpu_metrics_v1_8 { 1114 struct metrics_table_header common_header; 1115 1116 /* Temperature (Celsius) */ 1117 uint16_t temperature_hotspot; 1118 uint16_t temperature_mem; 1119 uint16_t temperature_vrsoc; 1120 1121 /* Power (Watts) */ 1122 uint16_t curr_socket_power; 1123 1124 /* Utilization (%) */ 1125 uint16_t average_gfx_activity; 1126 uint16_t average_umc_activity; // memory controller 1127 1128 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1129 uint64_t mem_max_bandwidth; 1130 1131 /* Energy (15.259uJ (2^-16) units) */ 1132 uint64_t energy_accumulator; 1133 1134 /* Driver attached timestamp (in ns) */ 1135 uint64_t system_clock_counter; 1136 1137 /* Accumulation cycle counter */ 1138 uint32_t accumulation_counter; 1139 1140 /* Accumulated throttler residencies */ 1141 uint32_t prochot_residency_acc; 1142 uint32_t ppt_residency_acc; 1143 uint32_t socket_thm_residency_acc; 1144 uint32_t vr_thm_residency_acc; 1145 uint32_t hbm_thm_residency_acc; 1146 1147 /* Clock Lock Status. Each bit corresponds to clock instance */ 1148 uint32_t gfxclk_lock_status; 1149 1150 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1151 uint16_t pcie_link_width; 1152 uint16_t pcie_link_speed; 1153 1154 /* XGMI bus width and bitrate (in Gbps) */ 1155 uint16_t xgmi_link_width; 1156 uint16_t xgmi_link_speed; 1157 1158 /* Utilization Accumulated (%) */ 1159 uint32_t gfx_activity_acc; 1160 uint32_t mem_activity_acc; 1161 1162 /*PCIE accumulated bandwidth (GB/sec) */ 1163 uint64_t pcie_bandwidth_acc; 1164 1165 /*PCIE instantaneous bandwidth (GB/sec) */ 1166 uint64_t pcie_bandwidth_inst; 1167 1168 /* PCIE L0 to recovery state transition accumulated count */ 1169 uint64_t pcie_l0_to_recov_count_acc; 1170 1171 /* PCIE replay accumulated count */ 1172 uint64_t pcie_replay_count_acc; 1173 1174 /* PCIE replay rollover accumulated count */ 1175 uint64_t pcie_replay_rover_count_acc; 1176 1177 /* PCIE NAK sent accumulated count */ 1178 uint32_t pcie_nak_sent_count_acc; 1179 1180 /* PCIE NAK received accumulated count */ 1181 uint32_t pcie_nak_rcvd_count_acc; 1182 1183 /* XGMI accumulated data transfer size(KiloBytes) */ 1184 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1185 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1186 1187 /* XGMI link status(active/inactive) */ 1188 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1189 1190 uint16_t padding; 1191 1192 /* PMFW attached timestamp (10ns resolution) */ 1193 uint64_t firmware_timestamp; 1194 1195 /* Current clocks (Mhz) */ 1196 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1197 uint16_t current_socclk[MAX_CLKS]; 1198 uint16_t current_vclk0[MAX_CLKS]; 1199 uint16_t current_dclk0[MAX_CLKS]; 1200 uint16_t current_uclk; 1201 1202 /* Number of current partition */ 1203 uint16_t num_partition; 1204 1205 /* XCP metrics stats */ 1206 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1207 1208 /* PCIE other end recovery counter */ 1209 uint32_t pcie_lc_perf_other_end_recovery; 1210 }; 1211 1212 /* 1213 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1214 * Use gpu_metrics_v2_1 or later instead. 1215 */ 1216 struct gpu_metrics_v2_0 { 1217 struct metrics_table_header common_header; 1218 1219 /* Driver attached timestamp (in ns) */ 1220 uint64_t system_clock_counter; 1221 1222 /* Temperature */ 1223 uint16_t temperature_gfx; // gfx temperature on APUs 1224 uint16_t temperature_soc; // soc temperature on APUs 1225 uint16_t temperature_core[8]; // CPU core temperature on APUs 1226 uint16_t temperature_l3[2]; 1227 1228 /* Utilization */ 1229 uint16_t average_gfx_activity; 1230 uint16_t average_mm_activity; // UVD or VCN 1231 1232 /* Power/Energy */ 1233 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1234 uint16_t average_cpu_power; 1235 uint16_t average_soc_power; 1236 uint16_t average_gfx_power; 1237 uint16_t average_core_power[8]; // CPU core power on APUs 1238 1239 /* Average clocks */ 1240 uint16_t average_gfxclk_frequency; 1241 uint16_t average_socclk_frequency; 1242 uint16_t average_uclk_frequency; 1243 uint16_t average_fclk_frequency; 1244 uint16_t average_vclk_frequency; 1245 uint16_t average_dclk_frequency; 1246 1247 /* Current clocks */ 1248 uint16_t current_gfxclk; 1249 uint16_t current_socclk; 1250 uint16_t current_uclk; 1251 uint16_t current_fclk; 1252 uint16_t current_vclk; 1253 uint16_t current_dclk; 1254 uint16_t current_coreclk[8]; // CPU core clocks 1255 uint16_t current_l3clk[2]; 1256 1257 /* Throttle status */ 1258 uint32_t throttle_status; 1259 1260 /* Fans */ 1261 uint16_t fan_pwm; 1262 1263 uint16_t padding; 1264 }; 1265 1266 struct gpu_metrics_v2_1 { 1267 struct metrics_table_header common_header; 1268 1269 /* Temperature */ 1270 uint16_t temperature_gfx; // gfx temperature on APUs 1271 uint16_t temperature_soc; // soc temperature on APUs 1272 uint16_t temperature_core[8]; // CPU core temperature on APUs 1273 uint16_t temperature_l3[2]; 1274 1275 /* Utilization */ 1276 uint16_t average_gfx_activity; 1277 uint16_t average_mm_activity; // UVD or VCN 1278 1279 /* Driver attached timestamp (in ns) */ 1280 uint64_t system_clock_counter; 1281 1282 /* Power/Energy */ 1283 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1284 uint16_t average_cpu_power; 1285 uint16_t average_soc_power; 1286 uint16_t average_gfx_power; 1287 uint16_t average_core_power[8]; // CPU core power on APUs 1288 1289 /* Average clocks */ 1290 uint16_t average_gfxclk_frequency; 1291 uint16_t average_socclk_frequency; 1292 uint16_t average_uclk_frequency; 1293 uint16_t average_fclk_frequency; 1294 uint16_t average_vclk_frequency; 1295 uint16_t average_dclk_frequency; 1296 1297 /* Current clocks */ 1298 uint16_t current_gfxclk; 1299 uint16_t current_socclk; 1300 uint16_t current_uclk; 1301 uint16_t current_fclk; 1302 uint16_t current_vclk; 1303 uint16_t current_dclk; 1304 uint16_t current_coreclk[8]; // CPU core clocks 1305 uint16_t current_l3clk[2]; 1306 1307 /* Throttle status */ 1308 uint32_t throttle_status; 1309 1310 /* Fans */ 1311 uint16_t fan_pwm; 1312 1313 uint16_t padding[3]; 1314 }; 1315 1316 struct gpu_metrics_v2_2 { 1317 struct metrics_table_header common_header; 1318 1319 /* Temperature */ 1320 uint16_t temperature_gfx; // gfx temperature on APUs 1321 uint16_t temperature_soc; // soc temperature on APUs 1322 uint16_t temperature_core[8]; // CPU core temperature on APUs 1323 uint16_t temperature_l3[2]; 1324 1325 /* Utilization */ 1326 uint16_t average_gfx_activity; 1327 uint16_t average_mm_activity; // UVD or VCN 1328 1329 /* Driver attached timestamp (in ns) */ 1330 uint64_t system_clock_counter; 1331 1332 /* Power/Energy */ 1333 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1334 uint16_t average_cpu_power; 1335 uint16_t average_soc_power; 1336 uint16_t average_gfx_power; 1337 uint16_t average_core_power[8]; // CPU core power on APUs 1338 1339 /* Average clocks */ 1340 uint16_t average_gfxclk_frequency; 1341 uint16_t average_socclk_frequency; 1342 uint16_t average_uclk_frequency; 1343 uint16_t average_fclk_frequency; 1344 uint16_t average_vclk_frequency; 1345 uint16_t average_dclk_frequency; 1346 1347 /* Current clocks */ 1348 uint16_t current_gfxclk; 1349 uint16_t current_socclk; 1350 uint16_t current_uclk; 1351 uint16_t current_fclk; 1352 uint16_t current_vclk; 1353 uint16_t current_dclk; 1354 uint16_t current_coreclk[8]; // CPU core clocks 1355 uint16_t current_l3clk[2]; 1356 1357 /* Throttle status (ASIC dependent) */ 1358 uint32_t throttle_status; 1359 1360 /* Fans */ 1361 uint16_t fan_pwm; 1362 1363 uint16_t padding[3]; 1364 1365 /* Throttle status (ASIC independent) */ 1366 uint64_t indep_throttle_status; 1367 }; 1368 1369 struct gpu_metrics_v2_3 { 1370 struct metrics_table_header common_header; 1371 1372 /* Temperature */ 1373 uint16_t temperature_gfx; // gfx temperature on APUs 1374 uint16_t temperature_soc; // soc temperature on APUs 1375 uint16_t temperature_core[8]; // CPU core temperature on APUs 1376 uint16_t temperature_l3[2]; 1377 1378 /* Utilization */ 1379 uint16_t average_gfx_activity; 1380 uint16_t average_mm_activity; // UVD or VCN 1381 1382 /* Driver attached timestamp (in ns) */ 1383 uint64_t system_clock_counter; 1384 1385 /* Power/Energy */ 1386 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1387 uint16_t average_cpu_power; 1388 uint16_t average_soc_power; 1389 uint16_t average_gfx_power; 1390 uint16_t average_core_power[8]; // CPU core power on APUs 1391 1392 /* Average clocks */ 1393 uint16_t average_gfxclk_frequency; 1394 uint16_t average_socclk_frequency; 1395 uint16_t average_uclk_frequency; 1396 uint16_t average_fclk_frequency; 1397 uint16_t average_vclk_frequency; 1398 uint16_t average_dclk_frequency; 1399 1400 /* Current clocks */ 1401 uint16_t current_gfxclk; 1402 uint16_t current_socclk; 1403 uint16_t current_uclk; 1404 uint16_t current_fclk; 1405 uint16_t current_vclk; 1406 uint16_t current_dclk; 1407 uint16_t current_coreclk[8]; // CPU core clocks 1408 uint16_t current_l3clk[2]; 1409 1410 /* Throttle status (ASIC dependent) */ 1411 uint32_t throttle_status; 1412 1413 /* Fans */ 1414 uint16_t fan_pwm; 1415 1416 uint16_t padding[3]; 1417 1418 /* Throttle status (ASIC independent) */ 1419 uint64_t indep_throttle_status; 1420 1421 /* Average Temperature */ 1422 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1423 uint16_t average_temperature_soc; // average soc temperature on APUs 1424 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1425 uint16_t average_temperature_l3[2]; 1426 }; 1427 1428 struct gpu_metrics_v2_4 { 1429 struct metrics_table_header common_header; 1430 1431 /* Temperature (unit: centi-Celsius) */ 1432 uint16_t temperature_gfx; 1433 uint16_t temperature_soc; 1434 uint16_t temperature_core[8]; 1435 uint16_t temperature_l3[2]; 1436 1437 /* Utilization (unit: centi) */ 1438 uint16_t average_gfx_activity; 1439 uint16_t average_mm_activity; 1440 1441 /* Driver attached timestamp (in ns) */ 1442 uint64_t system_clock_counter; 1443 1444 /* Power/Energy (unit: mW) */ 1445 uint16_t average_socket_power; 1446 uint16_t average_cpu_power; 1447 uint16_t average_soc_power; 1448 uint16_t average_gfx_power; 1449 uint16_t average_core_power[8]; 1450 1451 /* Average clocks (unit: MHz) */ 1452 uint16_t average_gfxclk_frequency; 1453 uint16_t average_socclk_frequency; 1454 uint16_t average_uclk_frequency; 1455 uint16_t average_fclk_frequency; 1456 uint16_t average_vclk_frequency; 1457 uint16_t average_dclk_frequency; 1458 1459 /* Current clocks (unit: MHz) */ 1460 uint16_t current_gfxclk; 1461 uint16_t current_socclk; 1462 uint16_t current_uclk; 1463 uint16_t current_fclk; 1464 uint16_t current_vclk; 1465 uint16_t current_dclk; 1466 uint16_t current_coreclk[8]; 1467 uint16_t current_l3clk[2]; 1468 1469 /* Throttle status (ASIC dependent) */ 1470 uint32_t throttle_status; 1471 1472 /* Fans */ 1473 uint16_t fan_pwm; 1474 1475 uint16_t padding[3]; 1476 1477 /* Throttle status (ASIC independent) */ 1478 uint64_t indep_throttle_status; 1479 1480 /* Average Temperature (unit: centi-Celsius) */ 1481 uint16_t average_temperature_gfx; 1482 uint16_t average_temperature_soc; 1483 uint16_t average_temperature_core[8]; 1484 uint16_t average_temperature_l3[2]; 1485 1486 /* Power/Voltage (unit: mV) */ 1487 uint16_t average_cpu_voltage; 1488 uint16_t average_soc_voltage; 1489 uint16_t average_gfx_voltage; 1490 1491 /* Power/Current (unit: mA) */ 1492 uint16_t average_cpu_current; 1493 uint16_t average_soc_current; 1494 uint16_t average_gfx_current; 1495 }; 1496 1497 struct gpu_metrics_v3_0 { 1498 struct metrics_table_header common_header; 1499 1500 /* Temperature */ 1501 /* gfx temperature on APUs */ 1502 uint16_t temperature_gfx; 1503 /* soc temperature on APUs */ 1504 uint16_t temperature_soc; 1505 /* CPU core temperature on APUs */ 1506 uint16_t temperature_core[16]; 1507 /* skin temperature on APUs */ 1508 uint16_t temperature_skin; 1509 1510 /* Utilization */ 1511 /* time filtered GFX busy % [0-100] */ 1512 uint16_t average_gfx_activity; 1513 /* time filtered VCN busy % [0-100] */ 1514 uint16_t average_vcn_activity; 1515 /* time filtered IPU per-column busy % [0-100] */ 1516 uint16_t average_ipu_activity[8]; 1517 /* time filtered per-core C0 residency % [0-100]*/ 1518 uint16_t average_core_c0_activity[16]; 1519 /* time filtered DRAM read bandwidth [MB/sec] */ 1520 uint16_t average_dram_reads; 1521 /* time filtered DRAM write bandwidth [MB/sec] */ 1522 uint16_t average_dram_writes; 1523 /* time filtered IPU read bandwidth [MB/sec] */ 1524 uint16_t average_ipu_reads; 1525 /* time filtered IPU write bandwidth [MB/sec] */ 1526 uint16_t average_ipu_writes; 1527 1528 /* Driver attached timestamp (in ns) */ 1529 uint64_t system_clock_counter; 1530 1531 /* Power/Energy */ 1532 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1533 uint32_t average_socket_power; 1534 /* time filtered IPU power [mW] */ 1535 uint16_t average_ipu_power; 1536 /* time filtered APU power [mW] */ 1537 uint32_t average_apu_power; 1538 /* time filtered GFX power [mW] */ 1539 uint32_t average_gfx_power; 1540 /* time filtered dGPU power [mW] */ 1541 uint32_t average_dgpu_power; 1542 /* time filtered sum of core power across all cores in the socket [mW] */ 1543 uint32_t average_all_core_power; 1544 /* calculated core power [mW] */ 1545 uint16_t average_core_power[16]; 1546 /* time filtered total system power [mW] */ 1547 uint16_t average_sys_power; 1548 /* maximum IRM defined STAPM power limit [mW] */ 1549 uint16_t stapm_power_limit; 1550 /* time filtered STAPM power limit [mW] */ 1551 uint16_t current_stapm_power_limit; 1552 1553 /* time filtered clocks [MHz] */ 1554 uint16_t average_gfxclk_frequency; 1555 uint16_t average_socclk_frequency; 1556 uint16_t average_vpeclk_frequency; 1557 uint16_t average_ipuclk_frequency; 1558 uint16_t average_fclk_frequency; 1559 uint16_t average_vclk_frequency; 1560 uint16_t average_uclk_frequency; 1561 uint16_t average_mpipu_frequency; 1562 1563 /* Current clocks */ 1564 /* target core frequency [MHz] */ 1565 uint16_t current_coreclk[16]; 1566 /* CCLK frequency limit enforced on classic cores [MHz] */ 1567 uint16_t current_core_maxfreq; 1568 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1569 uint16_t current_gfx_maxfreq; 1570 1571 /* Throttle Residency (ASIC dependent) */ 1572 uint32_t throttle_residency_prochot; 1573 uint32_t throttle_residency_spl; 1574 uint32_t throttle_residency_fppt; 1575 uint32_t throttle_residency_sppt; 1576 uint32_t throttle_residency_thm_core; 1577 uint32_t throttle_residency_thm_gfx; 1578 uint32_t throttle_residency_thm_soc; 1579 1580 /* Metrics table alpha filter time constant [us] */ 1581 uint32_t time_filter_alphavalue; 1582 }; 1583 1584 struct amdgpu_pmmetrics_header { 1585 uint16_t structure_size; 1586 uint16_t pad; 1587 uint32_t mp1_ip_discovery_version; 1588 uint32_t pmfw_version; 1589 uint32_t pmmetrics_version; 1590 }; 1591 1592 struct amdgpu_pm_metrics { 1593 struct amdgpu_pmmetrics_header common_header; 1594 1595 uint8_t data[]; 1596 }; 1597 1598 struct amdgpu_partition_metrics_v1_0 { 1599 struct metrics_table_header common_header; 1600 /* Current clocks (Mhz) */ 1601 uint16_t current_gfxclk[MAX_XCC]; 1602 uint16_t current_socclk[MAX_CLKS]; 1603 uint16_t current_vclk0[MAX_CLKS]; 1604 uint16_t current_dclk0[MAX_CLKS]; 1605 uint16_t current_uclk; 1606 uint16_t padding; 1607 1608 /* Utilization Instantaneous (%) */ 1609 uint32_t gfx_busy_inst[MAX_XCC]; 1610 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1611 uint16_t vcn_busy[NUM_VCN]; 1612 /* Utilization Accumulated (%) */ 1613 uint64_t gfx_busy_acc[MAX_XCC]; 1614 /* Total App Clock Counter Accumulated */ 1615 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1616 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1617 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1618 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1619 }; 1620 1621 #endif 1622