1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_UCODE_H__ 24 #define __AMDGPU_UCODE_H__ 25 26 #include "amdgpu_socbb.h" 27 28 #define RS64_FW_UC_START_ADDR_LO 0x3000 29 30 struct common_firmware_header { 31 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 32 uint32_t header_size_bytes; /* size of just the header in bytes */ 33 uint16_t header_version_major; /* header version */ 34 uint16_t header_version_minor; /* header version */ 35 uint16_t ip_version_major; /* IP version */ 36 uint16_t ip_version_minor; /* IP version */ 37 uint32_t ucode_version; 38 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 39 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 40 uint32_t crc32; /* crc32 checksum of the payload */ 41 }; 42 43 /* version_major=1, version_minor=0 */ 44 struct mc_firmware_header_v1_0 { 45 struct common_firmware_header header; 46 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 47 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 48 }; 49 50 /* version_major=1, version_minor=0 */ 51 struct smc_firmware_header_v1_0 { 52 struct common_firmware_header header; 53 uint32_t ucode_start_addr; 54 }; 55 56 /* version_major=2, version_minor=0 */ 57 struct smc_firmware_header_v2_0 { 58 struct smc_firmware_header_v1_0 v1_0; 59 uint32_t ppt_offset_bytes; /* soft pptable offset */ 60 uint32_t ppt_size_bytes; /* soft pptable size */ 61 }; 62 63 struct smc_soft_pptable_entry { 64 uint32_t id; 65 uint32_t ppt_offset_bytes; 66 uint32_t ppt_size_bytes; 67 }; 68 69 /* version_major=2, version_minor=1 */ 70 struct smc_firmware_header_v2_1 { 71 struct smc_firmware_header_v1_0 v1_0; 72 uint32_t pptable_count; 73 uint32_t pptable_entry_offset; 74 }; 75 76 struct psp_fw_legacy_bin_desc { 77 uint32_t fw_version; 78 uint32_t offset_bytes; 79 uint32_t size_bytes; 80 }; 81 82 /* version_major=1, version_minor=0 */ 83 struct psp_firmware_header_v1_0 { 84 struct common_firmware_header header; 85 struct psp_fw_legacy_bin_desc sos; 86 }; 87 88 /* version_major=1, version_minor=1 */ 89 struct psp_firmware_header_v1_1 { 90 struct psp_firmware_header_v1_0 v1_0; 91 struct psp_fw_legacy_bin_desc toc; 92 struct psp_fw_legacy_bin_desc kdb; 93 }; 94 95 /* version_major=1, version_minor=2 */ 96 struct psp_firmware_header_v1_2 { 97 struct psp_firmware_header_v1_0 v1_0; 98 struct psp_fw_legacy_bin_desc res; 99 struct psp_fw_legacy_bin_desc kdb; 100 }; 101 102 /* version_major=1, version_minor=3 */ 103 struct psp_firmware_header_v1_3 { 104 struct psp_firmware_header_v1_1 v1_1; 105 struct psp_fw_legacy_bin_desc spl; 106 struct psp_fw_legacy_bin_desc rl; 107 struct psp_fw_legacy_bin_desc sys_drv_aux; 108 struct psp_fw_legacy_bin_desc sos_aux; 109 }; 110 111 struct psp_fw_bin_desc { 112 uint32_t fw_type; 113 uint32_t fw_version; 114 uint32_t offset_bytes; 115 uint32_t size_bytes; 116 }; 117 118 enum psp_fw_type { 119 PSP_FW_TYPE_UNKOWN, 120 PSP_FW_TYPE_PSP_SOS, 121 PSP_FW_TYPE_PSP_SYS_DRV, 122 PSP_FW_TYPE_PSP_KDB, 123 PSP_FW_TYPE_PSP_TOC, 124 PSP_FW_TYPE_PSP_SPL, 125 PSP_FW_TYPE_PSP_RL, 126 PSP_FW_TYPE_PSP_SOC_DRV, 127 PSP_FW_TYPE_PSP_INTF_DRV, 128 PSP_FW_TYPE_PSP_DBG_DRV, 129 PSP_FW_TYPE_PSP_RAS_DRV, 130 PSP_FW_TYPE_PSP_IPKEYMGR_DRV, 131 PSP_FW_TYPE_PSP_SPDM_DRV, 132 PSP_FW_TYPE_MAX_INDEX, 133 }; 134 135 /* version_major=2, version_minor=0 */ 136 struct psp_firmware_header_v2_0 { 137 struct common_firmware_header header; 138 uint32_t psp_fw_bin_count; 139 struct psp_fw_bin_desc psp_fw_bin[]; 140 }; 141 142 /* version_major=2, version_minor=1 */ 143 struct psp_firmware_header_v2_1 { 144 struct common_firmware_header header; 145 uint32_t psp_fw_bin_count; 146 uint32_t psp_aux_fw_bin_index; 147 struct psp_fw_bin_desc psp_fw_bin[]; 148 }; 149 150 /* version_major=1, version_minor=0 */ 151 struct ta_firmware_header_v1_0 { 152 struct common_firmware_header header; 153 struct psp_fw_legacy_bin_desc xgmi; 154 struct psp_fw_legacy_bin_desc ras; 155 struct psp_fw_legacy_bin_desc hdcp; 156 struct psp_fw_legacy_bin_desc dtm; 157 struct psp_fw_legacy_bin_desc securedisplay; 158 }; 159 160 enum ta_fw_type { 161 TA_FW_TYPE_UNKOWN, 162 TA_FW_TYPE_PSP_ASD, 163 TA_FW_TYPE_PSP_XGMI, 164 TA_FW_TYPE_PSP_RAS, 165 TA_FW_TYPE_PSP_HDCP, 166 TA_FW_TYPE_PSP_DTM, 167 TA_FW_TYPE_PSP_RAP, 168 TA_FW_TYPE_PSP_SECUREDISPLAY, 169 TA_FW_TYPE_PSP_XGMI_AUX, 170 TA_FW_TYPE_MAX_INDEX, 171 }; 172 173 /* version_major=2, version_minor=0 */ 174 struct ta_firmware_header_v2_0 { 175 struct common_firmware_header header; 176 uint32_t ta_fw_bin_count; 177 struct psp_fw_bin_desc ta_fw_bin[]; 178 }; 179 180 /* version_major=1, version_minor=0 */ 181 struct gfx_firmware_header_v1_0 { 182 struct common_firmware_header header; 183 uint32_t ucode_feature_version; 184 uint32_t jt_offset; /* jt location */ 185 uint32_t jt_size; /* size of jt */ 186 }; 187 188 /* version_major=2, version_minor=0 */ 189 struct gfx_firmware_header_v2_0 { 190 struct common_firmware_header header; 191 uint32_t ucode_feature_version; 192 uint32_t ucode_size_bytes; 193 uint32_t ucode_offset_bytes; 194 uint32_t data_size_bytes; 195 uint32_t data_offset_bytes; 196 uint32_t ucode_start_addr_lo; 197 uint32_t ucode_start_addr_hi; 198 }; 199 200 /* version_major=1, version_minor=0 */ 201 struct mes_firmware_header_v1_0 { 202 struct common_firmware_header header; 203 uint32_t mes_ucode_version; 204 uint32_t mes_ucode_size_bytes; 205 uint32_t mes_ucode_offset_bytes; 206 uint32_t mes_ucode_data_version; 207 uint32_t mes_ucode_data_size_bytes; 208 uint32_t mes_ucode_data_offset_bytes; 209 uint32_t mes_uc_start_addr_lo; 210 uint32_t mes_uc_start_addr_hi; 211 uint32_t mes_data_start_addr_lo; 212 uint32_t mes_data_start_addr_hi; 213 }; 214 215 /* version_major=1, version_minor=0 */ 216 struct rlc_firmware_header_v1_0 { 217 struct common_firmware_header header; 218 uint32_t ucode_feature_version; 219 uint32_t save_and_restore_offset; 220 uint32_t clear_state_descriptor_offset; 221 uint32_t avail_scratch_ram_locations; 222 uint32_t master_pkt_description_offset; 223 }; 224 225 /* version_major=2, version_minor=0 */ 226 struct rlc_firmware_header_v2_0 { 227 struct common_firmware_header header; 228 uint32_t ucode_feature_version; 229 uint32_t jt_offset; /* jt location */ 230 uint32_t jt_size; /* size of jt */ 231 uint32_t save_and_restore_offset; 232 uint32_t clear_state_descriptor_offset; 233 uint32_t avail_scratch_ram_locations; 234 uint32_t reg_restore_list_size; 235 uint32_t reg_list_format_start; 236 uint32_t reg_list_format_separate_start; 237 uint32_t starting_offsets_start; 238 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 239 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 240 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 241 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 242 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 243 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 244 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 245 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 246 }; 247 248 /* version_major=2, version_minor=1 */ 249 struct rlc_firmware_header_v2_1 { 250 struct rlc_firmware_header_v2_0 v2_0; 251 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */ 252 uint32_t save_restore_list_cntl_ucode_ver; 253 uint32_t save_restore_list_cntl_feature_ver; 254 uint32_t save_restore_list_cntl_size_bytes; 255 uint32_t save_restore_list_cntl_offset_bytes; 256 uint32_t save_restore_list_gpm_ucode_ver; 257 uint32_t save_restore_list_gpm_feature_ver; 258 uint32_t save_restore_list_gpm_size_bytes; 259 uint32_t save_restore_list_gpm_offset_bytes; 260 uint32_t save_restore_list_srm_ucode_ver; 261 uint32_t save_restore_list_srm_feature_ver; 262 uint32_t save_restore_list_srm_size_bytes; 263 uint32_t save_restore_list_srm_offset_bytes; 264 }; 265 266 /* version_major=2, version_minor=2 */ 267 struct rlc_firmware_header_v2_2 { 268 struct rlc_firmware_header_v2_1 v2_1; 269 uint32_t rlc_iram_ucode_size_bytes; 270 uint32_t rlc_iram_ucode_offset_bytes; 271 uint32_t rlc_dram_ucode_size_bytes; 272 uint32_t rlc_dram_ucode_offset_bytes; 273 }; 274 275 /* version_major=2, version_minor=3 */ 276 struct rlc_firmware_header_v2_3 { 277 struct rlc_firmware_header_v2_2 v2_2; 278 uint32_t rlcp_ucode_version; 279 uint32_t rlcp_ucode_feature_version; 280 uint32_t rlcp_ucode_size_bytes; 281 uint32_t rlcp_ucode_offset_bytes; 282 uint32_t rlcv_ucode_version; 283 uint32_t rlcv_ucode_feature_version; 284 uint32_t rlcv_ucode_size_bytes; 285 uint32_t rlcv_ucode_offset_bytes; 286 }; 287 288 /* version_major=2, version_minor=4 */ 289 struct rlc_firmware_header_v2_4 { 290 struct rlc_firmware_header_v2_3 v2_3; 291 uint32_t global_tap_delays_ucode_size_bytes; 292 uint32_t global_tap_delays_ucode_offset_bytes; 293 uint32_t se0_tap_delays_ucode_size_bytes; 294 uint32_t se0_tap_delays_ucode_offset_bytes; 295 uint32_t se1_tap_delays_ucode_size_bytes; 296 uint32_t se1_tap_delays_ucode_offset_bytes; 297 uint32_t se2_tap_delays_ucode_size_bytes; 298 uint32_t se2_tap_delays_ucode_offset_bytes; 299 uint32_t se3_tap_delays_ucode_size_bytes; 300 uint32_t se3_tap_delays_ucode_offset_bytes; 301 }; 302 303 /* version_major=1, version_minor=0 */ 304 struct sdma_firmware_header_v1_0 { 305 struct common_firmware_header header; 306 uint32_t ucode_feature_version; 307 uint32_t ucode_change_version; 308 uint32_t jt_offset; /* jt location */ 309 uint32_t jt_size; /* size of jt */ 310 }; 311 312 /* version_major=1, version_minor=1 */ 313 struct sdma_firmware_header_v1_1 { 314 struct sdma_firmware_header_v1_0 v1_0; 315 uint32_t digest_size; 316 }; 317 318 /* version_major=2, version_minor=0 */ 319 struct sdma_firmware_header_v2_0 { 320 struct common_firmware_header header; 321 uint32_t ucode_feature_version; 322 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 323 uint32_t ctx_jt_offset; /* context thread jt location */ 324 uint32_t ctx_jt_size; /* context thread size of jt */ 325 uint32_t ctl_ucode_offset; 326 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 327 uint32_t ctl_jt_offset; /* control thread jt location */ 328 uint32_t ctl_jt_size; /* control thread size of jt */ 329 }; 330 331 /* version_major=1, version_minor=0 */ 332 struct vpe_firmware_header_v1_0 { 333 struct common_firmware_header header; 334 uint32_t ucode_feature_version; 335 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */ 336 uint32_t ctx_jt_offset; /* context thread jt location */ 337 uint32_t ctx_jt_size; /* context thread size of jt */ 338 uint32_t ctl_ucode_offset; 339 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */ 340 uint32_t ctl_jt_offset; /* control thread jt location */ 341 uint32_t ctl_jt_size; /* control thread size of jt */ 342 }; 343 344 /* version_major=1, version_minor=0 */ 345 struct umsch_mm_firmware_header_v1_0 { 346 struct common_firmware_header header; 347 uint32_t umsch_mm_ucode_version; 348 uint32_t umsch_mm_ucode_size_bytes; 349 uint32_t umsch_mm_ucode_offset_bytes; 350 uint32_t umsch_mm_ucode_data_version; 351 uint32_t umsch_mm_ucode_data_size_bytes; 352 uint32_t umsch_mm_ucode_data_offset_bytes; 353 uint32_t umsch_mm_irq_start_addr_lo; 354 uint32_t umsch_mm_irq_start_addr_hi; 355 uint32_t umsch_mm_uc_start_addr_lo; 356 uint32_t umsch_mm_uc_start_addr_hi; 357 uint32_t umsch_mm_data_start_addr_lo; 358 uint32_t umsch_mm_data_start_addr_hi; 359 }; 360 361 /* version_major=3, version_minor=0 */ 362 struct sdma_firmware_header_v3_0 { 363 struct common_firmware_header header; 364 uint32_t ucode_feature_version; 365 uint32_t ucode_offset_bytes; 366 uint32_t ucode_size_bytes; 367 }; 368 369 /* gpu info payload */ 370 struct gpu_info_firmware_v1_0 { 371 uint32_t gc_num_se; 372 uint32_t gc_num_cu_per_sh; 373 uint32_t gc_num_sh_per_se; 374 uint32_t gc_num_rb_per_se; 375 uint32_t gc_num_tccs; 376 uint32_t gc_num_gprs; 377 uint32_t gc_num_max_gs_thds; 378 uint32_t gc_gs_table_depth; 379 uint32_t gc_gsprim_buff_depth; 380 uint32_t gc_parameter_cache_depth; 381 uint32_t gc_double_offchip_lds_buffer; 382 uint32_t gc_wave_size; 383 uint32_t gc_max_waves_per_simd; 384 uint32_t gc_max_scratch_slots_per_cu; 385 uint32_t gc_lds_size; 386 }; 387 388 struct gpu_info_firmware_v1_1 { 389 struct gpu_info_firmware_v1_0 v1_0; 390 uint32_t num_sc_per_sh; 391 uint32_t num_packer_per_sc; 392 }; 393 394 /* gpu info payload 395 * version_major=1, version_minor=1 */ 396 struct gpu_info_firmware_v1_2 { 397 struct gpu_info_firmware_v1_1 v1_1; 398 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; 399 }; 400 401 /* version_major=1, version_minor=0 */ 402 struct gpu_info_firmware_header_v1_0 { 403 struct common_firmware_header header; 404 uint16_t version_major; /* version */ 405 uint16_t version_minor; /* version */ 406 }; 407 408 /* version_major=1, version_minor=0 */ 409 struct dmcu_firmware_header_v1_0 { 410 struct common_firmware_header header; 411 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */ 412 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */ 413 }; 414 415 /* version_major=1, version_minor=0 */ 416 struct dmcub_firmware_header_v1_0 { 417 struct common_firmware_header header; 418 uint32_t inst_const_bytes; /* size of instruction region, in bytes */ 419 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */ 420 }; 421 422 /* version_major=1, version_minor=0 */ 423 struct imu_firmware_header_v1_0 { 424 struct common_firmware_header header; 425 uint32_t imu_iram_ucode_size_bytes; 426 uint32_t imu_iram_ucode_offset_bytes; 427 uint32_t imu_dram_ucode_size_bytes; 428 uint32_t imu_dram_ucode_offset_bytes; 429 }; 430 431 /* header is fixed size */ 432 union amdgpu_firmware_header { 433 struct common_firmware_header common; 434 struct mc_firmware_header_v1_0 mc; 435 struct smc_firmware_header_v1_0 smc; 436 struct smc_firmware_header_v2_0 smc_v2_0; 437 struct psp_firmware_header_v1_0 psp; 438 struct psp_firmware_header_v1_1 psp_v1_1; 439 struct psp_firmware_header_v1_3 psp_v1_3; 440 struct psp_firmware_header_v2_0 psp_v2_0; 441 struct psp_firmware_header_v2_0 psp_v2_1; 442 struct ta_firmware_header_v1_0 ta; 443 struct ta_firmware_header_v2_0 ta_v2_0; 444 struct gfx_firmware_header_v1_0 gfx; 445 struct gfx_firmware_header_v2_0 gfx_v2_0; 446 struct rlc_firmware_header_v1_0 rlc; 447 struct rlc_firmware_header_v2_0 rlc_v2_0; 448 struct rlc_firmware_header_v2_1 rlc_v2_1; 449 struct rlc_firmware_header_v2_2 rlc_v2_2; 450 struct rlc_firmware_header_v2_3 rlc_v2_3; 451 struct rlc_firmware_header_v2_4 rlc_v2_4; 452 struct sdma_firmware_header_v1_0 sdma; 453 struct sdma_firmware_header_v1_1 sdma_v1_1; 454 struct sdma_firmware_header_v2_0 sdma_v2_0; 455 struct sdma_firmware_header_v3_0 sdma_v3_0; 456 struct gpu_info_firmware_header_v1_0 gpu_info; 457 struct dmcu_firmware_header_v1_0 dmcu; 458 struct dmcub_firmware_header_v1_0 dmcub; 459 struct imu_firmware_header_v1_0 imu; 460 uint8_t raw[0x100]; 461 }; 462 463 #define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2) 464 465 /* 466 * fw loading support 467 */ 468 enum AMDGPU_UCODE_ID { 469 AMDGPU_UCODE_ID_CAP = 0, 470 AMDGPU_UCODE_ID_SDMA0, 471 AMDGPU_UCODE_ID_SDMA1, 472 AMDGPU_UCODE_ID_SDMA2, 473 AMDGPU_UCODE_ID_SDMA3, 474 AMDGPU_UCODE_ID_SDMA4, 475 AMDGPU_UCODE_ID_SDMA5, 476 AMDGPU_UCODE_ID_SDMA6, 477 AMDGPU_UCODE_ID_SDMA7, 478 AMDGPU_UCODE_ID_SDMA_UCODE_TH0, 479 AMDGPU_UCODE_ID_SDMA_UCODE_TH1, 480 AMDGPU_UCODE_ID_SDMA_RS64, 481 AMDGPU_UCODE_ID_CP_CE, 482 AMDGPU_UCODE_ID_CP_PFP, 483 AMDGPU_UCODE_ID_CP_ME, 484 AMDGPU_UCODE_ID_CP_RS64_PFP, 485 AMDGPU_UCODE_ID_CP_RS64_ME, 486 AMDGPU_UCODE_ID_CP_RS64_MEC, 487 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK, 488 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK, 489 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK, 490 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK, 491 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK, 492 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK, 493 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK, 494 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK, 495 AMDGPU_UCODE_ID_CP_MEC1, 496 AMDGPU_UCODE_ID_CP_MEC1_JT, 497 AMDGPU_UCODE_ID_CP_MEC2, 498 AMDGPU_UCODE_ID_CP_MEC2_JT, 499 AMDGPU_UCODE_ID_CP_MES, 500 AMDGPU_UCODE_ID_CP_MES_DATA, 501 AMDGPU_UCODE_ID_CP_MES1, 502 AMDGPU_UCODE_ID_CP_MES1_DATA, 503 AMDGPU_UCODE_ID_IMU_I, 504 AMDGPU_UCODE_ID_IMU_D, 505 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS, 506 AMDGPU_UCODE_ID_SE0_TAP_DELAYS, 507 AMDGPU_UCODE_ID_SE1_TAP_DELAYS, 508 AMDGPU_UCODE_ID_SE2_TAP_DELAYS, 509 AMDGPU_UCODE_ID_SE3_TAP_DELAYS, 510 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL, 511 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM, 512 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, 513 AMDGPU_UCODE_ID_RLC_IRAM, 514 AMDGPU_UCODE_ID_RLC_DRAM, 515 AMDGPU_UCODE_ID_RLC_P, 516 AMDGPU_UCODE_ID_RLC_V, 517 AMDGPU_UCODE_ID_RLC_G, 518 AMDGPU_UCODE_ID_STORAGE, 519 AMDGPU_UCODE_ID_SMC, 520 AMDGPU_UCODE_ID_PPTABLE, 521 AMDGPU_UCODE_ID_UVD, 522 AMDGPU_UCODE_ID_UVD1, 523 AMDGPU_UCODE_ID_VCE, 524 AMDGPU_UCODE_ID_VCN, 525 AMDGPU_UCODE_ID_VCN1, 526 AMDGPU_UCODE_ID_DMCU_ERAM, 527 AMDGPU_UCODE_ID_DMCU_INTV, 528 AMDGPU_UCODE_ID_VCN0_RAM, 529 AMDGPU_UCODE_ID_VCN1_RAM, 530 AMDGPU_UCODE_ID_DMCUB, 531 AMDGPU_UCODE_ID_VPE_CTX, 532 AMDGPU_UCODE_ID_VPE_CTL, 533 AMDGPU_UCODE_ID_VPE, 534 AMDGPU_UCODE_ID_UMSCH_MM_UCODE, 535 AMDGPU_UCODE_ID_UMSCH_MM_DATA, 536 AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER, 537 AMDGPU_UCODE_ID_P2S_TABLE, 538 AMDGPU_UCODE_ID_JPEG_RAM, 539 AMDGPU_UCODE_ID_ISP, 540 AMDGPU_UCODE_ID_MAXIMUM, 541 }; 542 543 /* engine firmware status */ 544 enum AMDGPU_UCODE_STATUS { 545 AMDGPU_UCODE_STATUS_INVALID, 546 AMDGPU_UCODE_STATUS_NOT_LOADED, 547 AMDGPU_UCODE_STATUS_LOADED, 548 }; 549 550 enum amdgpu_firmware_load_type { 551 AMDGPU_FW_LOAD_DIRECT = 0, 552 AMDGPU_FW_LOAD_PSP, 553 AMDGPU_FW_LOAD_SMU, 554 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO, 555 }; 556 557 enum amdgpu_ucode_required { 558 AMDGPU_UCODE_OPTIONAL, 559 AMDGPU_UCODE_REQUIRED, 560 }; 561 562 /* conform to smu_ucode_xfer_cz.h */ 563 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 564 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 565 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 566 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 567 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 568 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 569 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 570 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 571 572 /* amdgpu firmware info */ 573 struct amdgpu_firmware_info { 574 /* ucode ID */ 575 enum AMDGPU_UCODE_ID ucode_id; 576 /* request_firmware */ 577 const struct firmware *fw; 578 /* starting mc address */ 579 uint64_t mc_addr; 580 /* kernel linear address */ 581 void *kaddr; 582 /* ucode_size_bytes */ 583 uint32_t ucode_size; 584 /* starting tmr mc address */ 585 uint32_t tmr_mc_addr_lo; 586 uint32_t tmr_mc_addr_hi; 587 }; 588 589 struct amdgpu_firmware { 590 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 591 enum amdgpu_firmware_load_type load_type; 592 struct amdgpu_bo *fw_buf; 593 unsigned int fw_size; 594 unsigned int max_ucodes; 595 /* firmwares are loaded by psp instead of smu from vega10 */ 596 const struct amdgpu_psp_funcs *funcs; 597 struct amdgpu_bo *rbuf; 598 struct mutex mutex; 599 600 /* gpu info firmware data pointer */ 601 const struct firmware *gpu_info_fw; 602 603 void *fw_buf_ptr; 604 uint64_t fw_buf_mc; 605 uint32_t pldm_version; 606 }; 607 608 struct kicker_device{ 609 unsigned short device; 610 u8 revision; 611 }; 612 613 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 614 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 615 void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr); 616 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 617 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 618 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 619 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr); 620 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr); 621 __printf(4, 5) 622 int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw, 623 enum amdgpu_ucode_required required, const char *fmt, ...); 624 void amdgpu_ucode_release(const struct firmware **fw); 625 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 626 uint16_t hdr_major, uint16_t hdr_minor); 627 628 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 629 int amdgpu_ucode_create_bo(struct amdgpu_device *adev); 630 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev); 631 void amdgpu_ucode_free_bo(struct amdgpu_device *adev); 632 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev); 633 634 enum amdgpu_firmware_load_type 635 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type); 636 637 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id); 638 639 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len); 640 bool amdgpu_is_kicker_fw(struct amdgpu_device *adev); 641 642 #endif 643