1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13 #include "llvm/CodeGen/MachinePassManager.h"
14 #include "llvm/IR/PassManager.h"
15 #include "llvm/Pass.h"
16 #include "llvm/Support/AMDGPUAddrSpace.h"
17 #include "llvm/Support/CodeGen.h"
18
19 namespace llvm {
20
21 class AMDGPUTargetMachine;
22 class GCNTargetMachine;
23 class TargetMachine;
24
25 // GlobalISel passes
26 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
27 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
28 void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &);
29 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
30 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
31 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
32 FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
33 FunctionPass *createAMDGPURegBankSelectPass();
34 FunctionPass *createAMDGPURegBankLegalizePass();
35
36 // SI Passes
37 FunctionPass *createGCNDPPCombinePass();
38 FunctionPass *createSIAnnotateControlFlowLegacyPass();
39 FunctionPass *createSIFoldOperandsLegacyPass();
40 FunctionPass *createSIPeepholeSDWALegacyPass();
41 FunctionPass *createSILowerI1CopiesLegacyPass();
42 FunctionPass *createSIShrinkInstructionsLegacyPass();
43 FunctionPass *createSILoadStoreOptimizerLegacyPass();
44 FunctionPass *createSIWholeQuadModeLegacyPass();
45 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
46 FunctionPass *createSIOptimizeExecMaskingPreRAPass();
47 FunctionPass *createSIOptimizeVGPRLiveRangeLegacyPass();
48 FunctionPass *createSIFixSGPRCopiesLegacyPass();
49 FunctionPass *createLowerWWMCopiesPass();
50 FunctionPass *createSIMemoryLegalizerPass();
51 FunctionPass *createSIInsertWaitcntsPass();
52 FunctionPass *createSIPreAllocateWWMRegsLegacyPass();
53 FunctionPass *createSIFormMemoryClausesLegacyPass();
54
55 FunctionPass *createSIPostRABundlerPass();
56 FunctionPass *createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *);
57 ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
58 FunctionPass *createAMDGPUCodeGenPreparePass();
59 FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
60 FunctionPass *createAMDGPUReserveWWMRegsPass();
61 FunctionPass *createAMDGPURewriteOutArgumentsPass();
62 ModulePass *
63 createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
64 ModulePass *createAMDGPULowerBufferFatPointersPass();
65 FunctionPass *createSIModeRegisterPass();
66 FunctionPass *createGCNPreRAOptimizationsLegacyPass();
67 FunctionPass *createAMDGPUPreloadKernArgPrologLegacyPass();
68 ModulePass *createAMDGPUPreloadKernelArgumentsLegacyPass(const TargetMachine *);
69
70 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
AMDGPUSimplifyLibCallsPassAMDGPUSimplifyLibCallsPass71 AMDGPUSimplifyLibCallsPass() {}
72 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
73 };
74
75 struct AMDGPUImageIntrinsicOptimizerPass
76 : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
AMDGPUImageIntrinsicOptimizerPassAMDGPUImageIntrinsicOptimizerPass77 AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM) : TM(TM) {}
78 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
79
80 private:
81 TargetMachine &TM;
82 };
83
84 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
85 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
86 };
87
88 class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
89 public:
90 SILowerI1CopiesPass() = default;
91 PreservedAnalyses run(MachineFunction &MF,
92 MachineFunctionAnalysisManager &MFAM);
93 };
94
95 void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
96
97 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
98
99 void initializeAMDGPUAsmPrinterPass(PassRegistry &);
100
101 // DPP/Iterative option enables the atomic optimizer with given strategy
102 // whereas None disables the atomic optimizer.
103 enum class ScanOptions { DPP, Iterative, None };
104 FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
105 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
106 extern char &AMDGPUAtomicOptimizerID;
107
108 ModulePass *createAMDGPUCtorDtorLoweringLegacyPass();
109 void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &);
110 extern char &AMDGPUCtorDtorLoweringLegacyPassID;
111
112 FunctionPass *createAMDGPULowerKernelArgumentsPass();
113 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
114 extern char &AMDGPULowerKernelArgumentsID;
115
116 FunctionPass *createAMDGPUPromoteKernelArgumentsPass();
117 void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &);
118 extern char &AMDGPUPromoteKernelArgumentsID;
119
120 struct AMDGPUPromoteKernelArgumentsPass
121 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
122 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
123 };
124
125 ModulePass *createAMDGPULowerKernelAttributesPass();
126 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &);
127 extern char &AMDGPULowerKernelAttributesID;
128
129 struct AMDGPULowerKernelAttributesPass
130 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
131 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
132 };
133
134 void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &);
135 extern char &AMDGPULowerModuleLDSLegacyPassID;
136
137 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
138 const AMDGPUTargetMachine &TM;
AMDGPULowerModuleLDSPassAMDGPULowerModuleLDSPass139 AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
140
141 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
142 };
143
144 void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &);
145 extern char &AMDGPULowerBufferFatPointersID;
146
147 struct AMDGPULowerBufferFatPointersPass
148 : PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
AMDGPULowerBufferFatPointersPassAMDGPULowerBufferFatPointersPass149 AMDGPULowerBufferFatPointersPass(const TargetMachine &TM) : TM(TM) {}
150 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
151
152 private:
153 const TargetMachine &TM;
154 };
155
156 void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
157 extern char &AMDGPUReserveWWMRegsLegacyID;
158
159 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
160 extern char &AMDGPURewriteOutArgumentsID;
161
162 void initializeGCNDPPCombineLegacyPass(PassRegistry &);
163 extern char &GCNDPPCombineLegacyID;
164
165 void initializeSIFoldOperandsLegacyPass(PassRegistry &);
166 extern char &SIFoldOperandsLegacyID;
167
168 void initializeSIPeepholeSDWALegacyPass(PassRegistry &);
169 extern char &SIPeepholeSDWALegacyID;
170
171 void initializeSIShrinkInstructionsLegacyPass(PassRegistry &);
172 extern char &SIShrinkInstructionsLegacyID;
173
174 void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
175 extern char &SIFixSGPRCopiesLegacyID;
176
177 void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
178 extern char &SIFixVGPRCopiesID;
179
180 void initializeSILowerWWMCopiesLegacyPass(PassRegistry &);
181 extern char &SILowerWWMCopiesLegacyID;
182
183 void initializeSILowerI1CopiesLegacyPass(PassRegistry &);
184 extern char &SILowerI1CopiesLegacyID;
185
186 void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
187 extern char &AMDGPUGlobalISelDivergenceLoweringID;
188
189 void initializeAMDGPURegBankSelectPass(PassRegistry &);
190 extern char &AMDGPURegBankSelectID;
191
192 void initializeAMDGPURegBankLegalizePass(PassRegistry &);
193 extern char &AMDGPURegBankLegalizeID;
194
195 void initializeAMDGPUMarkLastScratchLoadLegacyPass(PassRegistry &);
196 extern char &AMDGPUMarkLastScratchLoadID;
197
198 void initializeSILowerSGPRSpillsLegacyPass(PassRegistry &);
199 extern char &SILowerSGPRSpillsLegacyID;
200
201 void initializeSILoadStoreOptimizerLegacyPass(PassRegistry &);
202 extern char &SILoadStoreOptimizerLegacyID;
203
204 void initializeSIWholeQuadModeLegacyPass(PassRegistry &);
205 extern char &SIWholeQuadModeID;
206
207 void initializeSILowerControlFlowLegacyPass(PassRegistry &);
208 extern char &SILowerControlFlowLegacyID;
209
210 void initializeSIPreEmitPeepholeLegacyPass(PassRegistry &);
211 extern char &SIPreEmitPeepholeID;
212
213 void initializeSILateBranchLoweringLegacyPass(PassRegistry &);
214 extern char &SILateBranchLoweringPassID;
215
216 void initializeSIOptimizeExecMaskingLegacyPass(PassRegistry &);
217 extern char &SIOptimizeExecMaskingLegacyID;
218
219 void initializeSIPreAllocateWWMRegsLegacyPass(PassRegistry &);
220 extern char &SIPreAllocateWWMRegsLegacyID;
221
222 void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &);
223 extern char &AMDGPUImageIntrinsicOptimizerID;
224
225 void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &);
226 extern char &AMDGPUPerfHintAnalysisLegacyID;
227
228 void initializeGCNRegPressurePrinterPass(PassRegistry &);
229 extern char &GCNRegPressurePrinterID;
230
231 void initializeAMDGPUPreloadKernArgPrologLegacyPass(PassRegistry &);
232 extern char &AMDGPUPreloadKernArgPrologLegacyID;
233
234 void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
235 extern char &AMDGPUPreloadKernelArgumentsLegacyID;
236
237 // Passes common to R600 and SI
238 FunctionPass *createAMDGPUPromoteAlloca();
239 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
240 extern char &AMDGPUPromoteAllocaID;
241
242 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
AMDGPUPromoteAllocaPassAMDGPUPromoteAllocaPass243 AMDGPUPromoteAllocaPass(TargetMachine &TM) : TM(TM) {}
244 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
245
246 private:
247 TargetMachine &TM;
248 };
249
250 struct AMDGPUPromoteAllocaToVectorPass
251 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
AMDGPUPromoteAllocaToVectorPassAMDGPUPromoteAllocaToVectorPass252 AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM) : TM(TM) {}
253 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
254
255 private:
256 TargetMachine &TM;
257 };
258
259 struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
AMDGPUAtomicOptimizerPassAMDGPUAtomicOptimizerPass260 AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
261 : TM(TM), ScanImpl(ScanImpl) {}
262 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
263
264 private:
265 TargetMachine &TM;
266 ScanOptions ScanImpl;
267 };
268
269 struct AMDGPUInsertDelayAluPass
270 : public PassInfoMixin<AMDGPUInsertDelayAluPass> {
271 PreservedAnalyses run(MachineFunction &F,
272 MachineFunctionAnalysisManager &MFAM);
273 };
274
275 Pass *createAMDGPUStructurizeCFGPass();
276 FunctionPass *createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel);
277 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
278
279 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
GlobalOptAMDGPUAlwaysInlinePass280 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
281 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
282
283 private:
284 bool GlobalOpt;
285 };
286
287 void initializeAMDGPUSwLowerLDSLegacyPass(PassRegistry &);
288 extern char &AMDGPUSwLowerLDSLegacyPassID;
289 ModulePass *
290 createAMDGPUSwLowerLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
291
292 struct AMDGPUSwLowerLDSPass : PassInfoMixin<AMDGPUSwLowerLDSPass> {
293 const AMDGPUTargetMachine &TM;
AMDGPUSwLowerLDSPassAMDGPUSwLowerLDSPass294 AMDGPUSwLowerLDSPass(const AMDGPUTargetMachine &TM_) : TM(TM_) {}
295 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
296 };
297
298 class AMDGPUCodeGenPreparePass
299 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
300 private:
301 TargetMachine &TM;
302
303 public:
AMDGPUCodeGenPreparePass(TargetMachine & TM)304 AMDGPUCodeGenPreparePass(TargetMachine &TM) : TM(TM){};
305 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
306 };
307
308 class AMDGPULateCodeGenPreparePass
309 : public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
310 private:
311 const GCNTargetMachine &TM;
312
313 public:
AMDGPULateCodeGenPreparePass(const GCNTargetMachine & TM)314 AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM) : TM(TM) {};
315 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
316 };
317
318 class AMDGPULowerKernelArgumentsPass
319 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
320 private:
321 TargetMachine &TM;
322
323 public:
AMDGPULowerKernelArgumentsPass(TargetMachine & TM)324 AMDGPULowerKernelArgumentsPass(TargetMachine &TM) : TM(TM){};
325 PreservedAnalyses run(Function &, FunctionAnalysisManager &);
326 };
327
328 struct AMDGPUAttributorOptions {
329 bool IsClosedWorld = false;
330 };
331
332 class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
333 private:
334 TargetMachine &TM;
335
336 AMDGPUAttributorOptions Options;
337
338 const ThinOrFullLTOPhase LTOPhase;
339
340 public:
341 AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options,
342 ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None)
TM(TM)343 : TM(TM), Options(Options), LTOPhase(LTOPhase) {};
344 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
345 };
346
347 class AMDGPUPreloadKernelArgumentsPass
348 : public PassInfoMixin<AMDGPUPreloadKernelArgumentsPass> {
349 const TargetMachine &TM;
350
351 public:
AMDGPUPreloadKernelArgumentsPass(const TargetMachine & TM)352 explicit AMDGPUPreloadKernelArgumentsPass(const TargetMachine &TM) : TM(TM) {}
353
354 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
355 };
356
357 class AMDGPUAnnotateUniformValuesPass
358 : public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
359 public:
AMDGPUAnnotateUniformValuesPass()360 AMDGPUAnnotateUniformValuesPass() {}
361 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
362 };
363
364 class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
365 public:
SIModeRegisterPass()366 SIModeRegisterPass() {}
367 PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
368 };
369
370 class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
371 public:
372 PreservedAnalyses run(MachineFunction &MF,
373 MachineFunctionAnalysisManager &MFAM);
isRequired()374 static bool isRequired() { return true; }
375 };
376
377 class GCNCreateVOPDPass : public PassInfoMixin<GCNCreateVOPDPass> {
378 public:
379 PreservedAnalyses run(MachineFunction &MF,
380 MachineFunctionAnalysisManager &AM);
381 };
382
383 class AMDGPUMarkLastScratchLoadPass
384 : public PassInfoMixin<AMDGPUMarkLastScratchLoadPass> {
385 public:
386 PreservedAnalyses run(MachineFunction &MF,
387 MachineFunctionAnalysisManager &AM);
388 };
389
390 class SIInsertWaitcntsPass : public PassInfoMixin<SIInsertWaitcntsPass> {
391 public:
392 PreservedAnalyses run(MachineFunction &MF,
393 MachineFunctionAnalysisManager &MFAM);
isRequired()394 static bool isRequired() { return true; }
395 };
396
397 class SIInsertHardClausesPass : public PassInfoMixin<SIInsertHardClausesPass> {
398 public:
399 PreservedAnalyses run(MachineFunction &MF,
400 MachineFunctionAnalysisManager &MFAM);
401 };
402
403 class SILateBranchLoweringPass
404 : public PassInfoMixin<SILateBranchLoweringPass> {
405 public:
406 PreservedAnalyses run(MachineFunction &MF,
407 MachineFunctionAnalysisManager &MFAM);
isRequired()408 static bool isRequired() { return true; }
409 };
410
411 class SIPreEmitPeepholePass : public PassInfoMixin<SIPreEmitPeepholePass> {
412 public:
413 PreservedAnalyses run(MachineFunction &MF,
414 MachineFunctionAnalysisManager &MFAM);
isRequired()415 static bool isRequired() { return true; }
416 };
417
418 class AMDGPUSetWavePriorityPass
419 : public PassInfoMixin<AMDGPUSetWavePriorityPass> {
420 public:
421 PreservedAnalyses run(MachineFunction &MF,
422 MachineFunctionAnalysisManager &MFAM);
423 };
424
425 FunctionPass *createAMDGPUAnnotateUniformValuesLegacy();
426
427 ModulePass *createAMDGPUPrintfRuntimeBinding();
428 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
429 extern char &AMDGPUPrintfRuntimeBindingID;
430
431 void initializeAMDGPUResourceUsageAnalysisWrapperPassPass(PassRegistry &);
432 extern char &AMDGPUResourceUsageAnalysisID;
433
434 struct AMDGPUPrintfRuntimeBindingPass
435 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
436 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
437 };
438
439 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
440 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
441 };
442
443 void initializeSIOptimizeExecMaskingPreRALegacyPass(PassRegistry &);
444 extern char &SIOptimizeExecMaskingPreRAID;
445
446 void initializeSIOptimizeVGPRLiveRangeLegacyPass(PassRegistry &);
447 extern char &SIOptimizeVGPRLiveRangeLegacyID;
448
449 void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &);
450 extern char &AMDGPUAnnotateUniformValuesLegacyPassID;
451
452 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
453 extern char &AMDGPUCodeGenPrepareID;
454
455 void initializeAMDGPURemoveIncompatibleFunctionsLegacyPass(PassRegistry &);
456 extern char &AMDGPURemoveIncompatibleFunctionsID;
457
458 void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &);
459 extern char &AMDGPULateCodeGenPrepareLegacyID;
460
461 FunctionPass *createAMDGPURewriteUndefForPHILegacyPass();
462 void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &);
463 extern char &AMDGPURewriteUndefForPHILegacyPassID;
464
465 class AMDGPURewriteUndefForPHIPass
466 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
467 public:
468 AMDGPURewriteUndefForPHIPass() = default;
469 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
470 };
471
472 class SIAnnotateControlFlowPass
473 : public PassInfoMixin<SIAnnotateControlFlowPass> {
474 private:
475 const AMDGPUTargetMachine &TM;
476
477 public:
SIAnnotateControlFlowPass(const AMDGPUTargetMachine & TM)478 SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
479 PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
480 };
481
482 void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
483 extern char &SIAnnotateControlFlowLegacyPassID;
484
485 void initializeSIMemoryLegalizerLegacyPass(PassRegistry &);
486 extern char &SIMemoryLegalizerID;
487
488 void initializeSIModeRegisterLegacyPass(PassRegistry &);
489 extern char &SIModeRegisterID;
490
491 void initializeAMDGPUInsertDelayAluLegacyPass(PassRegistry &);
492 extern char &AMDGPUInsertDelayAluID;
493
494 void initializeSIInsertHardClausesLegacyPass(PassRegistry &);
495 extern char &SIInsertHardClausesID;
496
497 void initializeSIInsertWaitcntsLegacyPass(PassRegistry &);
498 extern char &SIInsertWaitcntsID;
499
500 void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
501 extern char &SIFormMemoryClausesID;
502
503 void initializeSIPostRABundlerLegacyPass(PassRegistry &);
504 extern char &SIPostRABundlerLegacyID;
505
506 void initializeGCNCreateVOPDLegacyPass(PassRegistry &);
507 extern char &GCNCreateVOPDID;
508
509 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
510 extern char &AMDGPUUnifyDivergentExitNodesID;
511
512 ImmutablePass *createAMDGPUAAWrapperPass();
513 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
514 ImmutablePass *createAMDGPUExternalAAWrapperPass();
515 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
516
517 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
518
519 ModulePass *createAMDGPUExportKernelRuntimeHandlesLegacyPass();
520 void initializeAMDGPUExportKernelRuntimeHandlesLegacyPass(PassRegistry &);
521 extern char &AMDGPUExportKernelRuntimeHandlesLegacyID;
522
523 void initializeGCNNSAReassignLegacyPass(PassRegistry &);
524 extern char &GCNNSAReassignID;
525
526 void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &);
527 extern char &GCNPreRALongBranchRegID;
528
529 void initializeGCNPreRAOptimizationsLegacyPass(PassRegistry &);
530 extern char &GCNPreRAOptimizationsID;
531
532 FunctionPass *createAMDGPUSetWavePriorityPass();
533 void initializeAMDGPUSetWavePriorityLegacyPass(PassRegistry &);
534
535 void initializeGCNRewritePartialRegUsesLegacyPass(llvm::PassRegistry &);
536 extern char &GCNRewritePartialRegUsesID;
537
538 void initializeAMDGPUWaitSGPRHazardsLegacyPass(PassRegistry &);
539 extern char &AMDGPUWaitSGPRHazardsLegacyID;
540
541 class AMDGPURewriteAGPRCopyMFMAPass
542 : public PassInfoMixin<AMDGPURewriteAGPRCopyMFMAPass> {
543 public:
544 AMDGPURewriteAGPRCopyMFMAPass() = default;
545 PreservedAnalyses run(MachineFunction &MF,
546 MachineFunctionAnalysisManager &MFAM);
547 };
548
549 void initializeAMDGPURewriteAGPRCopyMFMALegacyPass(PassRegistry &);
550 extern char &AMDGPURewriteAGPRCopyMFMALegacyID;
551
552 namespace AMDGPU {
553 enum TargetIndex {
554 TI_CONSTDATA_START,
555 TI_SCRATCH_RSRC_DWORD0,
556 TI_SCRATCH_RSRC_DWORD1,
557 TI_SCRATCH_RSRC_DWORD2,
558 TI_SCRATCH_RSRC_DWORD3
559 };
560
addrspacesMayAlias(unsigned AS1,unsigned AS2)561 static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
562 if (AS1 > AMDGPUAS::MAX_AMDGPU_ADDRESS || AS2 > AMDGPUAS::MAX_AMDGPU_ADDRESS)
563 return true;
564
565 // clang-format off
566 static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
567 /* Flat Global Region Local Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
568 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
569 /* Global */ {true, true, false, false, true, false, true, true, true, true},
570 /* Region */ {false, false, true, false, false, false, false, false, false, false},
571 /* Local */ {true, false, false, true, false, false, false, false, false, false},
572 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
573 /* Private */ {true, false, false, false, false, true, false, false, false, false},
574 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
575 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
576 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
577 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
578 };
579 // clang-format on
580 static_assert(std::size(ASAliasRules) == AMDGPUAS::MAX_AMDGPU_ADDRESS + 1);
581
582 return ASAliasRules[AS1][AS2];
583 }
584
585 }
586
587 } // End namespace llvm
588
589 #endif
590