1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24 #ifndef AMDGPU_VIRT_H
25 #define AMDGPU_VIRT_H
26
27 #include "amdgv_sriovmsg.h"
28
29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36 /* flags for indirect register access path supported by rlcg for sriov */
37 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
38 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
39 #define AMDGPU_RLCG_GC_READ (0x1 << 28)
40 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
41
42 /* error code for indirect register access path supported by rlcg for sriov */
43 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
46
47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
48 #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000
49
50 /* all asic after AI use this offset */
51 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
52 /* tonga/fiji use this offset */
53 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
54
55 #define AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT 2
56
57 enum amdgpu_sriov_vf_mode {
58 SRIOV_VF_MODE_BARE_METAL = 0,
59 SRIOV_VF_MODE_ONE_VF,
60 SRIOV_VF_MODE_MULTI_VF,
61 };
62
63 struct amdgpu_mm_table {
64 struct amdgpu_bo *bo;
65 uint32_t *cpu_addr;
66 uint64_t gpu_addr;
67 };
68
69 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16
70
71 /* struct error_entry - amdgpu VF error information. */
72 struct amdgpu_vf_error_buffer {
73 struct mutex lock;
74 int read_count;
75 int write_count;
76 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
77 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
78 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
79 };
80
81 enum idh_request;
82
83 /**
84 * struct amdgpu_virt_ops - amdgpu device virt operations
85 */
86 struct amdgpu_virt_ops {
87 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
88 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
89 int (*req_init_data)(struct amdgpu_device *adev);
90 int (*reset_gpu)(struct amdgpu_device *adev);
91 void (*ready_to_reset)(struct amdgpu_device *adev);
92 int (*wait_reset)(struct amdgpu_device *adev);
93 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
94 u32 data1, u32 data2, u32 data3);
95 void (*ras_poison_handler)(struct amdgpu_device *adev,
96 enum amdgpu_ras_block block);
97 bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
98 int (*req_ras_err_count)(struct amdgpu_device *adev);
99 };
100
101 /*
102 * Firmware Reserve Frame buffer
103 */
104 struct amdgpu_virt_fw_reserve {
105 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
106 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
107 void *ras_telemetry;
108 unsigned int checksum_key;
109 };
110
111 /*
112 * Legacy GIM header
113 *
114 * Defination between PF and VF
115 * Structures forcibly aligned to 4 to keep the same style as PF.
116 */
117 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
118
119 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
120 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
121
122 enum AMDGIM_FEATURE_FLAG {
123 /* GIM supports feature of Error log collecting */
124 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
125 /* GIM supports feature of loading uCodes */
126 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
127 /* VRAM LOST by GIM */
128 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
129 /* MM bandwidth */
130 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
131 /* PP ONE VF MODE in GIM */
132 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
133 /* Indirect Reg Access enabled */
134 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
135 /* AV1 Support MODE*/
136 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
137 /* VCN RB decouple */
138 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),
139 /* MES info */
140 AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8),
141 AMDGIM_FEATURE_RAS_CAPS = (1 << 9),
142 AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10),
143 };
144
145 enum AMDGIM_REG_ACCESS_FLAG {
146 /* Use PSP to program IH_RB_CNTL */
147 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
148 /* Use RLC to program MMHUB regs */
149 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
150 /* Use RLC to program GC regs */
151 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
152 };
153
154 struct amdgim_pf2vf_info_v1 {
155 /* header contains size and version */
156 struct amd_sriov_msg_pf2vf_info_header header;
157 /* max_width * max_height */
158 unsigned int uvd_enc_max_pixels_count;
159 /* 16x16 pixels/sec, codec independent */
160 unsigned int uvd_enc_max_bandwidth;
161 /* max_width * max_height */
162 unsigned int vce_enc_max_pixels_count;
163 /* 16x16 pixels/sec, codec independent */
164 unsigned int vce_enc_max_bandwidth;
165 /* MEC FW position in kb from the start of visible frame buffer */
166 unsigned int mecfw_kboffset;
167 /* The features flags of the GIM driver supports. */
168 unsigned int feature_flags;
169 /* use private key from mailbox 2 to create chueksum */
170 unsigned int checksum;
171 } __aligned(4);
172
173 struct amdgim_vf2pf_info_v1 {
174 /* header contains size and version */
175 struct amd_sriov_msg_vf2pf_info_header header;
176 /* driver version */
177 char driver_version[64];
178 /* driver certification, 1=WHQL, 0=None */
179 unsigned int driver_cert;
180 /* guest OS type and version: need a define */
181 unsigned int os_info;
182 /* in the unit of 1M */
183 unsigned int fb_usage;
184 /* guest gfx engine usage percentage */
185 unsigned int gfx_usage;
186 /* guest gfx engine health percentage */
187 unsigned int gfx_health;
188 /* guest compute engine usage percentage */
189 unsigned int compute_usage;
190 /* guest compute engine health percentage */
191 unsigned int compute_health;
192 /* guest vce engine usage percentage. 0xffff means N/A. */
193 unsigned int vce_enc_usage;
194 /* guest vce engine health percentage. 0xffff means N/A. */
195 unsigned int vce_enc_health;
196 /* guest uvd engine usage percentage. 0xffff means N/A. */
197 unsigned int uvd_enc_usage;
198 /* guest uvd engine usage percentage. 0xffff means N/A. */
199 unsigned int uvd_enc_health;
200 unsigned int checksum;
201 } __aligned(4);
202
203 struct amdgim_vf2pf_info_v2 {
204 /* header contains size and version */
205 struct amd_sriov_msg_vf2pf_info_header header;
206 uint32_t checksum;
207 /* driver version */
208 uint8_t driver_version[64];
209 /* driver certification, 1=WHQL, 0=None */
210 uint32_t driver_cert;
211 /* guest OS type and version: need a define */
212 uint32_t os_info;
213 /* in the unit of 1M */
214 uint32_t fb_usage;
215 /* guest gfx engine usage percentage */
216 uint32_t gfx_usage;
217 /* guest gfx engine health percentage */
218 uint32_t gfx_health;
219 /* guest compute engine usage percentage */
220 uint32_t compute_usage;
221 /* guest compute engine health percentage */
222 uint32_t compute_health;
223 /* guest vce engine usage percentage. 0xffff means N/A. */
224 uint32_t vce_enc_usage;
225 /* guest vce engine health percentage. 0xffff means N/A. */
226 uint32_t vce_enc_health;
227 /* guest uvd engine usage percentage. 0xffff means N/A. */
228 uint32_t uvd_enc_usage;
229 /* guest uvd engine usage percentage. 0xffff means N/A. */
230 uint32_t uvd_enc_health;
231 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
232 } __aligned(4);
233
234 struct amdgpu_virt_ras_err_handler_data {
235 /* point to bad page records array */
236 struct eeprom_table_record *bps;
237 /* point to reserved bo array */
238 struct amdgpu_bo **bps_bo;
239 /* the count of entries */
240 int count;
241 /* last reserved entry's index + 1 */
242 int last_reserved;
243 };
244
245 /* GPU virtualization */
246 struct amdgpu_virt {
247 uint32_t caps;
248 struct amdgpu_bo *csa_obj;
249 void *csa_cpu_addr;
250 bool chained_ib_support;
251 uint32_t reg_val_offs;
252 struct amdgpu_irq_src ack_irq;
253 struct amdgpu_irq_src rcv_irq;
254 struct work_struct flr_work;
255 struct amdgpu_mm_table mm_table;
256 const struct amdgpu_virt_ops *ops;
257 struct amdgpu_vf_error_buffer vf_errors;
258 struct amdgpu_virt_fw_reserve fw_reserve;
259 uint32_t gim_feature;
260 uint32_t reg_access_mode;
261 int req_init_data_ver;
262 bool tdr_debug;
263 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
264 bool ras_init_done;
265 uint32_t reg_access;
266
267 /* vf2pf message */
268 struct delayed_work vf2pf_work;
269 uint32_t vf2pf_update_interval_ms;
270 int vf2pf_update_retry_cnt;
271
272 /* multimedia bandwidth config */
273 bool is_mm_bw_enabled;
274 uint32_t decode_max_dimension_pixels;
275 uint32_t decode_max_frame_pixels;
276 uint32_t encode_max_dimension_pixels;
277 uint32_t encode_max_frame_pixels;
278
279 /* the ucode id to signal the autoload */
280 uint32_t autoload_ucode_id;
281
282 struct mutex rlcg_reg_lock;
283
284 union amd_sriov_ras_caps ras_en_caps;
285 union amd_sriov_ras_caps ras_telemetry_en_caps;
286
287 struct ratelimit_state ras_telemetry_rs;
288 struct amd_sriov_ras_telemetry_error_count count_cache;
289 };
290
291 struct amdgpu_video_codec_info;
292
293 #define amdgpu_sriov_enabled(adev) \
294 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
295
296 #define amdgpu_sriov_vf(adev) \
297 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
298
299 #define amdgpu_sriov_bios(adev) \
300 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
301
302 #define amdgpu_sriov_runtime(adev) \
303 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
304
305 #define amdgpu_sriov_fullaccess(adev) \
306 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
307
308 #define amdgpu_sriov_reg_indirect_en(adev) \
309 (amdgpu_sriov_vf((adev)) && \
310 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
311
312 #define amdgpu_sriov_reg_indirect_ih(adev) \
313 (amdgpu_sriov_vf((adev)) && \
314 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
315
316 #define amdgpu_sriov_reg_indirect_mmhub(adev) \
317 (amdgpu_sriov_vf((adev)) && \
318 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
319
320 #define amdgpu_sriov_reg_indirect_gc(adev) \
321 (amdgpu_sriov_vf((adev)) && \
322 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
323
324 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \
325 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
326
327 #define amdgpu_passthrough(adev) \
328 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
329
330 #define amdgpu_sriov_vf_mmio_access_protection(adev) \
331 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
332
333 #define amdgpu_sriov_ras_caps_en(adev) \
334 ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS)
335
336 #define amdgpu_sriov_ras_telemetry_en(adev) \
337 (((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry)
338
339 #define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \
340 (amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk))
341
is_virtual_machine(void)342 static inline bool is_virtual_machine(void)
343 {
344 #if defined(CONFIG_X86)
345 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
346 #elif defined(CONFIG_ARM64)
347 return !is_kernel_in_hyp_mode();
348 #else
349 return false;
350 #endif
351 }
352
353 #define amdgpu_sriov_is_pp_one_vf(adev) \
354 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
355 #define amdgpu_sriov_is_debug(adev) \
356 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
357 #define amdgpu_sriov_is_normal(adev) \
358 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
359 #define amdgpu_sriov_is_av1_support(adev) \
360 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
361 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \
362 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
363 #define amdgpu_sriov_is_mes_info_enable(adev) \
364 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
365 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
366 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
367 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
368 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
369 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
370 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
371 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev);
372 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
373 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
374 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
375 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);
376 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
377 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
378 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
379 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
380 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
381
382 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
383 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
384 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
385
386 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
387
388 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
389 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
390 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
391 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
392 u32 offset, u32 value,
393 u32 acc_flags, u32 hwip, u32 xcc_id);
394 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
395 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
396 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
397 uint32_t ucode_id);
398 void amdgpu_virt_pre_reset(struct amdgpu_device *adev);
399 void amdgpu_virt_post_reset(struct amdgpu_device *adev);
400 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
401 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
402 u32 acc_flags, u32 hwip,
403 bool write, u32 *rlcg_flag);
404 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
405 bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);
406 int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block,
407 struct ras_err_data *err_data);
408 int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev);
409 #endif
410