1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/sound/soc/codecs/tlv320aic32x4.c
4 *
5 * Copyright 2011 Vista Silicon S.L.
6 *
7 * Author: Javier Martin <javier.martin@vista-silicon.com>
8 *
9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
10 */
11
12 #include <linux/cdev.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/of_clk.h>
20 #include <linux/pm.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23
24 #include <sound/core.h>
25 #include <sound/initval.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/tlv.h>
31 #include <sound/tlv320aic32x4.h>
32
33 #include "tlv320aic32x4.h"
34
35 struct aic32x4_priv {
36 struct regmap *regmap;
37 u32 power_cfg;
38 u32 micpga_routing;
39 bool swapdacs;
40 struct gpio_desc *rstn_gpio;
41 const char *mclk_name;
42
43 struct regulator *supply_ldo;
44 struct regulator *supply_iov;
45 struct regulator *supply_dv;
46 struct regulator *supply_av;
47
48 struct aic32x4_setup_data *setup;
49 struct device *dev;
50 enum aic32x4_type type;
51
52 unsigned int fmt;
53 };
54
aic32x4_reset_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)55 static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
56 struct snd_kcontrol *kcontrol, int event)
57 {
58 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
59 u32 adc_reg;
60
61 /*
62 * Workaround: the datasheet does not mention a required programming
63 * sequence but experiments show the ADC needs to be reset after each
64 * capture to avoid audible artifacts.
65 */
66 switch (event) {
67 case SND_SOC_DAPM_POST_PMD:
68 adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
69 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
70 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
71 snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
72 break;
73 }
74 return 0;
75 };
76
mic_bias_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)77 static int mic_bias_event(struct snd_soc_dapm_widget *w,
78 struct snd_kcontrol *kcontrol, int event)
79 {
80 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
81
82 switch (event) {
83 case SND_SOC_DAPM_POST_PMU:
84 /* Change Mic Bias Registor */
85 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
86 AIC32x4_MICBIAS_MASK,
87 AIC32X4_MICBIAS_LDOIN |
88 AIC32X4_MICBIAS_2075V);
89 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
90 break;
91 case SND_SOC_DAPM_PRE_PMD:
92 snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
93 AIC32x4_MICBIAS_MASK, 0);
94 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
95 __func__);
96 break;
97 }
98
99 return 0;
100 }
101
102
aic32x4_get_mfp1_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)103 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
104 struct snd_ctl_elem_value *ucontrol)
105 {
106 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
107 u8 val;
108
109 val = snd_soc_component_read(component, AIC32X4_DINCTL);
110
111 ucontrol->value.integer.value[0] = (val & 0x01);
112
113 return 0;
114 };
115
aic32x4_set_mfp2_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)116 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
117 struct snd_ctl_elem_value *ucontrol)
118 {
119 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
120 u8 val;
121 u8 gpio_check;
122
123 val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
124 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
125 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
126 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
127 __func__);
128 return -EINVAL;
129 }
130
131 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
132 return 0;
133
134 if (ucontrol->value.integer.value[0])
135 val |= ucontrol->value.integer.value[0];
136 else
137 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
138
139 snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
140
141 return 0;
142 };
143
aic32x4_get_mfp3_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)144 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
145 struct snd_ctl_elem_value *ucontrol)
146 {
147 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
148 u8 val;
149
150 val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
151
152 ucontrol->value.integer.value[0] = (val & 0x01);
153
154 return 0;
155 };
156
aic32x4_set_mfp4_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)157 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol)
159 {
160 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
161 u8 val;
162 u8 gpio_check;
163
164 val = snd_soc_component_read(component, AIC32X4_MISOCTL);
165 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
166 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
167 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
168 __func__);
169 return -EINVAL;
170 }
171
172 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
173 return 0;
174
175 if (ucontrol->value.integer.value[0])
176 val |= ucontrol->value.integer.value[0];
177 else
178 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
179
180 snd_soc_component_write(component, AIC32X4_MISOCTL, val);
181
182 return 0;
183 };
184
aic32x4_get_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)185 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
186 struct snd_ctl_elem_value *ucontrol)
187 {
188 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
189 u8 val;
190
191 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
192 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
193
194 return 0;
195 };
196
aic32x4_set_mfp5_gpio(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)197 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
198 struct snd_ctl_elem_value *ucontrol)
199 {
200 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
201 u8 val;
202 u8 gpio_check;
203
204 val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
205 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
206 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
207 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
208 __func__);
209 return -EINVAL;
210 }
211
212 if (ucontrol->value.integer.value[0] == (val & 0x1))
213 return 0;
214
215 if (ucontrol->value.integer.value[0])
216 val |= ucontrol->value.integer.value[0];
217 else
218 val &= 0xfe;
219
220 snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
221
222 return 0;
223 };
224
225 static const struct snd_kcontrol_new aic32x4_mfp1[] = {
226 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
227 };
228
229 static const struct snd_kcontrol_new aic32x4_mfp2[] = {
230 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
231 };
232
233 static const struct snd_kcontrol_new aic32x4_mfp3[] = {
234 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
235 };
236
237 static const struct snd_kcontrol_new aic32x4_mfp4[] = {
238 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
239 };
240
241 static const struct snd_kcontrol_new aic32x4_mfp5[] = {
242 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
243 aic32x4_set_mfp5_gpio),
244 };
245
246 /* 0dB min, 0.5dB steps */
247 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
248 /* -63.5dB min, 0.5dB steps */
249 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
250 /* -6dB min, 1dB steps */
251 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
252 /* -12dB min, 0.5dB steps */
253 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
254 /* -6dB min, 1dB steps */
255 static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
256 static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
257
258 static const char * const lo_cm_text[] = {
259 "Full Chip", "1.65V",
260 };
261
262 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
263
264 static const char * const ptm_text[] = {
265 "P3", "P2", "P1",
266 };
267
268 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
269 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
270
271 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
272 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
273 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
274 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
275 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
276 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
277 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
278 tlv_driver_gain),
279 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
280 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
281 tlv_driver_gain),
282 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
283 AIC32X4_HPRGAIN, 6, 0x01, 1),
284 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
285 AIC32X4_LORGAIN, 6, 0x01, 1),
286 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
287 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
288 AIC32X4_RMICPGAVOL, 7, 0x01, 1),
289
290 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
291 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
292
293 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
294 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
295 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
296 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
297
298 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
299
300 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
301 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
302 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
303 4, 0x07, 0),
304 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
305 0, 0x03, 0),
306 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
307 6, 0x03, 0),
308 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
309 1, 0x1F, 0),
310 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
311 0, 0x7F, 0),
312 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
313 3, 0x1F, 0),
314 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
315 3, 0x1F, 0),
316 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
317 0, 0x1F, 0),
318 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
319 0, 0x0F, 0),
320 };
321
322 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
323 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
324 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
325 };
326
327 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
328 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
329 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
330 };
331
332 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
333 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
334 };
335
336 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
337 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
338 };
339
340 static const char * const resistor_text[] = {
341 "Off", "10 kOhm", "20 kOhm", "40 kOhm",
342 };
343
344 /* Left mixer pins */
345 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
346 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
347 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
348 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
349
350 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
351 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
352 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
353
354 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
355 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
356 };
357 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
358 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
359 };
360 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
361 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
362 };
363 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
364 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
365 };
366 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
367 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
368 };
369 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
370 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
371 };
372 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
373 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
374 };
375
376 /* Right mixer pins */
377 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
378 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
379 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
380 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
381 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
382 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
383 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
384
385 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
386 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
387 };
388 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
389 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
390 };
391 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
392 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
393 };
394 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
395 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
396 };
397 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
398 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
399 };
400 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
401 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
402 };
403 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
404 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
405 };
406
407 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
408 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
409 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
410 &hpl_output_mixer_controls[0],
411 ARRAY_SIZE(hpl_output_mixer_controls)),
412 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
413
414 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
415 &lol_output_mixer_controls[0],
416 ARRAY_SIZE(lol_output_mixer_controls)),
417 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
418
419 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
420 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
421 &hpr_output_mixer_controls[0],
422 ARRAY_SIZE(hpr_output_mixer_controls)),
423 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
424 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
425 &lor_output_mixer_controls[0],
426 ARRAY_SIZE(lor_output_mixer_controls)),
427 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
428
429 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
430 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
431 in1r_to_rmixer_controls),
432 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
433 in2r_to_rmixer_controls),
434 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
435 in3r_to_rmixer_controls),
436 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
437 in2l_to_rmixer_controls),
438 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
439 cmr_to_rmixer_controls),
440 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
441 in1l_to_rmixer_controls),
442 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
443 in3l_to_rmixer_controls),
444
445 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
446 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
447 in1l_to_lmixer_controls),
448 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
449 in2l_to_lmixer_controls),
450 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
451 in3l_to_lmixer_controls),
452 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
453 in1r_to_lmixer_controls),
454 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
455 cml_to_lmixer_controls),
456 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
457 in2r_to_lmixer_controls),
458 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
459 in3r_to_lmixer_controls),
460
461 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
462 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
463
464 SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
465
466 SND_SOC_DAPM_OUTPUT("HPL"),
467 SND_SOC_DAPM_OUTPUT("HPR"),
468 SND_SOC_DAPM_OUTPUT("LOL"),
469 SND_SOC_DAPM_OUTPUT("LOR"),
470 SND_SOC_DAPM_INPUT("IN1_L"),
471 SND_SOC_DAPM_INPUT("IN1_R"),
472 SND_SOC_DAPM_INPUT("IN2_L"),
473 SND_SOC_DAPM_INPUT("IN2_R"),
474 SND_SOC_DAPM_INPUT("IN3_L"),
475 SND_SOC_DAPM_INPUT("IN3_R"),
476 SND_SOC_DAPM_INPUT("CM_L"),
477 SND_SOC_DAPM_INPUT("CM_R"),
478 };
479
480 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
481 /* Left Output */
482 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
483 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
484
485 {"HPL Power", NULL, "HPL Output Mixer"},
486 {"HPL", NULL, "HPL Power"},
487
488 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
489
490 {"LOL Power", NULL, "LOL Output Mixer"},
491 {"LOL", NULL, "LOL Power"},
492
493 /* Right Output */
494 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
495 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
496
497 {"HPR Power", NULL, "HPR Output Mixer"},
498 {"HPR", NULL, "HPR Power"},
499
500 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
501
502 {"LOR Power", NULL, "LOR Output Mixer"},
503 {"LOR", NULL, "LOR Power"},
504
505 /* Right Input */
506 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
507 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
508 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
509 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
510
511 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
512 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
513 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
514 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
515
516 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
517 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
518 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
519 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
520
521 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
522 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
523 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
524 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
525
526 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
527 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
528 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
529 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
530
531 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
532 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
533 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
534 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
535
536 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
537 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
538 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
539 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
540
541 /* Left Input */
542 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
543 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
544 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
545 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
546
547 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
548 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
549 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
550 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
551
552 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
553 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
554 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
555 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
556
557 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
558 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
559 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
560 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
561
562 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
563 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
564 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
565 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
566
567 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
568 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
569 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
570 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
571
572 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
573 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
574 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
575 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
576 };
577
578 static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
579 {
580 .selector_reg = 0,
581 .selector_mask = 0xff,
582 .window_start = 0,
583 .window_len = 128,
584 .range_min = 0,
585 .range_max = AIC32X4_REFPOWERUP,
586 },
587 };
588
589 const struct regmap_config aic32x4_regmap_config = {
590 .max_register = AIC32X4_REFPOWERUP,
591 .ranges = aic32x4_regmap_pages,
592 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
593 };
594 EXPORT_SYMBOL(aic32x4_regmap_config);
595
aic32x4_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)596 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
597 int clk_id, unsigned int freq, int dir)
598 {
599 struct snd_soc_component *component = codec_dai->component;
600 struct clk *mclk;
601 struct clk *pll;
602
603 pll = devm_clk_get(component->dev, "pll");
604 if (IS_ERR(pll))
605 return PTR_ERR(pll);
606
607 mclk = clk_get_parent(pll);
608
609 return clk_set_rate(mclk, freq);
610 }
611
aic32x4_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)612 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
613 {
614 struct snd_soc_component *component = codec_dai->component;
615 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
616 u8 iface_reg_1 = 0;
617 u8 iface_reg_2 = 0;
618 u8 iface_reg_3 = 0;
619
620 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
621 case SND_SOC_DAIFMT_CBP_CFP:
622 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
623 break;
624 case SND_SOC_DAIFMT_CBC_CFC:
625 break;
626 default:
627 printk(KERN_ERR "aic32x4: invalid clock provider\n");
628 return -EINVAL;
629 }
630
631 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
632 case SND_SOC_DAIFMT_I2S:
633 break;
634 case SND_SOC_DAIFMT_DSP_A:
635 iface_reg_1 |= (AIC32X4_DSP_MODE <<
636 AIC32X4_IFACE1_DATATYPE_SHIFT);
637 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
638 iface_reg_2 = 0x01; /* add offset 1 */
639 break;
640 case SND_SOC_DAIFMT_DSP_B:
641 iface_reg_1 |= (AIC32X4_DSP_MODE <<
642 AIC32X4_IFACE1_DATATYPE_SHIFT);
643 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
644 break;
645 case SND_SOC_DAIFMT_RIGHT_J:
646 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
647 AIC32X4_IFACE1_DATATYPE_SHIFT);
648 break;
649 case SND_SOC_DAIFMT_LEFT_J:
650 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
651 AIC32X4_IFACE1_DATATYPE_SHIFT);
652 break;
653 default:
654 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
655 return -EINVAL;
656 }
657
658 aic32x4->fmt = fmt;
659
660 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
661 AIC32X4_IFACE1_DATATYPE_MASK |
662 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
663 snd_soc_component_update_bits(component, AIC32X4_IFACE2,
664 AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
665 snd_soc_component_update_bits(component, AIC32X4_IFACE3,
666 AIC32X4_BCLKINV_MASK, iface_reg_3);
667
668 return 0;
669 }
670
aic32x4_set_aosr(struct snd_soc_component * component,u8 aosr)671 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
672 {
673 return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
674 }
675
aic32x4_set_dosr(struct snd_soc_component * component,u16 dosr)676 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
677 {
678 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
679 snd_soc_component_write(component, AIC32X4_DOSRLSB,
680 (dosr & 0xff));
681
682 return 0;
683 }
684
aic32x4_set_processing_blocks(struct snd_soc_component * component,u8 r_block,u8 p_block)685 static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
686 u8 r_block, u8 p_block)
687 {
688 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
689
690 if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
691 if (r_block || p_block > 3)
692 return -EINVAL;
693
694 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
695 } else { /* AIC32x4 */
696 if (r_block > 18 || p_block > 25)
697 return -EINVAL;
698
699 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
700 snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
701 }
702
703 return 0;
704 }
705
aic32x4_setup_clocks(struct snd_soc_component * component,unsigned int sample_rate,unsigned int channels,unsigned int bit_depth)706 static int aic32x4_setup_clocks(struct snd_soc_component *component,
707 unsigned int sample_rate, unsigned int channels,
708 unsigned int bit_depth)
709 {
710 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
711 u8 aosr;
712 u16 dosr;
713 u8 adc_resource_class, dac_resource_class;
714 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
715 u8 dosr_increment;
716 u16 max_dosr, min_dosr;
717 unsigned long adc_clock_rate, dac_clock_rate;
718 int ret;
719
720 static struct clk_bulk_data clocks[] = {
721 { .id = "pll" },
722 { .id = "nadc" },
723 { .id = "madc" },
724 { .id = "ndac" },
725 { .id = "mdac" },
726 { .id = "bdiv" },
727 };
728 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
729 if (ret)
730 return ret;
731
732 if (sample_rate <= 48000) {
733 aosr = 128;
734 adc_resource_class = 6;
735 dac_resource_class = 8;
736 dosr_increment = 8;
737 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
738 aic32x4_set_processing_blocks(component, 0, 1);
739 else
740 aic32x4_set_processing_blocks(component, 1, 1);
741 } else if (sample_rate <= 96000) {
742 aosr = 64;
743 adc_resource_class = 6;
744 dac_resource_class = 8;
745 dosr_increment = 4;
746 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
747 aic32x4_set_processing_blocks(component, 0, 1);
748 else
749 aic32x4_set_processing_blocks(component, 1, 9);
750 } else if (sample_rate == 192000) {
751 aosr = 32;
752 adc_resource_class = 3;
753 dac_resource_class = 4;
754 dosr_increment = 2;
755 if (aic32x4->type == AIC32X4_TYPE_TAS2505)
756 aic32x4_set_processing_blocks(component, 0, 1);
757 else
758 aic32x4_set_processing_blocks(component, 13, 19);
759 } else {
760 dev_err(component->dev, "Sampling rate not supported\n");
761 return -EINVAL;
762 }
763
764 /* PCM over I2S is always 2-channel */
765 if ((aic32x4->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S)
766 channels = 2;
767
768 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
769 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
770 dosr_increment;
771 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
772 dosr_increment;
773 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
774
775 for (nadc = max_nadc; nadc > 0; --nadc) {
776 adc_clock_rate = nadc * madc * aosr * sample_rate;
777 for (dosr = max_dosr; dosr >= min_dosr;
778 dosr -= dosr_increment) {
779 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
780 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
781 (min_mdac * dosr * sample_rate);
782 for (mdac = min_mdac; mdac <= 128; ++mdac) {
783 for (ndac = max_ndac; ndac > 0; --ndac) {
784 dac_clock_rate = ndac * mdac * dosr *
785 sample_rate;
786 if (dac_clock_rate == adc_clock_rate) {
787 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
788 continue;
789
790 clk_set_rate(clocks[0].clk,
791 dac_clock_rate);
792
793 clk_set_rate(clocks[1].clk,
794 sample_rate * aosr *
795 madc);
796 clk_set_rate(clocks[2].clk,
797 sample_rate * aosr);
798 aic32x4_set_aosr(component,
799 aosr);
800
801 clk_set_rate(clocks[3].clk,
802 sample_rate * dosr *
803 mdac);
804 clk_set_rate(clocks[4].clk,
805 sample_rate * dosr);
806 aic32x4_set_dosr(component,
807 dosr);
808
809 clk_set_rate(clocks[5].clk,
810 sample_rate * channels *
811 bit_depth);
812
813 return 0;
814 }
815 }
816 }
817 }
818 }
819
820 dev_err(component->dev,
821 "Could not set clocks to support sample rate.\n");
822 return -EINVAL;
823 }
824
aic32x4_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)825 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
826 struct snd_pcm_hw_params *params,
827 struct snd_soc_dai *dai)
828 {
829 struct snd_soc_component *component = dai->component;
830 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
831 u8 iface1_reg = 0;
832 u8 dacsetup_reg = 0;
833
834 aic32x4_setup_clocks(component, params_rate(params),
835 params_channels(params),
836 params_physical_width(params));
837
838 switch (params_physical_width(params)) {
839 case 16:
840 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
841 AIC32X4_IFACE1_DATALEN_SHIFT);
842 break;
843 case 20:
844 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
845 AIC32X4_IFACE1_DATALEN_SHIFT);
846 break;
847 case 24:
848 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
849 AIC32X4_IFACE1_DATALEN_SHIFT);
850 break;
851 case 32:
852 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
853 AIC32X4_IFACE1_DATALEN_SHIFT);
854 break;
855 }
856 snd_soc_component_update_bits(component, AIC32X4_IFACE1,
857 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
858
859 if (params_channels(params) == 1) {
860 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
861 } else {
862 if (aic32x4->swapdacs)
863 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
864 else
865 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
866 }
867 snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
868 AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
869
870 return 0;
871 }
872
aic32x4_mute(struct snd_soc_dai * dai,int mute,int direction)873 static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
874 {
875 struct snd_soc_component *component = dai->component;
876
877 snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
878 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
879
880 return 0;
881 }
882
aic32x4_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)883 static int aic32x4_set_bias_level(struct snd_soc_component *component,
884 enum snd_soc_bias_level level)
885 {
886 int ret;
887
888 static struct clk_bulk_data clocks[] = {
889 { .id = "madc" },
890 { .id = "mdac" },
891 { .id = "bdiv" },
892 };
893
894 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
895 if (ret)
896 return ret;
897
898 switch (level) {
899 case SND_SOC_BIAS_ON:
900 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
901 if (ret) {
902 dev_err(component->dev, "Failed to enable clocks\n");
903 return ret;
904 }
905 break;
906 case SND_SOC_BIAS_PREPARE:
907 break;
908 case SND_SOC_BIAS_STANDBY:
909 /* Initial cold start */
910 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
911 break;
912
913 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
914 break;
915 case SND_SOC_BIAS_OFF:
916 break;
917 }
918 return 0;
919 }
920
921 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000
922 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
923 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
924 | SNDRV_PCM_FMTBIT_S32_LE)
925
926 static const struct snd_soc_dai_ops aic32x4_ops = {
927 .hw_params = aic32x4_hw_params,
928 .mute_stream = aic32x4_mute,
929 .set_fmt = aic32x4_set_dai_fmt,
930 .set_sysclk = aic32x4_set_dai_sysclk,
931 .no_capture_mute = 1,
932 };
933
934 static struct snd_soc_dai_driver aic32x4_dai = {
935 .name = "tlv320aic32x4-hifi",
936 .playback = {
937 .stream_name = "Playback",
938 .channels_min = 1,
939 .channels_max = 2,
940 .rates = AIC32X4_RATES,
941 .formats = AIC32X4_FORMATS,},
942 .capture = {
943 .stream_name = "Capture",
944 .channels_min = 1,
945 .channels_max = 8,
946 .rates = AIC32X4_RATES,
947 .formats = AIC32X4_FORMATS,},
948 .ops = &aic32x4_ops,
949 .symmetric_rate = 1,
950 };
951
aic32x4_setup_gpios(struct snd_soc_component * component)952 static void aic32x4_setup_gpios(struct snd_soc_component *component)
953 {
954 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
955
956 /* setup GPIO functions */
957 /* MFP1 */
958 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
959 snd_soc_component_write(component, AIC32X4_DINCTL,
960 aic32x4->setup->gpio_func[0]);
961 snd_soc_add_component_controls(component, aic32x4_mfp1,
962 ARRAY_SIZE(aic32x4_mfp1));
963 }
964
965 /* MFP2 */
966 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
967 snd_soc_component_write(component, AIC32X4_DOUTCTL,
968 aic32x4->setup->gpio_func[1]);
969 snd_soc_add_component_controls(component, aic32x4_mfp2,
970 ARRAY_SIZE(aic32x4_mfp2));
971 }
972
973 /* MFP3 */
974 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
975 snd_soc_component_write(component, AIC32X4_SCLKCTL,
976 aic32x4->setup->gpio_func[2]);
977 snd_soc_add_component_controls(component, aic32x4_mfp3,
978 ARRAY_SIZE(aic32x4_mfp3));
979 }
980
981 /* MFP4 */
982 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
983 snd_soc_component_write(component, AIC32X4_MISOCTL,
984 aic32x4->setup->gpio_func[3]);
985 snd_soc_add_component_controls(component, aic32x4_mfp4,
986 ARRAY_SIZE(aic32x4_mfp4));
987 }
988
989 /* MFP5 */
990 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
991 snd_soc_component_write(component, AIC32X4_GPIOCTL,
992 aic32x4->setup->gpio_func[4]);
993 snd_soc_add_component_controls(component, aic32x4_mfp5,
994 ARRAY_SIZE(aic32x4_mfp5));
995 }
996 }
997
aic32x4_component_probe(struct snd_soc_component * component)998 static int aic32x4_component_probe(struct snd_soc_component *component)
999 {
1000 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1001 u32 tmp_reg;
1002 int ret;
1003
1004 static struct clk_bulk_data clocks[] = {
1005 { .id = "codec_clkin" },
1006 { .id = "pll" },
1007 { .id = "bdiv" },
1008 { .id = "mdac" },
1009 };
1010
1011 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1012 if (ret)
1013 return ret;
1014
1015 if (aic32x4->setup)
1016 aic32x4_setup_gpios(component);
1017
1018 clk_set_parent(clocks[0].clk, clocks[1].clk);
1019 clk_set_parent(clocks[2].clk, clocks[3].clk);
1020
1021 /* Power platform configuration */
1022 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1023 snd_soc_component_write(component, AIC32X4_MICBIAS,
1024 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1025 }
1026 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1027 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1028
1029 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1030 AIC32X4_LDOCTLEN : 0;
1031 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1032
1033 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1034 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1035 tmp_reg |= AIC32X4_LDOIN_18_36;
1036 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1037 tmp_reg |= AIC32X4_LDOIN2HP;
1038 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1039
1040 /* Mic PGA routing */
1041 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1042 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1043 AIC32X4_LMICPGANIN_IN2R_10K);
1044 else
1045 snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1046 AIC32X4_LMICPGANIN_CM1L_10K);
1047 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1048 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1049 AIC32X4_RMICPGANIN_IN1L_10K);
1050 else
1051 snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1052 AIC32X4_RMICPGANIN_CM1R_10K);
1053
1054 /*
1055 * Workaround: for an unknown reason, the ADC needs to be powered up
1056 * and down for the first capture to work properly. It seems related to
1057 * a HW BUG or some kind of behavior not documented in the datasheet.
1058 */
1059 tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1060 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1061 AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1062 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1063
1064 /*
1065 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1066 * before using the analog circuits.
1067 */
1068 snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1069 AIC32X4_REFPOWERUP_40MS);
1070 msleep(40);
1071
1072 return 0;
1073 }
1074
aic32x4_of_xlate_dai_id(struct snd_soc_component * component,struct device_node * endpoint)1075 static int aic32x4_of_xlate_dai_id(struct snd_soc_component *component,
1076 struct device_node *endpoint)
1077 {
1078 /* return dai id 0, whatever the endpoint index */
1079 return 0;
1080 }
1081
1082 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1083 .probe = aic32x4_component_probe,
1084 .set_bias_level = aic32x4_set_bias_level,
1085 .controls = aic32x4_snd_controls,
1086 .num_controls = ARRAY_SIZE(aic32x4_snd_controls),
1087 .dapm_widgets = aic32x4_dapm_widgets,
1088 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets),
1089 .dapm_routes = aic32x4_dapm_routes,
1090 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes),
1091 .of_xlate_dai_id = aic32x4_of_xlate_dai_id,
1092 .suspend_bias_off = 1,
1093 .idle_bias_on = 1,
1094 .use_pmdown_time = 1,
1095 .endianness = 1,
1096 };
1097
1098 static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
1099 SOC_SINGLE_S8_TLV("PCM Playback Volume",
1100 AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1101 SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
1102
1103 SOC_SINGLE_TLV("HP Driver Gain Volume",
1104 AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
1105 SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
1106
1107 SOC_SINGLE_TLV("Speaker Driver Playback Volume",
1108 TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
1109 SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
1110 TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1111
1112 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1113 };
1114
1115 static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1116 SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1117 };
1118
1119 static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1120 SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1121 SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1122 &hp_output_mixer_controls[0],
1123 ARRAY_SIZE(hp_output_mixer_controls)),
1124 SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1125
1126 SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1127
1128 SND_SOC_DAPM_OUTPUT("HP"),
1129 SND_SOC_DAPM_OUTPUT("Speaker"),
1130 };
1131
1132 static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1133 /* Left Output */
1134 {"HP Output Mixer", "DAC Switch", "DAC"},
1135
1136 {"HP Power", NULL, "HP Output Mixer"},
1137 {"HP", NULL, "HP Power"},
1138
1139 {"Speaker Driver", NULL, "DAC"},
1140 {"Speaker", NULL, "Speaker Driver"},
1141 };
1142
1143 static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1144 .name = "tas2505-hifi",
1145 .playback = {
1146 .stream_name = "Playback",
1147 .channels_min = 1,
1148 .channels_max = 2,
1149 .rates = SNDRV_PCM_RATE_8000_96000,
1150 .formats = AIC32X4_FORMATS,},
1151 .ops = &aic32x4_ops,
1152 .symmetric_rate = 1,
1153 };
1154
aic32x4_tas2505_component_probe(struct snd_soc_component * component)1155 static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1156 {
1157 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1158 u32 tmp_reg;
1159 int ret;
1160
1161 static struct clk_bulk_data clocks[] = {
1162 { .id = "codec_clkin" },
1163 { .id = "pll" },
1164 { .id = "bdiv" },
1165 { .id = "mdac" },
1166 };
1167
1168 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1169 if (ret)
1170 return ret;
1171
1172 if (aic32x4->setup)
1173 aic32x4_setup_gpios(component);
1174
1175 clk_set_parent(clocks[0].clk, clocks[1].clk);
1176 clk_set_parent(clocks[2].clk, clocks[3].clk);
1177
1178 /* Power platform configuration */
1179 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1180 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1181
1182 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1183 AIC32X4_LDOCTLEN : 0;
1184 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1185
1186 tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1187 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1188 tmp_reg |= AIC32X4_LDOIN_18_36;
1189 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1190 tmp_reg |= AIC32X4_LDOIN2HP;
1191 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1192
1193 /*
1194 * Enable the fast charging feature and ensure the needed 40ms ellapsed
1195 * before using the analog circuits.
1196 */
1197 snd_soc_component_write(component, TAS2505_REFPOWERUP,
1198 AIC32X4_REFPOWERUP_40MS);
1199 msleep(40);
1200
1201 return 0;
1202 }
1203
1204 static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1205 .probe = aic32x4_tas2505_component_probe,
1206 .set_bias_level = aic32x4_set_bias_level,
1207 .controls = aic32x4_tas2505_snd_controls,
1208 .num_controls = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1209 .dapm_widgets = aic32x4_tas2505_dapm_widgets,
1210 .num_dapm_widgets = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1211 .dapm_routes = aic32x4_tas2505_dapm_routes,
1212 .num_dapm_routes = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1213 .of_xlate_dai_id = aic32x4_of_xlate_dai_id,
1214 .suspend_bias_off = 1,
1215 .idle_bias_on = 1,
1216 .use_pmdown_time = 1,
1217 .endianness = 1,
1218 };
1219
aic32x4_parse_dt(struct aic32x4_priv * aic32x4,struct device_node * np)1220 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1221 struct device_node *np)
1222 {
1223 struct aic32x4_setup_data *aic32x4_setup;
1224 int ret;
1225
1226 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1227 GFP_KERNEL);
1228 if (!aic32x4_setup)
1229 return -ENOMEM;
1230
1231 ret = of_property_match_string(np, "clock-names", "mclk");
1232 if (ret < 0)
1233 return -EINVAL;
1234 aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1235
1236 aic32x4->swapdacs = false;
1237 aic32x4->micpga_routing = 0;
1238 /* Assert reset using GPIOD_OUT_HIGH, because reset is GPIO_ACTIVE_LOW */
1239 aic32x4->rstn_gpio = devm_gpiod_get_optional(aic32x4->dev, "reset", GPIOD_OUT_HIGH);
1240 if (IS_ERR(aic32x4->rstn_gpio)) {
1241 return dev_err_probe(aic32x4->dev, PTR_ERR(aic32x4->rstn_gpio),
1242 "Failed to get reset gpio\n");
1243 } else {
1244 gpiod_set_consumer_name(aic32x4->rstn_gpio, "tlv320aic32x4_rstn");
1245 }
1246
1247 if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1248 aic32x4_setup->gpio_func, 5) >= 0)
1249 aic32x4->setup = aic32x4_setup;
1250 return 0;
1251 }
1252
aic32x4_disable_regulators(struct aic32x4_priv * aic32x4)1253 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1254 {
1255 regulator_disable(aic32x4->supply_iov);
1256
1257 if (!IS_ERR(aic32x4->supply_ldo))
1258 regulator_disable(aic32x4->supply_ldo);
1259
1260 if (!IS_ERR(aic32x4->supply_dv))
1261 regulator_disable(aic32x4->supply_dv);
1262
1263 if (!IS_ERR(aic32x4->supply_av))
1264 regulator_disable(aic32x4->supply_av);
1265 }
1266
aic32x4_setup_regulators(struct device * dev,struct aic32x4_priv * aic32x4)1267 static int aic32x4_setup_regulators(struct device *dev,
1268 struct aic32x4_priv *aic32x4)
1269 {
1270 int ret = 0;
1271
1272 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1273 aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1274 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1275 aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1276
1277 /* Check if the regulator requirements are fulfilled */
1278
1279 if (IS_ERR(aic32x4->supply_iov)) {
1280 dev_err(dev, "Missing supply 'iov'\n");
1281 return PTR_ERR(aic32x4->supply_iov);
1282 }
1283
1284 if (IS_ERR(aic32x4->supply_ldo)) {
1285 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1286 return -EPROBE_DEFER;
1287
1288 if (IS_ERR(aic32x4->supply_dv)) {
1289 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1290 return PTR_ERR(aic32x4->supply_dv);
1291 }
1292 if (IS_ERR(aic32x4->supply_av)) {
1293 dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1294 return PTR_ERR(aic32x4->supply_av);
1295 }
1296 } else {
1297 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1298 return -EPROBE_DEFER;
1299 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1300 return -EPROBE_DEFER;
1301 }
1302
1303 ret = regulator_enable(aic32x4->supply_iov);
1304 if (ret) {
1305 dev_err(dev, "Failed to enable regulator iov\n");
1306 return ret;
1307 }
1308
1309 if (!IS_ERR(aic32x4->supply_ldo)) {
1310 ret = regulator_enable(aic32x4->supply_ldo);
1311 if (ret) {
1312 dev_err(dev, "Failed to enable regulator ldo\n");
1313 goto error_ldo;
1314 }
1315 }
1316
1317 if (!IS_ERR(aic32x4->supply_dv)) {
1318 ret = regulator_enable(aic32x4->supply_dv);
1319 if (ret) {
1320 dev_err(dev, "Failed to enable regulator dv\n");
1321 goto error_dv;
1322 }
1323 }
1324
1325 if (!IS_ERR(aic32x4->supply_av)) {
1326 ret = regulator_enable(aic32x4->supply_av);
1327 if (ret) {
1328 dev_err(dev, "Failed to enable regulator av\n");
1329 goto error_av;
1330 }
1331 }
1332
1333 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1334 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1335
1336 return 0;
1337
1338 error_av:
1339 if (!IS_ERR(aic32x4->supply_dv))
1340 regulator_disable(aic32x4->supply_dv);
1341
1342 error_dv:
1343 if (!IS_ERR(aic32x4->supply_ldo))
1344 regulator_disable(aic32x4->supply_ldo);
1345
1346 error_ldo:
1347 regulator_disable(aic32x4->supply_iov);
1348 return ret;
1349 }
1350
aic32x4_probe(struct device * dev,struct regmap * regmap,enum aic32x4_type type)1351 int aic32x4_probe(struct device *dev, struct regmap *regmap,
1352 enum aic32x4_type type)
1353 {
1354 struct aic32x4_priv *aic32x4;
1355 struct device_node *np = dev->of_node;
1356 int ret;
1357
1358 if (IS_ERR(regmap))
1359 return PTR_ERR(regmap);
1360
1361 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1362 GFP_KERNEL);
1363 if (aic32x4 == NULL)
1364 return -ENOMEM;
1365
1366 aic32x4->dev = dev;
1367 aic32x4->type = type;
1368
1369 dev_set_drvdata(dev, aic32x4);
1370
1371 if (np) {
1372 ret = aic32x4_parse_dt(aic32x4, np);
1373 if (ret) {
1374 dev_err(dev, "Failed to parse DT node\n");
1375 return ret;
1376 }
1377 } else {
1378 aic32x4->power_cfg = 0;
1379 aic32x4->swapdacs = false;
1380 aic32x4->micpga_routing = 0;
1381 aic32x4->rstn_gpio = NULL;
1382 aic32x4->mclk_name = "mclk";
1383 }
1384
1385 ret = aic32x4_setup_regulators(dev, aic32x4);
1386 if (ret) {
1387 dev_err(dev, "Failed to setup regulators\n");
1388 return ret;
1389 }
1390
1391 if (aic32x4->rstn_gpio) {
1392 ndelay(10);
1393 /* deassert reset */
1394 gpiod_set_value_cansleep(aic32x4->rstn_gpio, 0);
1395 mdelay(1);
1396 }
1397
1398 ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1399 if (ret)
1400 goto err_disable_regulators;
1401
1402 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1403 if (ret)
1404 goto err_disable_regulators;
1405
1406 switch (aic32x4->type) {
1407 case AIC32X4_TYPE_TAS2505:
1408 ret = devm_snd_soc_register_component(dev,
1409 &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1410 break;
1411 default:
1412 ret = devm_snd_soc_register_component(dev,
1413 &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1414 }
1415
1416 if (ret) {
1417 dev_err(dev, "Failed to register component\n");
1418 goto err_disable_regulators;
1419 }
1420
1421 return 0;
1422
1423 err_disable_regulators:
1424 aic32x4_disable_regulators(aic32x4);
1425
1426 return ret;
1427 }
1428 EXPORT_SYMBOL(aic32x4_probe);
1429
aic32x4_remove(struct device * dev)1430 void aic32x4_remove(struct device *dev)
1431 {
1432 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1433
1434 aic32x4_disable_regulators(aic32x4);
1435 }
1436 EXPORT_SYMBOL(aic32x4_remove);
1437
1438 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1439 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1440 MODULE_LICENSE("GPL");
1441