1 /*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23
24 #include "ah_eeprom_v3.h"
25
26 #include "ar5212/ar5212.h"
27 #include "ar5212/ar5212reg.h"
28 #include "ar5212/ar5212phy.h"
29
30 #define AH_5212_5111
31 #include "ar5212/ar5212.ini"
32
33 #define N(a) (sizeof(a)/sizeof(a[0]))
34
35 struct ar5111State {
36 RF_HAL_FUNCS base; /* public state, must be first */
37 uint16_t pcdacTable[PWR_TABLE_SIZE];
38
39 uint32_t Bank0Data[N(ar5212Bank0_5111)];
40 uint32_t Bank1Data[N(ar5212Bank1_5111)];
41 uint32_t Bank2Data[N(ar5212Bank2_5111)];
42 uint32_t Bank3Data[N(ar5212Bank3_5111)];
43 uint32_t Bank6Data[N(ar5212Bank6_5111)];
44 uint32_t Bank7Data[N(ar5212Bank7_5111)];
45 };
46 #define AR5111(ah) ((struct ar5111State *) AH5212(ah)->ah_rfHal)
47
48 static uint16_t ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
49 const PCDACS_EEPROM *pSrcStruct);
50 static HAL_BOOL ar5212FindValueInList(uint16_t channel, uint16_t pcdacValue,
51 const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue);
52 static void ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
53 const PCDACS_EEPROM *pSrcStruct,
54 uint16_t *pLowerPcdac, uint16_t *pUpperPcdac);
55
56 extern void ar5212GetLowerUpperValues(uint16_t value,
57 const uint16_t *pList, uint16_t listSize,
58 uint16_t *pLowerValue, uint16_t *pUpperValue);
59 extern void ar5212ModifyRfBuffer(uint32_t *rfBuf, uint32_t reg32,
60 uint32_t numBits, uint32_t firstBit, uint32_t column);
61
62 static void
ar5111WriteRegs(struct ath_hal * ah,u_int modesIndex,u_int freqIndex,int writes)63 ar5111WriteRegs(struct ath_hal *ah, u_int modesIndex, u_int freqIndex,
64 int writes)
65 {
66 HAL_INI_WRITE_ARRAY(ah, ar5212Modes_5111, modesIndex, writes);
67 HAL_INI_WRITE_ARRAY(ah, ar5212Common_5111, 1, writes);
68 HAL_INI_WRITE_ARRAY(ah, ar5212BB_RfGain_5111, freqIndex, writes);
69 }
70
71 /*
72 * Take the MHz channel value and set the Channel value
73 *
74 * ASSUMES: Writes enabled to analog bus
75 */
76 static HAL_BOOL
ar5111SetChannel(struct ath_hal * ah,const struct ieee80211_channel * chan)77 ar5111SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
78 {
79 #define CI_2GHZ_INDEX_CORRECTION 19
80 uint16_t freq = ath_hal_gethwchannel(ah, chan);
81 uint32_t refClk, reg32, data2111;
82 int16_t chan5111, chanIEEE;
83
84 /*
85 * Structure to hold 11b tuning information for 5111/2111
86 * 16 MHz mode, divider ratio = 198 = NP+S. N=16, S=4 or 6, P=12
87 */
88 typedef struct {
89 uint32_t refClkSel; /* reference clock, 1 for 16 MHz */
90 uint32_t channelSelect; /* P[7:4]S[3:0] bits */
91 uint16_t channel5111; /* 11a channel for 5111 */
92 } CHAN_INFO_2GHZ;
93
94 static const CHAN_INFO_2GHZ chan2GHzData[] = {
95 { 1, 0x46, 96 }, /* 2312 -19 */
96 { 1, 0x46, 97 }, /* 2317 -18 */
97 { 1, 0x46, 98 }, /* 2322 -17 */
98 { 1, 0x46, 99 }, /* 2327 -16 */
99 { 1, 0x46, 100 }, /* 2332 -15 */
100 { 1, 0x46, 101 }, /* 2337 -14 */
101 { 1, 0x46, 102 }, /* 2342 -13 */
102 { 1, 0x46, 103 }, /* 2347 -12 */
103 { 1, 0x46, 104 }, /* 2352 -11 */
104 { 1, 0x46, 105 }, /* 2357 -10 */
105 { 1, 0x46, 106 }, /* 2362 -9 */
106 { 1, 0x46, 107 }, /* 2367 -8 */
107 { 1, 0x46, 108 }, /* 2372 -7 */
108 /* index -6 to 0 are pad to make this a nolookup table */
109 { 1, 0x46, 116 }, /* -6 */
110 { 1, 0x46, 116 }, /* -5 */
111 { 1, 0x46, 116 }, /* -4 */
112 { 1, 0x46, 116 }, /* -3 */
113 { 1, 0x46, 116 }, /* -2 */
114 { 1, 0x46, 116 }, /* -1 */
115 { 1, 0x46, 116 }, /* 0 */
116 { 1, 0x46, 116 }, /* 2412 1 */
117 { 1, 0x46, 117 }, /* 2417 2 */
118 { 1, 0x46, 118 }, /* 2422 3 */
119 { 1, 0x46, 119 }, /* 2427 4 */
120 { 1, 0x46, 120 }, /* 2432 5 */
121 { 1, 0x46, 121 }, /* 2437 6 */
122 { 1, 0x46, 122 }, /* 2442 7 */
123 { 1, 0x46, 123 }, /* 2447 8 */
124 { 1, 0x46, 124 }, /* 2452 9 */
125 { 1, 0x46, 125 }, /* 2457 10 */
126 { 1, 0x46, 126 }, /* 2462 11 */
127 { 1, 0x46, 127 }, /* 2467 12 */
128 { 1, 0x46, 128 }, /* 2472 13 */
129 { 1, 0x44, 124 }, /* 2484 14 */
130 { 1, 0x46, 136 }, /* 2512 15 */
131 { 1, 0x46, 140 }, /* 2532 16 */
132 { 1, 0x46, 144 }, /* 2552 17 */
133 { 1, 0x46, 148 }, /* 2572 18 */
134 { 1, 0x46, 152 }, /* 2592 19 */
135 { 1, 0x46, 156 }, /* 2612 20 */
136 { 1, 0x46, 160 }, /* 2632 21 */
137 { 1, 0x46, 164 }, /* 2652 22 */
138 { 1, 0x46, 168 }, /* 2672 23 */
139 { 1, 0x46, 172 }, /* 2692 24 */
140 { 1, 0x46, 176 }, /* 2712 25 */
141 { 1, 0x46, 180 } /* 2732 26 */
142 };
143
144 OS_MARK(ah, AH_MARK_SETCHANNEL, freq);
145
146 chanIEEE = chan->ic_ieee;
147 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
148 const CHAN_INFO_2GHZ* ci =
149 &chan2GHzData[chanIEEE + CI_2GHZ_INDEX_CORRECTION];
150 uint32_t txctl;
151
152 data2111 = ((ath_hal_reverseBits(ci->channelSelect, 8) & 0xff)
153 << 5)
154 | (ci->refClkSel << 4);
155 chan5111 = ci->channel5111;
156 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
157 if (freq == 2484) {
158 /* Enable channel spreading for channel 14 */
159 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
160 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
161 } else {
162 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
163 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
164 }
165 } else {
166 chan5111 = chanIEEE; /* no conversion needed */
167 data2111 = 0;
168 }
169
170 /* Rest of the code is common for 5 GHz and 2.4 GHz. */
171 if (chan5111 >= 145 || (chan5111 & 0x1)) {
172 reg32 = ath_hal_reverseBits(chan5111 - 24, 8) & 0xff;
173 refClk = 1;
174 } else {
175 reg32 = ath_hal_reverseBits(((chan5111 - 24)/2), 8) & 0xff;
176 refClk = 0;
177 }
178
179 reg32 = (reg32 << 2) | (refClk << 1) | (1 << 10) | 0x1;
180 OS_REG_WRITE(ah, AR_PHY(0x27), ((data2111 & 0xff) << 8) | (reg32 & 0xff));
181 reg32 >>= 8;
182 OS_REG_WRITE(ah, AR_PHY(0x34), (data2111 & 0xff00) | (reg32 & 0xff));
183
184 AH_PRIVATE(ah)->ah_curchan = chan;
185 return AH_TRUE;
186 #undef CI_2GHZ_INDEX_CORRECTION
187 }
188
189 /*
190 * Return a reference to the requested RF Bank.
191 */
192 static uint32_t *
ar5111GetRfBank(struct ath_hal * ah,int bank)193 ar5111GetRfBank(struct ath_hal *ah, int bank)
194 {
195 struct ar5111State *priv = AR5111(ah);
196
197 HALASSERT(priv != AH_NULL);
198 switch (bank) {
199 case 0: return priv->Bank0Data;
200 case 1: return priv->Bank1Data;
201 case 2: return priv->Bank2Data;
202 case 3: return priv->Bank3Data;
203 case 6: return priv->Bank6Data;
204 case 7: return priv->Bank7Data;
205 }
206 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown RF Bank %d requested\n",
207 __func__, bank);
208 return AH_NULL;
209 }
210
211 /*
212 * Reads EEPROM header info from device structure and programs
213 * all rf registers
214 *
215 * REQUIRES: Access to the analog rf device
216 */
217 static HAL_BOOL
ar5111SetRfRegs(struct ath_hal * ah,const struct ieee80211_channel * chan,uint16_t modesIndex,uint16_t * rfXpdGain)218 ar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan,
219 uint16_t modesIndex, uint16_t *rfXpdGain)
220 {
221 uint16_t freq = ath_hal_gethwchannel(ah, chan);
222 struct ath_hal_5212 *ahp = AH5212(ah);
223 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
224 uint16_t rfXpdGainFixed, rfPloSel, rfPwdXpd, gainI;
225 uint16_t tempOB, tempDB;
226 uint32_t ob2GHz, db2GHz, rfReg[N(ar5212Bank6_5111)];
227 int i, regWrites = 0;
228
229 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
230 __func__, chan->ic_freq, chan->ic_flags, modesIndex);
231
232 /* Setup rf parameters */
233 switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
234 case IEEE80211_CHAN_A:
235 if (4000 < freq && freq < 5260) {
236 tempOB = ee->ee_ob1;
237 tempDB = ee->ee_db1;
238 } else if (5260 <= freq && freq < 5500) {
239 tempOB = ee->ee_ob2;
240 tempDB = ee->ee_db2;
241 } else if (5500 <= freq && freq < 5725) {
242 tempOB = ee->ee_ob3;
243 tempDB = ee->ee_db3;
244 } else if (freq >= 5725) {
245 tempOB = ee->ee_ob4;
246 tempDB = ee->ee_db4;
247 } else {
248 /* XXX when does this happen??? */
249 tempOB = tempDB = 0;
250 }
251 ob2GHz = db2GHz = 0;
252
253 rfXpdGainFixed = ee->ee_xgain[headerInfo11A];
254 rfPloSel = ee->ee_xpd[headerInfo11A];
255 rfPwdXpd = !ee->ee_xpd[headerInfo11A];
256 gainI = ee->ee_gainI[headerInfo11A];
257 break;
258 case IEEE80211_CHAN_B:
259 tempOB = ee->ee_obFor24;
260 tempDB = ee->ee_dbFor24;
261 ob2GHz = ee->ee_ob2GHz[0];
262 db2GHz = ee->ee_db2GHz[0];
263
264 rfXpdGainFixed = ee->ee_xgain[headerInfo11B];
265 rfPloSel = ee->ee_xpd[headerInfo11B];
266 rfPwdXpd = !ee->ee_xpd[headerInfo11B];
267 gainI = ee->ee_gainI[headerInfo11B];
268 break;
269 case IEEE80211_CHAN_G:
270 case IEEE80211_CHAN_PUREG: /* NB: really 108G */
271 tempOB = ee->ee_obFor24g;
272 tempDB = ee->ee_dbFor24g;
273 ob2GHz = ee->ee_ob2GHz[1];
274 db2GHz = ee->ee_db2GHz[1];
275
276 rfXpdGainFixed = ee->ee_xgain[headerInfo11G];
277 rfPloSel = ee->ee_xpd[headerInfo11G];
278 rfPwdXpd = !ee->ee_xpd[headerInfo11G];
279 gainI = ee->ee_gainI[headerInfo11G];
280 break;
281 default:
282 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
283 __func__, chan->ic_flags);
284 return AH_FALSE;
285 }
286
287 HALASSERT(1 <= tempOB && tempOB <= 5);
288 HALASSERT(1 <= tempDB && tempDB <= 5);
289
290 /* Bank 0 Write */
291 for (i = 0; i < N(ar5212Bank0_5111); i++)
292 rfReg[i] = ar5212Bank0_5111[i][modesIndex];
293 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
294 ar5212ModifyRfBuffer(rfReg, ob2GHz, 3, 119, 0);
295 ar5212ModifyRfBuffer(rfReg, db2GHz, 3, 122, 0);
296 }
297 HAL_INI_WRITE_BANK(ah, ar5212Bank0_5111, rfReg, regWrites);
298
299 /* Bank 1 Write */
300 HAL_INI_WRITE_ARRAY(ah, ar5212Bank1_5111, 1, regWrites);
301
302 /* Bank 2 Write */
303 HAL_INI_WRITE_ARRAY(ah, ar5212Bank2_5111, modesIndex, regWrites);
304
305 /* Bank 3 Write */
306 HAL_INI_WRITE_ARRAY(ah, ar5212Bank3_5111, modesIndex, regWrites);
307
308 /* Bank 6 Write */
309 for (i = 0; i < N(ar5212Bank6_5111); i++)
310 rfReg[i] = ar5212Bank6_5111[i][modesIndex];
311 if (IEEE80211_IS_CHAN_A(chan)) { /* NB: CHANNEL_A | CHANNEL_T */
312 ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd84, 1, 51, 3);
313 ar5212ModifyRfBuffer(rfReg, ee->ee_cornerCal.pd90, 1, 45, 3);
314 }
315 ar5212ModifyRfBuffer(rfReg, rfPwdXpd, 1, 95, 0);
316 ar5212ModifyRfBuffer(rfReg, rfXpdGainFixed, 4, 96, 0);
317 /* Set 5212 OB & DB */
318 ar5212ModifyRfBuffer(rfReg, tempOB, 3, 104, 0);
319 ar5212ModifyRfBuffer(rfReg, tempDB, 3, 107, 0);
320 HAL_INI_WRITE_BANK(ah, ar5212Bank6_5111, rfReg, regWrites);
321
322 /* Bank 7 Write */
323 for (i = 0; i < N(ar5212Bank7_5111); i++)
324 rfReg[i] = ar5212Bank7_5111[i][modesIndex];
325 ar5212ModifyRfBuffer(rfReg, gainI, 6, 29, 0);
326 ar5212ModifyRfBuffer(rfReg, rfPloSel, 1, 4, 0);
327
328 if (IEEE80211_IS_CHAN_QUARTER(chan) || IEEE80211_IS_CHAN_HALF(chan)) {
329 uint32_t rfWaitI, rfWaitS, rfMaxTime;
330
331 rfWaitS = 0x1f;
332 rfWaitI = (IEEE80211_IS_CHAN_HALF(chan)) ? 0x10 : 0x1f;
333 rfMaxTime = 3;
334 ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0);
335 ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0);
336 ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0);
337 }
338
339 HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites);
340
341 /* Now that we have reprogrammed rfgain value, clear the flag. */
342 ahp->ah_rfgainState = HAL_RFGAIN_INACTIVE;
343
344 return AH_TRUE;
345 }
346
347 /*
348 * Returns interpolated or the scaled up interpolated value
349 */
350 static uint16_t
interpolate(uint16_t target,uint16_t srcLeft,uint16_t srcRight,uint16_t targetLeft,uint16_t targetRight)351 interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
352 uint16_t targetLeft, uint16_t targetRight)
353 {
354 uint16_t rv;
355 int16_t lRatio;
356
357 /* to get an accurate ratio, always scale, if want to scale, then don't scale back down */
358 if ((targetLeft * targetRight) == 0)
359 return 0;
360
361 if (srcRight != srcLeft) {
362 /*
363 * Note the ratio always need to be scaled,
364 * since it will be a fraction.
365 */
366 lRatio = (target - srcLeft) * EEP_SCALE / (srcRight - srcLeft);
367 if (lRatio < 0) {
368 /* Return as Left target if value would be negative */
369 rv = targetLeft;
370 } else if (lRatio > EEP_SCALE) {
371 /* Return as Right target if Ratio is greater than 100% (SCALE) */
372 rv = targetRight;
373 } else {
374 rv = (lRatio * targetRight + (EEP_SCALE - lRatio) *
375 targetLeft) / EEP_SCALE;
376 }
377 } else {
378 rv = targetLeft;
379 }
380 return rv;
381 }
382
383 /*
384 * Read the transmit power levels from the structures taken from EEPROM
385 * Interpolate read transmit power values for this channel
386 * Organize the transmit power values into a table for writing into the hardware
387 */
388 static HAL_BOOL
ar5111SetPowerTable(struct ath_hal * ah,int16_t * pMinPower,int16_t * pMaxPower,const struct ieee80211_channel * chan,uint16_t * rfXpdGain)389 ar5111SetPowerTable(struct ath_hal *ah,
390 int16_t *pMinPower, int16_t *pMaxPower,
391 const struct ieee80211_channel *chan,
392 uint16_t *rfXpdGain)
393 {
394 uint16_t freq = ath_hal_gethwchannel(ah, chan);
395 struct ath_hal_5212 *ahp = AH5212(ah);
396 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
397 FULL_PCDAC_STRUCT pcdacStruct;
398 int i, j;
399
400 uint16_t *pPcdacValues;
401 int16_t *pScaledUpDbm;
402 int16_t minScaledPwr;
403 int16_t maxScaledPwr;
404 int16_t pwr;
405 uint16_t pcdacMin = 0;
406 uint16_t pcdacMax = PCDAC_STOP;
407 uint16_t pcdacTableIndex;
408 uint16_t scaledPcdac;
409 PCDACS_EEPROM *pSrcStruct;
410 PCDACS_EEPROM eepromPcdacs;
411
412 /* setup the pcdac struct to point to the correct info, based on mode */
413 switch (chan->ic_flags & IEEE80211_CHAN_ALLTURBOFULL) {
414 case IEEE80211_CHAN_A:
415 case IEEE80211_CHAN_ST:
416 eepromPcdacs.numChannels = ee->ee_numChannels11a;
417 eepromPcdacs.pChannelList = ee->ee_channels11a;
418 eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11a;
419 break;
420 case IEEE80211_CHAN_B:
421 eepromPcdacs.numChannels = ee->ee_numChannels2_4;
422 eepromPcdacs.pChannelList = ee->ee_channels11b;
423 eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11b;
424 break;
425 case IEEE80211_CHAN_G:
426 case IEEE80211_CHAN_108G:
427 eepromPcdacs.numChannels = ee->ee_numChannels2_4;
428 eepromPcdacs.pChannelList = ee->ee_channels11g;
429 eepromPcdacs.pDataPerChannel = ee->ee_dataPerChannel11g;
430 break;
431 default:
432 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
433 __func__, chan->ic_flags);
434 return AH_FALSE;
435 }
436
437 pSrcStruct = &eepromPcdacs;
438
439 OS_MEMZERO(&pcdacStruct, sizeof(pcdacStruct));
440 pPcdacValues = pcdacStruct.PcdacValues;
441 pScaledUpDbm = pcdacStruct.PwrValues;
442
443 /* Initialize the pcdacs to dBM structs pcdacs to be 1 to 63 */
444 for (i = PCDAC_START, j = 0; i <= PCDAC_STOP; i+= PCDAC_STEP, j++)
445 pPcdacValues[j] = i;
446
447 pcdacStruct.numPcdacValues = j;
448 pcdacStruct.pcdacMin = PCDAC_START;
449 pcdacStruct.pcdacMax = PCDAC_STOP;
450
451 /* Fill out the power values for this channel */
452 for (j = 0; j < pcdacStruct.numPcdacValues; j++ )
453 pScaledUpDbm[j] = ar5212GetScaledPower(freq,
454 pPcdacValues[j], pSrcStruct);
455
456 /* Now scale the pcdac values to fit in the 64 entry power table */
457 minScaledPwr = pScaledUpDbm[0];
458 maxScaledPwr = pScaledUpDbm[pcdacStruct.numPcdacValues - 1];
459
460 /* find minimum and make monotonic */
461 for (j = 0; j < pcdacStruct.numPcdacValues; j++) {
462 if (minScaledPwr >= pScaledUpDbm[j]) {
463 minScaledPwr = pScaledUpDbm[j];
464 pcdacMin = j;
465 }
466 /*
467 * Make the full_hsh monotonically increasing otherwise
468 * interpolation algorithm will get fooled gotta start
469 * working from the top, hence i = 63 - j.
470 */
471 i = (uint16_t)(pcdacStruct.numPcdacValues - 1 - j);
472 if (i == 0)
473 break;
474 if (pScaledUpDbm[i-1] > pScaledUpDbm[i]) {
475 /*
476 * It could be a glitch, so make the power for
477 * this pcdac the same as the power from the
478 * next highest pcdac.
479 */
480 pScaledUpDbm[i - 1] = pScaledUpDbm[i];
481 }
482 }
483
484 for (j = 0; j < pcdacStruct.numPcdacValues; j++)
485 if (maxScaledPwr < pScaledUpDbm[j]) {
486 maxScaledPwr = pScaledUpDbm[j];
487 pcdacMax = j;
488 }
489
490 /* Find the first power level with a pcdac */
491 pwr = (uint16_t)(PWR_STEP *
492 ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN);
493
494 /* Write all the first pcdac entries based off the pcdacMin */
495 pcdacTableIndex = 0;
496 for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++) {
497 HALASSERT(pcdacTableIndex < PWR_TABLE_SIZE);
498 ahp->ah_pcdacTable[pcdacTableIndex++] = pcdacMin;
499 }
500
501 i = 0;
502 while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
503 pcdacTableIndex < PWR_TABLE_SIZE) {
504 pwr += PWR_STEP;
505 /* stop if dbM > max_power_possible */
506 while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
507 (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
508 i++;
509 /* scale by 2 and add 1 to enable round up or down as needed */
510 scaledPcdac = (uint16_t)(interpolate(pwr,
511 pScaledUpDbm[i], pScaledUpDbm[i + 1],
512 (uint16_t)(pPcdacValues[i] * 2),
513 (uint16_t)(pPcdacValues[i + 1] * 2)) + 1);
514
515 HALASSERT(pcdacTableIndex < PWR_TABLE_SIZE);
516 ahp->ah_pcdacTable[pcdacTableIndex] = scaledPcdac / 2;
517 if (ahp->ah_pcdacTable[pcdacTableIndex] > pcdacMax)
518 ahp->ah_pcdacTable[pcdacTableIndex] = pcdacMax;
519 pcdacTableIndex++;
520 }
521
522 /* Write all the last pcdac entries based off the last valid pcdac */
523 while (pcdacTableIndex < PWR_TABLE_SIZE) {
524 ahp->ah_pcdacTable[pcdacTableIndex] =
525 ahp->ah_pcdacTable[pcdacTableIndex - 1];
526 pcdacTableIndex++;
527 }
528
529 /* No power table adjustment for 5111 */
530 ahp->ah_txPowerIndexOffset = 0;
531
532 return AH_TRUE;
533 }
534
535 /*
536 * Get or interpolate the pcdac value from the calibrated data.
537 */
538 static uint16_t
ar5212GetScaledPower(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct)539 ar5212GetScaledPower(uint16_t channel, uint16_t pcdacValue,
540 const PCDACS_EEPROM *pSrcStruct)
541 {
542 uint16_t powerValue;
543 uint16_t lFreq, rFreq; /* left and right frequency values */
544 uint16_t llPcdac, ulPcdac; /* lower and upper left pcdac values */
545 uint16_t lrPcdac, urPcdac; /* lower and upper right pcdac values */
546 uint16_t lPwr, uPwr; /* lower and upper temp pwr values */
547 uint16_t lScaledPwr, rScaledPwr; /* left and right scaled power */
548
549 if (ar5212FindValueInList(channel, pcdacValue, pSrcStruct, &powerValue)) {
550 /* value was copied from srcStruct */
551 return powerValue;
552 }
553
554 ar5212GetLowerUpperValues(channel,
555 pSrcStruct->pChannelList, pSrcStruct->numChannels,
556 &lFreq, &rFreq);
557 ar5212GetLowerUpperPcdacs(pcdacValue,
558 lFreq, pSrcStruct, &llPcdac, &ulPcdac);
559 ar5212GetLowerUpperPcdacs(pcdacValue,
560 rFreq, pSrcStruct, &lrPcdac, &urPcdac);
561
562 /* get the power index for the pcdac value */
563 ar5212FindValueInList(lFreq, llPcdac, pSrcStruct, &lPwr);
564 ar5212FindValueInList(lFreq, ulPcdac, pSrcStruct, &uPwr);
565 lScaledPwr = interpolate(pcdacValue, llPcdac, ulPcdac, lPwr, uPwr);
566
567 ar5212FindValueInList(rFreq, lrPcdac, pSrcStruct, &lPwr);
568 ar5212FindValueInList(rFreq, urPcdac, pSrcStruct, &uPwr);
569 rScaledPwr = interpolate(pcdacValue, lrPcdac, urPcdac, lPwr, uPwr);
570
571 return interpolate(channel, lFreq, rFreq, lScaledPwr, rScaledPwr);
572 }
573
574 /*
575 * Find the value from the calibrated source data struct
576 */
577 static HAL_BOOL
ar5212FindValueInList(uint16_t channel,uint16_t pcdacValue,const PCDACS_EEPROM * pSrcStruct,uint16_t * powerValue)578 ar5212FindValueInList(uint16_t channel, uint16_t pcdacValue,
579 const PCDACS_EEPROM *pSrcStruct, uint16_t *powerValue)
580 {
581 const DATA_PER_CHANNEL *pChannelData = pSrcStruct->pDataPerChannel;
582 int i;
583
584 for (i = 0; i < pSrcStruct->numChannels; i++ ) {
585 if (pChannelData->channelValue == channel) {
586 const uint16_t* pPcdac = pChannelData->PcdacValues;
587 int j;
588
589 for (j = 0; j < pChannelData->numPcdacValues; j++ ) {
590 if (*pPcdac == pcdacValue) {
591 *powerValue = pChannelData->PwrValues[j];
592 return AH_TRUE;
593 }
594 pPcdac++;
595 }
596 }
597 pChannelData++;
598 }
599 return AH_FALSE;
600 }
601
602 /*
603 * Get the upper and lower pcdac given the channel and the pcdac
604 * used in the search
605 */
606 static void
ar5212GetLowerUpperPcdacs(uint16_t pcdac,uint16_t channel,const PCDACS_EEPROM * pSrcStruct,uint16_t * pLowerPcdac,uint16_t * pUpperPcdac)607 ar5212GetLowerUpperPcdacs(uint16_t pcdac, uint16_t channel,
608 const PCDACS_EEPROM *pSrcStruct,
609 uint16_t *pLowerPcdac, uint16_t *pUpperPcdac)
610 {
611 const DATA_PER_CHANNEL *pChannelData = pSrcStruct->pDataPerChannel;
612 int i;
613
614 /* Find the channel information */
615 for (i = 0; i < pSrcStruct->numChannels; i++) {
616 if (pChannelData->channelValue == channel)
617 break;
618 pChannelData++;
619 }
620 ar5212GetLowerUpperValues(pcdac, pChannelData->PcdacValues,
621 pChannelData->numPcdacValues,
622 pLowerPcdac, pUpperPcdac);
623 }
624
625 static HAL_BOOL
ar5111GetChannelMaxMinPower(struct ath_hal * ah,const struct ieee80211_channel * chan,int16_t * maxPow,int16_t * minPow)626 ar5111GetChannelMaxMinPower(struct ath_hal *ah,
627 const struct ieee80211_channel *chan,
628 int16_t *maxPow, int16_t *minPow)
629 {
630 /* XXX - Get 5111 power limits! */
631 /* NB: caller will cope */
632 return AH_FALSE;
633 }
634
635 /*
636 * Adjust NF based on statistical values for 5GHz frequencies.
637 */
638 static int16_t
ar5111GetNfAdjust(struct ath_hal * ah,const HAL_CHANNEL_INTERNAL * c)639 ar5111GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
640 {
641 static const struct {
642 uint16_t freqLow;
643 int16_t adjust;
644 } adjust5111[] = {
645 { 5790, 6 }, /* NB: ordered high -> low */
646 { 5730, 4 },
647 { 5690, 3 },
648 { 5660, 2 },
649 { 5610, 1 },
650 { 5530, 0 },
651 { 5450, 0 },
652 { 5379, 1 },
653 { 5209, 3 },
654 { 3000, 5 },
655 { 0, 0 },
656 };
657 int i;
658
659 for (i = 0; c->channel <= adjust5111[i].freqLow; i++)
660 ;
661 return adjust5111[i].adjust;
662 }
663
664 /*
665 * Free memory for analog bank scratch buffers
666 */
667 static void
ar5111RfDetach(struct ath_hal * ah)668 ar5111RfDetach(struct ath_hal *ah)
669 {
670 struct ath_hal_5212 *ahp = AH5212(ah);
671
672 HALASSERT(ahp->ah_rfHal != AH_NULL);
673 ath_hal_free(ahp->ah_rfHal);
674 ahp->ah_rfHal = AH_NULL;
675 }
676
677 /*
678 * Allocate memory for analog bank scratch buffers
679 * Scratch Buffer will be reinitialized every reset so no need to zero now
680 */
681 static HAL_BOOL
ar5111RfAttach(struct ath_hal * ah,HAL_STATUS * status)682 ar5111RfAttach(struct ath_hal *ah, HAL_STATUS *status)
683 {
684 struct ath_hal_5212 *ahp = AH5212(ah);
685 struct ar5111State *priv;
686
687 HALASSERT(ah->ah_magic == AR5212_MAGIC);
688
689 HALASSERT(ahp->ah_rfHal == AH_NULL);
690 priv = ath_hal_malloc(sizeof(struct ar5111State));
691 if (priv == AH_NULL) {
692 HALDEBUG(ah, HAL_DEBUG_ANY,
693 "%s: cannot allocate private state\n", __func__);
694 *status = HAL_ENOMEM; /* XXX */
695 return AH_FALSE;
696 }
697 priv->base.rfDetach = ar5111RfDetach;
698 priv->base.writeRegs = ar5111WriteRegs;
699 priv->base.getRfBank = ar5111GetRfBank;
700 priv->base.setChannel = ar5111SetChannel;
701 priv->base.setRfRegs = ar5111SetRfRegs;
702 priv->base.setPowerTable = ar5111SetPowerTable;
703 priv->base.getChannelMaxMinPower = ar5111GetChannelMaxMinPower;
704 priv->base.getNfAdjust = ar5111GetNfAdjust;
705
706 ahp->ah_pcdacTable = priv->pcdacTable;
707 ahp->ah_pcdacTableSize = sizeof(priv->pcdacTable);
708 ahp->ah_rfHal = &priv->base;
709
710 return AH_TRUE;
711 }
712
713 static HAL_BOOL
ar5111Probe(struct ath_hal * ah)714 ar5111Probe(struct ath_hal *ah)
715 {
716 return IS_RAD5111(ah);
717 }
718 AH_RF(RF5111, ar5111Probe, ar5111RfAttach);
719