1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 25 */ 26 27 28 #ifndef _AHCIVAR_H 29 #define _AHCIVAR_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * AHCI address qualifier flags (in qual field of ahci_addr struct). 37 */ 38 #define AHCI_ADDR_NULL 0x00 39 #define AHCI_ADDR_PORT 0x01 40 #define AHCI_ADDR_PMPORT 0x02 41 #define AHCI_ADDR_PMULT 0x04 42 #define AHCI_ADDR_VALID (AHCI_ADDR_PORT | \ 43 AHCI_ADDR_PMULT | \ 44 AHCI_ADDR_PMPORT) 45 46 /* 47 * AHCI address structure. 48 */ 49 struct ahci_addr { 50 51 /* HBA port number */ 52 uint8_t aa_port; 53 54 /* Port multiplier port number */ 55 uint8_t aa_pmport; 56 57 /* 58 * AHCI_ADDR_NULL 59 * AHCI_ADDR_PORT 60 * AHCI_ADDR_PMPORT 61 * AHCI_ADDR_PMULT 62 */ 63 uint8_t aa_qual; 64 }; 65 typedef struct ahci_addr ahci_addr_t; 66 67 _NOTE(SCHEME_PROTECTS_DATA("unshared data", ahci_addr)) 68 69 #define AHCI_ADDR_IS_PORT(addrp) \ 70 ((addrp)->aa_qual & AHCI_ADDR_PORT) 71 #define AHCI_ADDR_IS_PMPORT(addrp) \ 72 ((addrp)->aa_qual & AHCI_ADDR_PMPORT) 73 #define AHCI_ADDR_IS_PMULT(addrp) \ 74 ((addrp)->aa_qual & AHCI_ADDR_PMULT) 75 #define AHCI_ADDR_IS_VALID(addrp) \ 76 ((addrp)->aa_port < SATA_MAX_CPORTS) && \ 77 ((addrp)->aa_pmport < SATA_MAX_PMPORTS) && \ 78 ((addrp)->aa_qual & AHCI_ADDR_VALID) 79 80 #define AHCI_ADDR_SET(addrp, port, pmport, qual) \ 81 { \ 82 (addrp)->aa_port = port; \ 83 (addrp)->aa_pmport = pmport; \ 84 (addrp)->aa_qual = qual; \ 85 } 86 #define AHCI_ADDR_SET_PORT(addrp, port) \ 87 AHCI_ADDR_SET(addrp, port, 0, AHCI_ADDR_PORT) 88 #define AHCI_ADDR_SET_PMPORT(addrp, port, pmport) \ 89 AHCI_ADDR_SET(addrp, port, pmport, AHCI_ADDR_PMPORT) 90 #define AHCI_ADDR_SET_PMULT(addrp, port) \ 91 AHCI_ADDR_SET(addrp, port, SATA_PMULT_HOSTPORT, AHCI_ADDR_PMULT) 92 93 /* Type for argument of event handler */ 94 typedef struct ahci_event_arg { 95 void *ahciea_ctlp; 96 void *ahciea_portp; 97 void *ahciea_addrp; 98 uint32_t ahciea_event; 99 } ahci_event_arg_t; 100 101 /* Warlock annotation */ 102 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_ctlp)) 103 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_portp)) 104 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_addrp)) 105 _NOTE(DATA_READABLE_WITHOUT_LOCK(ahci_event_arg_t::ahciea_event)) 106 107 108 /* 109 * ahci_pmult_info stores the information of a port multiplier and its 110 * sub-devices in case a port multiplier is attached to an HBA port. 111 */ 112 struct ahci_pmult_info { 113 114 /* Number of the device ports */ 115 int ahcipmi_num_dev_ports; 116 117 /* Device type of the sub-devices of the port multipler */ 118 uint8_t ahcipmi_device_type[SATA_MAX_PMPORTS]; 119 120 /* State of port multiplier port */ 121 uint32_t ahcipmi_port_state[SATA_MAX_PMPORTS]; 122 123 /* 124 * Port multiplier port on which there is outstanding NCQ 125 * commands. Only make sense in command based switching mode. 126 */ 127 uint8_t ahcipmi_ncq_pmport; 128 129 /* Pending asynchronous notification events tags */ 130 uint32_t ahcipmi_snotif_tags; 131 }; 132 typedef struct ahci_pmult_info ahci_pmult_info_t; 133 134 /* 135 * flags for ahciport_flags 136 * 137 * AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped, 138 * and all the outstanding commands need to be aborted and sent to upper 139 * layers. 140 * 141 * AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is 142 * disabled, and the command is executed in POLLING mode. 143 * 144 * AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which 145 * is used to retrieve sense data is being executed. 146 * 147 * AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started, 148 * that is PxCMD.ST is set with '1', and be cleared when the port is put into 149 * idle, that is PxCMD.ST is changed from '1' to '0'. 150 * 151 * AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which 152 * is used to retrieve NCQ failure context is being executed. 153 * 154 * AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone 155 * during ahci_restart_port_wait_till_ready process. 156 * 157 * AHCI_PORT_FLAG_RDWR_PMULT: this flag will be set when a READ/WRITE 158 * PORTMULT command is being executed. 159 * 160 * AHCI_PORT_FLAG_IGNORE_IPMS: this flag will be set when enumerating a port 161 * multiplier. According AHCI spec, IPMS error should be ignore during 162 * enumeration of port multiplier. 163 * 164 * AHCI_PORT_FLAG_PMULT_SNTF: this flag will be set when the a asynchronous 165 * notification event on the port multiplier is being handled. 166 * 167 * AHCI_PORT_FLAG_HOTPLUG: this flag will be set when a hot plug event is 168 * being handled. 169 * 170 * AHCI_PORT_FLAG_ERRPRINT: this flag will be set when error recovery message 171 * will be printed. Note that, for INDENTIFY DEVICE command sent to ATAPI 172 * device or ATAPI PACKET command, this flag won't be set. 173 */ 174 #define AHCI_PORT_FLAG_MOPPING 0x02 175 #define AHCI_PORT_FLAG_POLLING 0x04 176 #define AHCI_PORT_FLAG_RQSENSE 0x08 177 #define AHCI_PORT_FLAG_STARTED 0x10 178 #define AHCI_PORT_FLAG_RDLOGEXT 0x20 179 #define AHCI_PORT_FLAG_NODEV 0x40 180 #define AHCI_PORT_FLAG_RDWR_PMULT 0x80 181 #define AHCI_PORT_FLAG_IGNORE_IPMS 0x100 182 #define AHCI_PORT_FLAG_PMULT_SNTF 0x200 183 #define AHCI_PORT_FLAG_HOTPLUG 0x400 184 #define AHCI_PORT_FLAG_ERRPRINT 0x800 185 186 typedef struct ahci_port { 187 /* The physical port number */ 188 uint8_t ahciport_port_num; 189 190 /* Type of the device attached to the port */ 191 uint8_t ahciport_device_type; 192 /* State of the port */ 193 uint32_t ahciport_port_state; 194 195 /* Port multiplier struct */ 196 ahci_pmult_info_t *ahciport_pmult_info; 197 198 /* 199 * AHCI_PORT_FLAG_MOPPING 200 * AHCI_PORT_FLAG_POLLING 201 * AHCI_PORT_FLAG_RQSENSE 202 * AHCI_PORT_FLAG_STARTED 203 * AHCI_PORT_FLAG_RDLOGEXT 204 * AHCI_PORT_FLAG_NODEV 205 * AHCI_PORT_FLAG_RDWR_PMULT 206 * AHCI_PORT_FLAG_IGNORE_IPMS 207 * AHCI_PORT_FLAG_PMULT_SNTF 208 * AHCI_PORT_FLAG_HOTPLUG 209 * AHCI_PORT_FLAG_ERRPRINT 210 */ 211 int ahciport_flags; 212 213 /* Pointer to received FIS structure */ 214 ahci_rcvd_fis_t *ahciport_rcvd_fis; 215 ddi_dma_handle_t ahciport_rcvd_fis_dma_handle; 216 ddi_acc_handle_t ahciport_rcvd_fis_acc_handle; 217 ddi_dma_cookie_t ahciport_rcvd_fis_dma_cookie; 218 219 /* Pointer to command list structure */ 220 ahci_cmd_header_t *ahciport_cmd_list; 221 ddi_dma_handle_t ahciport_cmd_list_dma_handle; 222 ddi_acc_handle_t ahciport_cmd_list_acc_handle; 223 ddi_dma_cookie_t ahciport_cmd_list_dma_cookie; 224 225 /* Pointer to cmmand table structure */ 226 ahci_cmd_table_t \ 227 *ahciport_cmd_tables[AHCI_PORT_MAX_CMD_SLOTS]; 228 ddi_dma_handle_t \ 229 ahciport_cmd_tables_dma_handle[AHCI_PORT_MAX_CMD_SLOTS]; 230 ddi_acc_handle_t \ 231 ahciport_cmd_tables_acc_handle[AHCI_PORT_MAX_CMD_SLOTS]; 232 233 /* Condition variable used for sync mode commands */ 234 kcondvar_t ahciport_cv; 235 236 /* The whole mutex for the port structure */ 237 kmutex_t ahciport_mutex; 238 239 /* The maximum number of tags for native queuing command transfers */ 240 int ahciport_max_ncq_tags; 241 242 /* Keep the tags of all pending non-ncq commands */ 243 uint32_t ahciport_pending_tags; 244 245 /* 246 * Keep the tags of all pending ncq commands 247 * (READ/WRITE FPDMA QUEUED) 248 */ 249 uint32_t ahciport_pending_ncq_tags; 250 251 /* Keep all the pending sata packets */ 252 sata_pkt_t *ahciport_slot_pkts[AHCI_PORT_MAX_CMD_SLOTS]; 253 254 /* Used to check whether corresponding packet is timeout */ 255 int ahciport_slot_timeout[AHCI_PORT_MAX_CMD_SLOTS]; 256 257 /* Queue of completed (done) sata packet */ 258 sata_pkt_t *ahciport_doneq; 259 260 /* Pointer of the tail of completed sata packet queue */ 261 sata_pkt_t **ahciport_doneqtail; 262 263 /* the length of the completed sata packet queue */ 264 uint32_t ahciport_doneq_len; 265 266 /* Keep the byte count of all PRD entries for every sata packet */ 267 uint32_t \ 268 ahciport_prd_bytecounts[AHCI_PORT_MAX_CMD_SLOTS]; 269 270 /* Keep the error retrieval sata packet */ 271 sata_pkt_t *ahciport_err_retri_pkt; 272 273 /* Keep the read/write port multiplier packet */ 274 sata_pkt_t *ahciport_rdwr_pmult_pkt; 275 276 /* 277 * SATA HBA driver is supposed to remember and maintain device 278 * reset state. While the reset is in progress, it doesn't accept 279 * any more commands until receiving the command with 280 * SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE. 281 */ 282 int ahciport_reset_in_progress; 283 284 /* Taskq for handling event */ 285 ddi_taskq_t *ahciport_event_taskq; 286 287 /* This is for error recovery handler */ 288 ahci_event_arg_t *ahciport_event_args; 289 290 /* This is to calculate how many mops are in progress */ 291 int ahciport_mop_in_progress; 292 } ahci_port_t; 293 294 /* Warlock annotation */ 295 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_rcvd_fis_dma_handle)) 296 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_list_dma_handle)) 297 _NOTE(READ_ONLY_DATA(ahci_port_t::ahciport_cmd_tables_dma_handle)) 298 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 299 ahci_port_t::ahciport_device_type)) 300 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 301 ahci_port_t::ahciport_port_state)) 302 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 303 ahci_port_t::ahciport_flags)) 304 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 305 ahci_port_t::ahciport_pending_tags)) 306 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 307 ahci_port_t::ahciport_slot_pkts)) 308 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 309 ahci_port_t::ahciport_slot_timeout)) 310 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 311 ahci_port_t::ahciport_doneq)) 312 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 313 ahci_port_t::ahciport_doneqtail)) 314 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 315 ahci_port_t::ahciport_doneq_len)) 316 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 317 ahci_port_t::ahciport_reset_in_progress)) 318 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 319 ahci_port_t::ahciport_mop_in_progress)) 320 _NOTE(MUTEX_PROTECTS_DATA(ahci_port_t::ahciport_mutex, 321 ahci_port_t::ahciport_event_taskq)) 322 323 #define AHCI_NUM_PORTS(ctlp) \ 324 (ctlp)->ahcictl_num_ports 325 326 #define AHCIPORT_NUM_PMPORTS(portp) \ 327 (portp)->ahciport_pmult_info->ahcipmi_num_dev_ports 328 329 #define AHCIPORT_NCQ_PMPORT(ahci_portp) \ 330 (ahci_portp->ahciport_pmult_info->ahcipmi_ncq_pmport) 331 332 #define AHCIPORT_DEV_TYPE(portp, addrp) \ 333 (portp)->ahciport_device_type 334 335 #define AHCIPORT_PMDEV_TYPE(portp, addrp) \ 336 (portp)->ahciport_pmult_info->ahcipmi_device_type \ 337 [(addrp)->aa_pmport] 338 339 #define AHCIPORT_GET_DEV_TYPE(portp, addrp) \ 340 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \ 341 AHCIPORT_DEV_TYPE(portp, addrp) : \ 342 AHCIPORT_PMDEV_TYPE(portp, addrp)) 343 344 #define AHCIPORT_SET_DEV_TYPE(portp, addrp, type) \ 345 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \ 346 AHCIPORT_DEV_TYPE(portp, addrp) = type; \ 347 else \ 348 AHCIPORT_PMDEV_TYPE(portp, addrp) = type; 349 350 #define AHCIPORT_STATE(portp, addrp) \ 351 (portp)->ahciport_port_state 352 353 #define AHCIPORT_PMSTATE(portp, addrp) \ 354 (portp)->ahciport_pmult_info->ahcipmi_port_state \ 355 [(addrp)->aa_pmport] 356 357 #define AHCIPORT_GET_STATE(portp, addrp) \ 358 (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp) ? \ 359 AHCIPORT_STATE(portp, addrp) : AHCIPORT_PMSTATE(portp, addrp)) 360 361 #define AHCIPORT_SET_STATE(portp, addrp, state) \ 362 if (AHCI_ADDR_IS_PORT(addrp) | AHCI_ADDR_IS_PMULT(addrp)) \ 363 AHCIPORT_STATE(portp, addrp) = state; \ 364 else \ 365 AHCIPORT_PMSTATE(portp, addrp) = state; 366 367 typedef struct ahci_ctl { 368 dev_info_t *ahcictl_dip; 369 370 ushort_t ahcictl_venid; 371 ushort_t ahcictl_devid; 372 373 /* To map port number to cport number */ 374 uint8_t ahcictl_port_to_cport[AHCI_MAX_PORTS]; 375 /* To map cport number to port number */ 376 uint8_t ahcictl_cport_to_port[AHCI_MAX_PORTS]; 377 378 /* Number of controller ports */ 379 int ahcictl_num_ports; 380 /* Number of command slots */ 381 int ahcictl_num_cmd_slots; 382 /* Number of implemented ports */ 383 int ahcictl_num_implemented_ports; 384 /* Bit map to indicate which port is implemented */ 385 uint32_t ahcictl_ports_implemented; 386 ahci_port_t *ahcictl_ports[AHCI_MAX_PORTS]; 387 388 int ahcictl_flags; 389 int ahcictl_power_level; 390 off_t ahcictl_pmcsr_offset; 391 392 /* 393 * AHCI_CAP_PIO_MDRQ 394 * AHCI_CAP_NO_MCMDLIST_NONQUEUE 395 * AHCI_CAP_NCQ 396 * AHCI_CAP_PM 397 * AHCI_CAP_BUF_32BIT_DMA 398 * AHCI_CAP_SCLO 399 * AHCI_CAP_COMMU_32BIT_DMA 400 * AHCI_CAP_INIT_PORT_RESET 401 * AHCI_CAP_SNTF 402 * AHCI_CAP_PMULT_CBSS 403 * AHCI_CAP_PMULT_FBSS 404 * AHCI_CAP_SRST_NO_HOSTPORT 405 */ 406 int ahcictl_cap; 407 408 /* Pci configuration space handle */ 409 ddi_acc_handle_t ahcictl_pci_conf_handle; 410 411 /* Mapping into bar 5 - AHCI base address */ 412 ddi_acc_handle_t ahcictl_ahci_acc_handle; 413 uintptr_t ahcictl_ahci_addr; 414 415 /* Pointer used for sata hba framework registration */ 416 struct sata_hba_tran *ahcictl_sata_hba_tran; 417 418 /* DMA attributes for the data buffer */ 419 ddi_dma_attr_t ahcictl_buffer_dma_attr; 420 /* DMA attributes for the rcvd FIS */ 421 ddi_dma_attr_t ahcictl_rcvd_fis_dma_attr; 422 /* DMA attributes for the command list */ 423 ddi_dma_attr_t ahcictl_cmd_list_dma_attr; 424 /* DMA attributes for command tables */ 425 ddi_dma_attr_t ahcictl_cmd_table_dma_attr; 426 427 /* Used for watchdog handler */ 428 timeout_id_t ahcictl_timeout_id; 429 430 /* Per controller mutex */ 431 kmutex_t ahcictl_mutex; 432 433 /* Components for interrupt */ 434 ddi_intr_handle_t *ahcictl_intr_htable; /* For array of intrs */ 435 int ahcictl_intr_type; /* What type of interrupt */ 436 int ahcictl_intr_cnt; /* # of intrs returned */ 437 size_t ahcictl_intr_size; /* Size of intr array */ 438 uint_t ahcictl_intr_pri; /* Intr priority */ 439 int ahcictl_intr_cap; /* Intr capabilities */ 440 441 /* FMA capabilities */ 442 int ahcictl_fm_cap; 443 } ahci_ctl_t; 444 445 /* Warlock annotation */ 446 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_ports)) 447 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_cport_to_port)) 448 _NOTE(READ_ONLY_DATA(ahci_ctl_t::ahcictl_port_to_cport)) 449 450 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 451 ahci_ctl_t::ahcictl_power_level)) 452 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 453 ahci_ctl_t::ahcictl_flags)) 454 _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex, 455 ahci_ctl_t::ahcictl_timeout_id)) 456 457 #define AHCI_SUCCESS (0) /* Successful return */ 458 #define AHCI_TIMEOUT (1) /* Timed out */ 459 #define AHCI_FAILURE (-1) /* Unsuccessful return */ 460 461 /* Flags for ahcictl_flags */ 462 #define AHCI_ATTACH 0x1 463 #define AHCI_DETACH 0x2 464 #define AHCI_SUSPEND 0x4 465 #define AHCI_QUIESCE 0x8 466 467 /* Values for ahcictl_cap */ 468 /* PIO Multiple DRQ Block */ 469 #define AHCI_CAP_PIO_MDRQ 0x1 470 /* 471 * Multiple command slots in the command list cannot be used for 472 * non-queued commands 473 */ 474 #define AHCI_CAP_NO_MCMDLIST_NONQUEUE 0x2 475 /* Native Command Queuing (NCQ) */ 476 #define AHCI_CAP_NCQ 0x4 477 /* Power Management (PM) */ 478 #define AHCI_CAP_PM 0x8 479 /* 32-bit DMA addressing for buffer block */ 480 #define AHCI_CAP_BUF_32BIT_DMA 0x10 481 /* Supports Command List Override */ 482 #define AHCI_CAP_SCLO 0x20 483 /* 32-bit DMA addressing for communication memory descriptors */ 484 #define AHCI_CAP_COMMU_32BIT_DMA 0x40 485 /* Port reset is needed for initialization */ 486 #define AHCI_CAP_INIT_PORT_RESET 0x80 487 /* Port Asychronous Notification */ 488 #define AHCI_CAP_SNTF 0x100 489 /* Port Multiplier Command-Based Switching Support (PMULT_CBSS) */ 490 #define AHCI_CAP_PMULT_CBSS 0x200 491 /* Port Multiplier FIS-Based Switching Support (PMULT_FBSS) */ 492 #define AHCI_CAP_PMULT_FBSS 0x400 493 /* Software Reset FIS cannot set pmport with 0xf for direct access device */ 494 #define AHCI_CAP_SRST_NO_HOSTPORT 0x800 495 496 /* Flags controlling the restart port behavior */ 497 #define AHCI_PORT_RESET 0x0001 /* Reset the port */ 498 #define AHCI_RESET_NO_EVENTS_UP 0x0002 /* Don't send reset events up */ 499 500 #define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \ 501 (ahci_portp->ahciport_flags & \ 502 (AHCI_PORT_FLAG_RQSENSE|AHCI_PORT_FLAG_RDLOGEXT)) 503 504 #define RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) \ 505 (ahci_portp->ahciport_flags & \ 506 AHCI_PORT_FLAG_RDWR_PMULT) 507 508 #define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \ 509 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 510 ahci_portp->ahciport_pending_tags != 0 && \ 511 ahci_portp->ahciport_pending_ncq_tags == 0) 512 513 #define NCQ_CMD_IN_PROGRESS(ahci_portp) \ 514 (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \ 515 ahci_portp->ahciport_pending_ncq_tags != 0) 516 517 /* Command type for ahci_claim_free_slot routine */ 518 #define AHCI_NON_NCQ_CMD 0x0 519 #define AHCI_NCQ_CMD 0x1 520 #define AHCI_ERR_RETRI_CMD 0x2 521 #define AHCI_RDWR_PMULT_CMD 0x4 522 523 /* State values for ahci_attach */ 524 #define AHCI_ATTACH_STATE_NONE (0x1 << 0) 525 #define AHCI_ATTACH_STATE_STATEP_ALLOC (0x1 << 1) 526 #define AHCI_ATTACH_STATE_FMA (0x1 << 2) 527 #define AHCI_ATTACH_STATE_REG_MAP (0x1 << 3) 528 #define AHCI_ATTACH_STATE_PCICFG_SETUP (0x1 << 4) 529 #define AHCI_ATTACH_STATE_INTR_ADDED (0x1 << 5) 530 #define AHCI_ATTACH_STATE_MUTEX_INIT (0x1 << 6) 531 #define AHCI_ATTACH_STATE_PORT_ALLOC (0x1 << 7) 532 #define AHCI_ATTACH_STATE_HW_INIT (0x1 << 8) 533 #define AHCI_ATTACH_STATE_TIMEOUT_ENABLED (0x1 << 9) 534 535 /* Interval used for delay */ 536 #define AHCI_10MS_TICKS (drv_usectohz(10000)) /* ticks in 10 ms */ 537 #define AHCI_1MS_TICKS (drv_usectohz(1000)) /* ticks in 1 ms */ 538 #define AHCI_100US_TICKS (drv_usectohz(100)) /* ticks in 100 us */ 539 #define AHCI_10MS_USECS (10000) /* microsecs in 10 millisec */ 540 #define AHCI_1MS_USECS (1000) /* microsecs in 1 millisec */ 541 #define AHCI_100US_USECS (100) 542 543 /* 544 * The following values are the numbers of times to retry polled requests. 545 */ 546 #define AHCI_POLLRATE_HBA_RESET 100 547 #define AHCI_POLLRATE_PORT_SSTATUS 10 548 #define AHCI_POLLRATE_PORT_TFD_ERROR 1100 549 #define AHCI_POLLRATE_PORT_IDLE 50 550 #define AHCI_POLLRATE_PORT_SOFTRESET 100 551 #define AHCI_POLLRATE_GET_SPKT 100 552 #define AHCI_POLLRATE_PORT_IDLE_FR 500 553 554 555 /* Clearing & setting the n'th bit in a given tag */ 556 #define CLEAR_BIT(tag, bit) (tag &= ~(0x1<<bit)) 557 #define SET_BIT(tag, bit) (tag |= (0x1<<bit)) 558 559 560 #if DEBUG 561 562 #define AHCI_DEBUG 1 563 564 #endif 565 566 #define AHCIDBG_INIT 0x0001 567 #define AHCIDBG_ENTRY 0x0002 568 #define AHCIDBG_PRDT 0x0004 569 #define AHCIDBG_EVENT 0x0008 570 #define AHCIDBG_POLL_LOOP 0x0010 571 #define AHCIDBG_PKTCOMP 0x0020 572 #define AHCIDBG_TIMEOUT 0x0040 573 #define AHCIDBG_INFO 0x0080 574 #define AHCIDBG_VERBOSE 0x0100 575 #define AHCIDBG_INTR 0x0200 576 #define AHCIDBG_ERRS 0x0400 577 #define AHCIDBG_ATACMD 0x0800 578 #define AHCIDBG_ATAPICMD 0x1000 579 #define AHCIDBG_SENSEDATA 0x2000 580 #define AHCIDBG_NCQ 0x4000 581 #define AHCIDBG_PM 0x8000 582 #define AHCIDBG_UNDERFLOW 0x10000 583 #define AHCIDBG_MSI 0x20000 584 #define AHCIDBG_PMULT 0x40000 585 586 extern uint32_t ahci_debug_flags; 587 588 #if DEBUG 589 590 #define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \ 591 if (ahci_debug_flags & (flag)) { \ 592 ahci_log(ahci_ctlp, CE_WARN, fmt, ## args); \ 593 if (ahci_ctlp == NULL) \ 594 sata_trace_debug(NULL, fmt, ## args); \ 595 else \ 596 sata_trace_debug(ahci_ctlp->ahcictl_dip,\ 597 fmt, ## args); \ 598 } 599 600 #else 601 602 #define AHCIDBG(flag, ahci_ctlp, fmt, args ...) \ 603 if (ahci_debug_flags & (flag)) { \ 604 if (ahci_ctlp == NULL) \ 605 sata_trace_debug(NULL, fmt, ## args); \ 606 else \ 607 sata_trace_debug(ahci_ctlp->ahcictl_dip,\ 608 fmt, ## args); \ 609 } 610 611 #endif /* DEBUG */ 612 613 614 #ifdef __cplusplus 615 } 616 #endif 617 618 #endif /* _AHCIVAR_H */ 619