1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef ADF_DH895x_HW_DATA_H_ 4 #define ADF_DH895x_HW_DATA_H_ 5 6 /* PCIe configuration space */ 7 #define ADF_DH895XCC_SRAM_BAR 0 8 #define ADF_DH895XCC_PMISC_BAR 1 9 #define ADF_DH895XCC_ETR_BAR 2 10 #define ADF_DH895XCC_RX_RINGS_OFFSET 8 11 #define ADF_DH895XCC_TX_RINGS_MASK 0xFF 12 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000 13 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20 14 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0 15 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1 16 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2 17 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3 18 #define ADF_DH895XCC_MAX_ACCELERATORS 6 19 #define ADF_DH895XCC_MAX_ACCELENGINES 12 20 #define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13 21 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F 22 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF 23 #define ADF_DH895XCC_ETR_MAX_BANKS 32 24 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28) 25 #define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) 26 #define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF 27 #define ADF_DH895XCC_SMIA1_MASK 0x1 28 /* Error detection and correction */ 29 #define ADF_DH895XCC_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) 30 #define ADF_DH895XCC_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) 31 #define ADF_DH895XCC_ENABLE_AE_ECC_ERR BIT(28) 32 #define ADF_DH895XCC_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12)) 33 #define ADF_DH895XCC_UERRSSMSH(i) (i * 0x4000 + 0x18) 34 #define ADF_DH895XCC_CERRSSMSH(i) (i * 0x4000 + 0x10) 35 #define ADF_DH895XCC_ERRSSMSH_EN BIT(3) 36 #define ADF_DH895XCC_ERRSOU3 (0x3A000 + 0x0C) 37 #define ADF_DH895XCC_ERRSOU5 (0x3A000 + 0xD8) 38 /* BIT(2) enables the logging of push/pull data errors. */ 39 #define ADF_DH895XCC_PPERR_EN (BIT(2)) 40 41 /* Masks for VF2PF interrupts */ 42 #define ADF_DH895XCC_VF2PF1_16 (0xFFFF << 9) 43 #define ADF_DH895XCC_VF2PF17_32 (0xFFFF) 44 #define ADF_DH895XCC_ERRSOU3_VF2PF_L(errsou3) (((errsou3)&0x01FFFE00) >> 9) 45 #define ADF_DH895XCC_ERRSOU5_VF2PF_U(errsou5) (((errsou5)&0x0000FFFF) << 16) 46 #define ADF_DH895XCC_ERRMSK3_VF2PF_L(vf_mask) (((vf_mask)&0xFFFF) << 9) 47 #define ADF_DH895XCC_ERRMSK5_VF2PF_U(vf_mask) ((vf_mask) >> 16) 48 49 /* Masks for correctable error interrupts. */ 50 #define ADF_DH895XCC_ERRMSK0_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 51 #define ADF_DH895XCC_ERRMSK1_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 52 #define ADF_DH895XCC_ERRMSK3_CERR (BIT(7)) 53 #define ADF_DH895XCC_ERRMSK4_CERR (BIT(24) | BIT(16) | BIT(8) | BIT(0)) 54 #define ADF_DH895XCC_ERRMSK5_CERR (0) 55 56 /* Masks for uncorrectable error interrupts. */ 57 #define ADF_DH895XCC_ERRMSK0_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 58 #define ADF_DH895XCC_ERRMSK1_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 59 #define ADF_DH895XCC_ERRMSK3_UERR \ 60 (BIT(8) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(0)) 61 #define ADF_DH895XCC_ERRMSK4_UERR (BIT(25) | BIT(17) | BIT(9) | BIT(1)) 62 #define ADF_DH895XCC_ERRMSK5_UERR (BIT(19) | BIT(18) | BIT(17) | BIT(16)) 63 64 /* RI CPP control */ 65 #define ADF_DH895XCC_RICPPINTCTL (0x3A000 + 0x110) 66 /* 67 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 68 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 69 */ 70 #define ADF_DH895XCC_RICPP_EN (BIT(1) | BIT(0)) 71 72 /* TI CPP control */ 73 #define ADF_DH895XCC_TICPPINTCTL (0x3A400 + 0x138) 74 /* 75 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 76 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 77 */ 78 #define ADF_DH895XCC_TICPP_EN (BIT(1) | BIT(0)) 79 80 /* CFC Uncorrectable Errors */ 81 #define ADF_DH895XCC_CPP_SHAC_ERR_CTRL (0x30000 + 0xC00) 82 /* 83 * BIT(1) enables interrupt. 84 * BIT(0) enables detecting and logging of push/pull data errors. 85 */ 86 #define ADF_DH895XCC_CPP_SHAC_UE (BIT(1) | BIT(0)) 87 88 /* Correctable SecureRAM Error Reg */ 89 #define ADF_DH895XCC_ESRAMCERR (0x3AC00 + 0x00) 90 /* BIT(3) enables fixing and logging of correctable errors. */ 91 #define ADF_DH895XCC_ESRAM_CERR (BIT(3)) 92 93 /* Uncorrectable SecureRAM Error Reg */ 94 #define ADF_DH895XCC_ESRAMUERR (ADF_SECRAMUERR) 95 /* 96 * BIT(17) enables interrupt. 97 * BIT(3) enables detecting and logging of uncorrectable errors. 98 */ 99 #define ADF_DH895XCC_ESRAM_UERR (BIT(17) | BIT(3)) 100 101 /* Miscellaneous Memory Target Errors Register */ 102 /* 103 * BIT(3) enables detecting and logging push/pull data errors. 104 * BIT(2) enables interrupt. 105 */ 106 #define ADF_DH895XCC_TGT_UERR (BIT(3) | BIT(2)) 107 108 #define ADF_DH895XCC_SLICEPWRDOWN(i) ((i)*0x4000 + 0x2C) 109 /* Enabling PKE4-PKE0. */ 110 #define ADF_DH895XCC_MMP_PWR_UP_MSK (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3)) 111 112 /* CPM Uncorrectable Errors */ 113 #define ADF_DH895XCC_INTMASKSSM(i) ((i)*0x4000 + 0x0) 114 /* Disabling interrupts for correctable errors. */ 115 #define ADF_DH895XCC_INTMASKSSM_UERR \ 116 (BIT(11) | BIT(9) | BIT(7) | BIT(5) | BIT(3) | BIT(1)) 117 118 /* MMP */ 119 /* BIT(3) enables correction. */ 120 #define ADF_DH895XCC_CERRSSMMMP_EN (BIT(3)) 121 122 /* BIT(3) enables logging. */ 123 #define ADF_DH895XCC_UERRSSMMMP_EN (BIT(3)) 124 125 #define ADF_DH895XCC_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i)*0x04)) 126 #define ADF_DH895XCC_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i)*0x04)) 127 128 /* Arbiter configuration */ 129 #define ADF_DH895XCC_ARB_OFFSET 0x30000 130 #define ADF_DH895XCC_ARB_WRK_2_SER_MAP_OFFSET 0x180 131 #define ADF_DH895XCC_ARB_WQCFG_OFFSET 0x100 132 133 /* Admin Interface Reg Offset */ 134 #define ADF_DH895XCC_ADMINMSGUR_OFFSET (0x3A000 + 0x574) 135 #define ADF_DH895XCC_ADMINMSGLR_OFFSET (0x3A000 + 0x578) 136 #define ADF_DH895XCC_MAILBOX_BASE_OFFSET 0x20970 137 138 /* FW names */ 139 #define ADF_DH895XCC_FW "qat_dh895xcc_fw" 140 #define ADF_DH895XCC_MMP "qat_dh895xcc_mmp_fw" 141 142 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 143 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data); 144 #define ADF_DH895XCC_AE_FREQ (933 * 1000000) 145 #endif 146