1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5
6 #include "qat_freebsd.h"
7 #include "adf_cfg_common.h"
8 #include "adf_pfvf_msg.h"
9
10 #include "opt_qat.h"
11
12 #define ADF_CFG_NUM_SERVICES 4
13
14 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
15 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
16 #define ADF_C62X_DEVICE_NAME "c6xx"
17 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
18 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
19 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
20 #define ADF_200XX_DEVICE_NAME "200xx"
21 #define ADF_200XXVF_DEVICE_NAME "200xxvf"
22 #define ADF_C4XXX_DEVICE_NAME "c4xxx"
23 #define ADF_C4XXXVF_DEVICE_NAME "c4xxxvf"
24 #define ADF_4XXX_DEVICE_NAME "4xxx"
25 #define ADF_4XXXVF_DEVICE_NAME "4xxxvf"
26 #define ADF_DH895XCC_PCI_DEVICE_ID 0x435
27 #define ADF_DH895XCCIOV_PCI_DEVICE_ID 0x443
28 #define ADF_C62X_PCI_DEVICE_ID 0x37c8
29 #define ADF_C62XIOV_PCI_DEVICE_ID 0x37c9
30 #define ADF_C3XXX_PCI_DEVICE_ID 0x19e2
31 #define ADF_C3XXXIOV_PCI_DEVICE_ID 0x19e3
32 #define ADF_200XX_PCI_DEVICE_ID 0x18ee
33 #define ADF_200XXIOV_PCI_DEVICE_ID 0x18ef
34 #define ADF_D15XX_PCI_DEVICE_ID 0x6f54
35 #define ADF_D15XXIOV_PCI_DEVICE_ID 0x6f55
36 #define ADF_C4XXX_PCI_DEVICE_ID 0x18a0
37 #define ADF_C4XXXIOV_PCI_DEVICE_ID 0x18a1
38 #define ADF_4XXX_PCI_DEVICE_ID 0x4940
39 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
40 #define ADF_401XX_PCI_DEVICE_ID 0x4942
41 #define ADF_401XXIOV_PCI_DEVICE_ID 0x4943
42 #define ADF_402XX_PCI_DEVICE_ID 0x4944
43 #define ADF_402XXIOV_PCI_DEVICE_ID 0x4945
44
45 #define IS_QAT_GEN3(ID) ({ (ID == ADF_C4XXX_PCI_DEVICE_ID); })
46 static inline bool
IS_QAT_GEN4(const unsigned int id)47 IS_QAT_GEN4(const unsigned int id)
48 {
49 return (id == ADF_4XXX_PCI_DEVICE_ID || id == ADF_401XX_PCI_DEVICE_ID ||
50 id == ADF_402XX_PCI_DEVICE_ID ||
51 id == ADF_402XXIOV_PCI_DEVICE_ID ||
52 id == ADF_4XXXIOV_PCI_DEVICE_ID ||
53 id == ADF_401XXIOV_PCI_DEVICE_ID);
54 }
55
56 #define IS_QAT_GEN3_OR_GEN4(ID) (IS_QAT_GEN3(ID) || IS_QAT_GEN4(ID))
57 #define ADF_VF2PF_SET_SIZE 32
58 #define ADF_MAX_VF2PF_SET 4
59 #define ADF_VF2PF_SET_OFFSET(set_nr) ((set_nr)*ADF_VF2PF_SET_SIZE)
60 #define ADF_VF2PF_VFNR_TO_SET(vf_nr) ((vf_nr) / ADF_VF2PF_SET_SIZE)
61 #define ADF_VF2PF_VFNR_TO_MASK(vf_nr) \
62 ({ \
63 u32 vf_nr_ = (vf_nr); \
64 BIT((vf_nr_)-ADF_VF2PF_SET_SIZE *ADF_VF2PF_VFNR_TO_SET( \
65 vf_nr_)); \
66 })
67
68 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
69 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
70 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
71 #define ADF_PCI_MAX_BARS 3
72 #define ADF_DEVICE_NAME_LENGTH 32
73 #define ADF_ETR_MAX_RINGS_PER_BANK 16
74 #define ADF_MAX_MSIX_VECTOR_NAME 32
75 #define ADF_DEVICE_NAME_PREFIX "qat_"
76 #define ADF_STOP_RETRY 50
77 #define ADF_NUM_THREADS_PER_AE (8)
78 #define ADF_AE_ADMIN_THREAD (7)
79 #define ADF_NUM_PKE_STRAND (2)
80 #define ADF_AE_STRAND0_THREAD (8)
81 #define ADF_AE_STRAND1_THREAD (9)
82 #define ADF_CFG_NUM_SERVICES 4
83 #define ADF_SRV_TYPE_BIT_LEN 3
84 #define ADF_SRV_TYPE_MASK 0x7
85 #define ADF_RINGS_PER_SRV_TYPE 2
86 #define ADF_THRD_ABILITY_BIT_LEN 4
87 #define ADF_THRD_ABILITY_MASK 0xf
88 #define ADF_VF_OFFSET 0x8
89 #define ADF_MAX_FUNC_PER_DEV 0x7
90 #define ADF_PCI_DEV_OFFSET 0x3
91
92 #define ADF_SRV_TYPE_BIT_LEN 3
93 #define ADF_SRV_TYPE_MASK 0x7
94
95 #define GET_SRV_TYPE(ena_srv_mask, srv) \
96 (((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK)
97
98 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.csr_ops)
99 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.pfvf_ops)
100 #define ADF_DEFAULT_RING_TO_SRV_MAP \
101 (CRYPTO | CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
102 NA << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
103 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
104
105 enum adf_accel_capabilities {
106 ADF_ACCEL_CAPABILITIES_NULL = 0,
107 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
108 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
109 ADF_ACCEL_CAPABILITIES_CIPHER = 4,
110 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
111 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
112 ADF_ACCEL_CAPABILITIES_DEPRECATED = 64,
113 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
114 };
115
116 struct adf_bar {
117 rman_res_t base_addr;
118 struct resource *virt_addr;
119 rman_res_t size;
120 } __packed;
121
122 struct adf_accel_msix {
123 struct msix_entry *entries;
124 u32 num_entries;
125 } __packed;
126
127 struct adf_accel_pci {
128 device_t pci_dev;
129 struct adf_accel_msix msix_entries;
130 struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
131 uint8_t revid;
132 uint8_t sku;
133 int node;
134 } __packed;
135
136 enum dev_state { DEV_DOWN = 0, DEV_UP };
137
138 enum dev_sku_info {
139 DEV_SKU_1 = 0,
140 DEV_SKU_2,
141 DEV_SKU_3,
142 DEV_SKU_4,
143 DEV_SKU_VF,
144 DEV_SKU_1_CY,
145 DEV_SKU_2_CY,
146 DEV_SKU_3_CY,
147 DEV_SKU_UNKNOWN
148 };
149
150 static inline const char *
get_sku_info(enum dev_sku_info info)151 get_sku_info(enum dev_sku_info info)
152 {
153 switch (info) {
154 case DEV_SKU_1:
155 return "SKU1";
156 case DEV_SKU_1_CY:
157 return "SKU1CY";
158 case DEV_SKU_2:
159 return "SKU2";
160 case DEV_SKU_2_CY:
161 return "SKU2CY";
162 case DEV_SKU_3:
163 return "SKU3";
164 case DEV_SKU_3_CY:
165 return "SKU3CY";
166 case DEV_SKU_4:
167 return "SKU4";
168 case DEV_SKU_VF:
169 return "SKUVF";
170 case DEV_SKU_UNKNOWN:
171 default:
172 break;
173 }
174 return "Unknown SKU";
175 }
176
177 enum adf_accel_unit_services {
178 ADF_ACCEL_SERVICE_NULL = 0,
179 ADF_ACCEL_INLINE_CRYPTO = 1,
180 ADF_ACCEL_CRYPTO = 2,
181 ADF_ACCEL_COMPRESSION = 4,
182 ADF_ACCEL_ASYM = 8,
183 ADF_ACCEL_ADMIN = 16
184 };
185
186 struct adf_ae_info {
187 u32 num_asym_thd;
188 u32 num_sym_thd;
189 u32 num_dc_thd;
190 } __packed;
191
192 struct adf_accel_unit {
193 u8 au_mask;
194 u32 accel_mask;
195 u64 ae_mask;
196 u64 comp_ae_mask;
197 u32 num_ae;
198 enum adf_accel_unit_services services;
199 } __packed;
200
201 struct adf_accel_unit_info {
202 u32 inline_ingress_msk;
203 u32 inline_egress_msk;
204 u32 sym_ae_msk;
205 u32 asym_ae_msk;
206 u32 dc_ae_msk;
207 u8 num_cy_au;
208 u8 num_dc_au;
209 u8 num_asym_au;
210 u8 num_inline_au;
211 struct adf_accel_unit *au;
212 const struct adf_ae_info *ae_info;
213 } __packed;
214
215 struct adf_hw_aram_info {
216 /* Inline Egress mask. "1" = AE is working with egress traffic */
217 u32 inline_direction_egress_mask;
218 /* Inline congestion managmenet profiles set in config file */
219 u32 inline_congest_mngt_profile;
220 /* Initialise CY AE mask, "1" = AE is used for CY operations */
221 u32 cy_ae_mask;
222 /* Initialise DC AE mask, "1" = AE is used for DC operations */
223 u32 dc_ae_mask;
224 /* Number of long words used to define the ARAM regions */
225 u32 num_aram_lw_entries;
226 /* ARAM region definitions */
227 u32 mmp_region_size;
228 u32 mmp_region_offset;
229 u32 skm_region_size;
230 u32 skm_region_offset;
231 /*
232 * Defines size and offset of compression intermediate buffers stored
233 * in ARAM (device's on-chip memory).
234 */
235 u32 inter_buff_aram_region_size;
236 u32 inter_buff_aram_region_offset;
237 u32 sadb_region_size;
238 u32 sadb_region_offset;
239 } __packed;
240
241 struct adf_hw_device_class {
242 const char *name;
243 const enum adf_device_type type;
244 uint32_t instances;
245 } __packed;
246
247 struct arb_info {
248 u32 arbiter_offset;
249 u32 wrk_thd_2_srv_arb_map;
250 u32 wrk_cfg_offset;
251 } __packed;
252
253 struct admin_info {
254 u32 admin_msg_ur;
255 u32 admin_msg_lr;
256 u32 mailbox_offset;
257 } __packed;
258
259 struct adf_hw_csr_ops {
260 u64 (*build_csr_ring_base_addr)(bus_addr_t addr, u32 size);
261 u32 (*read_csr_ring_head)(struct resource *csr_base_addr,
262 u32 bank,
263 u32 ring);
264 void (*write_csr_ring_head)(struct resource *csr_base_addr,
265 u32 bank,
266 u32 ring,
267 u32 value);
268 u32 (*read_csr_ring_tail)(struct resource *csr_base_addr,
269 u32 bank,
270 u32 ring);
271 void (*write_csr_ring_tail)(struct resource *csr_base_addr,
272 u32 bank,
273 u32 ring,
274 u32 value);
275 u32 (*read_csr_e_stat)(struct resource *csr_base_addr, u32 bank);
276 void (*write_csr_ring_config)(struct resource *csr_base_addr,
277 u32 bank,
278 u32 ring,
279 u32 value);
280 bus_addr_t (*read_csr_ring_base)(struct resource *csr_base_addr,
281 u32 bank,
282 u32 ring);
283 void (*write_csr_ring_base)(struct resource *csr_base_addr,
284 u32 bank,
285 u32 ring,
286 bus_addr_t addr);
287 void (*write_csr_int_flag)(struct resource *csr_base_addr,
288 u32 bank,
289 u32 value);
290 void (*write_csr_int_srcsel)(struct resource *csr_base_addr, u32 bank);
291 void (*write_csr_int_col_en)(struct resource *csr_base_addr,
292 u32 bank,
293 u32 value);
294 void (*write_csr_int_col_ctl)(struct resource *csr_base_addr,
295 u32 bank,
296 u32 value);
297 void (*write_csr_int_flag_and_col)(struct resource *csr_base_addr,
298 u32 bank,
299 u32 value);
300 u32 (*read_csr_ring_srv_arb_en)(struct resource *csr_base_addr,
301 u32 bank);
302 void (*write_csr_ring_srv_arb_en)(struct resource *csr_base_addr,
303 u32 bank,
304 u32 value);
305 u32 (*get_src_sel_mask)(void);
306 u32 (*get_int_col_ctl_enable_mask)(void);
307 u32 (*get_bank_irq_mask)(u32 irq_mask);
308 };
309
310 struct adf_cfg_device_data;
311 struct adf_accel_dev;
312 struct adf_etr_data;
313 struct adf_etr_ring_data;
314
315 struct adf_pfvf_ops {
316 int (*enable_comms)(struct adf_accel_dev *accel_dev);
317 u32 (*get_pf2vf_offset)(u32 i);
318 u32 (*get_vf2pf_offset)(u32 i);
319 void (*enable_vf2pf_interrupts)(struct resource *pmisc_addr,
320 u32 vf_mask);
321 void (*disable_all_vf2pf_interrupts)(struct resource *pmisc_addr);
322 u32 (*disable_pending_vf2pf_interrupts)(struct resource *pmisc_addr);
323 int (*send_msg)(struct adf_accel_dev *accel_dev,
324 struct pfvf_message msg,
325 u32 pfvf_offset,
326 struct mutex *csr_lock);
327 struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev,
328 u32 pfvf_offset,
329 u8 compat_ver);
330 };
331
332 struct adf_hw_csr_info {
333 struct adf_hw_csr_ops csr_ops;
334 struct adf_pfvf_ops pfvf_ops;
335 u32 csr_addr_offset;
336 u32 ring_bundle_size;
337 u32 bank_int_flag_clear_mask;
338 u32 num_rings_per_int_srcsel;
339 u32 arb_enable_mask;
340 };
341
342 struct adf_hw_device_data {
343 struct adf_hw_device_class *dev_class;
344 uint32_t (*get_accel_mask)(struct adf_accel_dev *accel_dev);
345 uint32_t (*get_ae_mask)(struct adf_accel_dev *accel_dev);
346 uint32_t (*get_sram_bar_id)(struct adf_hw_device_data *self);
347 uint32_t (*get_misc_bar_id)(struct adf_hw_device_data *self);
348 uint32_t (*get_etr_bar_id)(struct adf_hw_device_data *self);
349 uint32_t (*get_num_aes)(struct adf_hw_device_data *self);
350 uint32_t (*get_num_accels)(struct adf_hw_device_data *self);
351 void (*notify_and_wait_ethernet)(struct adf_accel_dev *accel_dev);
352 bool (*get_eth_doorbell_msg)(struct adf_accel_dev *accel_dev);
353 void (*get_arb_info)(struct arb_info *arb_csrs_info);
354 void (*get_admin_info)(struct admin_info *admin_csrs_info);
355 void (*get_errsou_offset)(u32 *errsou3, u32 *errsou5);
356 uint32_t (*get_num_accel_units)(struct adf_hw_device_data *self);
357 int (*init_accel_units)(struct adf_accel_dev *accel_dev);
358 void (*exit_accel_units)(struct adf_accel_dev *accel_dev);
359 uint32_t (*get_clock_speed)(struct adf_hw_device_data *self);
360 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
361 bool (*check_prod_sku)(struct adf_accel_dev *accel_dev);
362 int (*alloc_irq)(struct adf_accel_dev *accel_dev);
363 void (*free_irq)(struct adf_accel_dev *accel_dev);
364 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
365 int (*check_uncorrectable_error)(struct adf_accel_dev *accel_dev);
366 void (*print_err_registers)(struct adf_accel_dev *accel_dev);
367 void (*disable_error_interrupts)(struct adf_accel_dev *accel_dev);
368 int (*init_ras)(struct adf_accel_dev *accel_dev);
369 void (*exit_ras)(struct adf_accel_dev *accel_dev);
370 void (*disable_arb)(struct adf_accel_dev *accel_dev);
371 void (*update_ras_errors)(struct adf_accel_dev *accel_dev, int error);
372 bool (*ras_interrupts)(struct adf_accel_dev *accel_dev,
373 bool *reset_required);
374 int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
375 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
376 int (*send_admin_init)(struct adf_accel_dev *accel_dev);
377 void (*set_asym_rings_mask)(struct adf_accel_dev *accel_dev);
378 int (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev,
379 u16 *ring_to_svc_map);
380 uint32_t (*get_accel_cap)(struct adf_accel_dev *accel_dev);
381 int (*init_arb)(struct adf_accel_dev *accel_dev);
382 void (*exit_arb)(struct adf_accel_dev *accel_dev);
383 void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
384 const uint32_t **cfg);
385 int (*init_device)(struct adf_accel_dev *accel_dev);
386 int (*get_heartbeat_status)(struct adf_accel_dev *accel_dev);
387 int (*int_timer_init)(struct adf_accel_dev *accel_dev);
388 void (*int_timer_exit)(struct adf_accel_dev *accel_dev);
389 uint32_t (*get_ae_clock)(struct adf_hw_device_data *self);
390 uint32_t (*get_hb_clock)(struct adf_hw_device_data *self);
391 void (*disable_iov)(struct adf_accel_dev *accel_dev);
392 void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
393 bool enable);
394 void (*enable_ints)(struct adf_accel_dev *accel_dev);
395 bool (*check_slice_hang)(struct adf_accel_dev *accel_dev);
396 int (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
397 void (*enable_pf2vf_interrupt)(struct adf_accel_dev *accel_dev);
398 void (*disable_pf2vf_interrupt)(struct adf_accel_dev *accel_dev);
399 int (*interrupt_active_pf2vf)(struct adf_accel_dev *accel_dev);
400 int (*get_int_active_bundles)(struct adf_accel_dev *accel_dev);
401 void (*reset_device)(struct adf_accel_dev *accel_dev);
402 void (*reset_hw_units)(struct adf_accel_dev *accel_dev);
403 int (*measure_clock)(struct adf_accel_dev *accel_dev);
404 void (*restore_device)(struct adf_accel_dev *accel_dev);
405 uint32_t (*get_obj_cfg_ae_mask)(struct adf_accel_dev *accel_dev,
406 enum adf_accel_unit_services services);
407 enum adf_accel_unit_services (
408 *get_service_type)(struct adf_accel_dev *accel_dev, s32 obj_num);
409 int (*add_pke_stats)(struct adf_accel_dev *accel_dev);
410 void (*remove_pke_stats)(struct adf_accel_dev *accel_dev);
411 int (*add_misc_error)(struct adf_accel_dev *accel_dev);
412 int (*count_ras_event)(struct adf_accel_dev *accel_dev,
413 u32 *ras_event,
414 char *aeidstr);
415 void (*remove_misc_error)(struct adf_accel_dev *accel_dev);
416 int (*configure_accel_units)(struct adf_accel_dev *accel_dev);
417 int (*ring_pair_reset)(struct adf_accel_dev *accel_dev,
418 u32 bank_number);
419 void (*config_ring_irq)(struct adf_accel_dev *accel_dev,
420 u32 bank_number,
421 u16 ring_mask);
422 uint32_t (*get_objs_num)(struct adf_accel_dev *accel_dev);
423 const char *(*get_obj_name)(struct adf_accel_dev *accel_dev,
424 enum adf_accel_unit_services services);
425 void (*pre_reset)(struct adf_accel_dev *accel_dev);
426 void (*post_reset)(struct adf_accel_dev *accel_dev);
427 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
428 void (*get_ring_svc_map_data)(int ring_pair_index,
429 u16 ring_to_svc_map,
430 u8 *serv_type,
431 int *ring_index,
432 int *num_rings_per_srv,
433 int bundle_num);
434 struct adf_hw_csr_info csr_info;
435 const char *fw_name;
436 const char *fw_mmp_name;
437 bool reset_ack;
438 uint32_t fuses;
439 uint32_t accel_capabilities_mask;
440 uint32_t instance_id;
441 uint16_t accel_mask;
442 u32 aerucm_mask;
443 u32 ae_mask;
444 u32 admin_ae_mask;
445 u32 service_mask;
446 u32 service_to_load_mask;
447 u32 heartbeat_ctr_num;
448 uint16_t tx_rings_mask;
449 uint8_t tx_rx_gap;
450 uint8_t num_banks;
451 u8 num_rings_per_bank;
452 uint8_t num_accel;
453 uint8_t num_logical_accel;
454 uint8_t num_engines;
455 bool get_ring_to_svc_done;
456 int (*get_storage_enabled)(struct adf_accel_dev *accel_dev,
457 uint32_t *storage_enabled);
458 u8 query_storage_cap;
459 u32 clock_frequency;
460 u8 storage_enable;
461 u32 extended_dc_capabilities;
462 int (*config_device)(struct adf_accel_dev *accel_dev);
463 u32 asym_ae_active_thd_mask;
464 u16 asym_rings_mask;
465 int (*get_fw_image_type)(struct adf_accel_dev *accel_dev,
466 enum adf_cfg_fw_image_type *fw_image_type);
467 u16 ring_to_svc_map;
468 } __packed;
469
470 /* helper enum for performing CSR operations */
471 enum operation {
472 AND,
473 OR,
474 };
475
476 /* 32-bit CSR write macro */
477 #define ADF_CSR_WR(csr_base, csr_offset, val) \
478 bus_write_4(csr_base, csr_offset, val)
479
480 /* 64-bit CSR write macro */
481 #ifdef __x86_64__
482 #define ADF_CSR_WR64(csr_base, csr_offset, val) \
483 bus_write_8(csr_base, csr_offset, val)
484 #else
485 static __inline void
adf_csr_wr64(struct resource * csr_base,bus_size_t offset,uint64_t value)486 adf_csr_wr64(struct resource *csr_base, bus_size_t offset, uint64_t value)
487 {
488 bus_write_4(csr_base, offset, (uint32_t)value);
489 bus_write_4(csr_base, offset + 4, (uint32_t)(value >> 32));
490 }
491 #define ADF_CSR_WR64(csr_base, csr_offset, val) \
492 adf_csr_wr64(csr_base, csr_offset, val)
493 #endif
494
495 /* 32-bit CSR read macro */
496 #define ADF_CSR_RD(csr_base, csr_offset) bus_read_4(csr_base, csr_offset)
497
498 /* 64-bit CSR read macro */
499 #ifdef __x86_64__
500 #define ADF_CSR_RD64(csr_base, csr_offset) bus_read_8(csr_base, csr_offset)
501 #else
502 static __inline uint64_t
adf_csr_rd64(struct resource * csr_base,bus_size_t offset)503 adf_csr_rd64(struct resource *csr_base, bus_size_t offset)
504 {
505 return (((uint64_t)bus_read_4(csr_base, offset)) |
506 (((uint64_t)bus_read_4(csr_base, offset + 4)) << 32));
507 }
508 #define ADF_CSR_RD64(csr_base, csr_offset) adf_csr_rd64(csr_base, csr_offset)
509 #endif
510
511 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev)
512 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
513 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
514 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
515 #define GET_DEV_SKU(accel_dev) (accel_dev->accel_pci_dev.sku)
516 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
517 (GET_HW_DATA(accel_dev)->num_rings_per_bank)
518 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
519 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
520 #define GET_SRV_TYPE(ena_srv_mask, srv) \
521 (((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK)
522 #define SET_ASYM_MASK(asym_mask, srv) \
523 ({ \
524 typeof(srv) srv_ = (srv); \
525 (asym_mask) |= ((1 << (srv_)*ADF_RINGS_PER_SRV_TYPE) | \
526 (1 << ((srv_)*ADF_RINGS_PER_SRV_TYPE + 1))); \
527 })
528
529 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
530 (GET_HW_DATA(accel_dev)->num_rings_per_bank)
531 #define GET_MAX_PROCESSES(accel_dev) \
532 ({ \
533 typeof(accel_dev) dev = (accel_dev); \
534 (GET_MAX_BANKS(dev) * (GET_NUM_RINGS_PER_BANK(dev) / 2)); \
535 })
536 #define GET_DU_TABLE(accel_dev) (accel_dev->du_table)
537
538 static inline void
adf_csr_fetch_and_and(struct resource * csr,size_t offs,unsigned long mask)539 adf_csr_fetch_and_and(struct resource *csr, size_t offs, unsigned long mask)
540 {
541 unsigned int val = ADF_CSR_RD(csr, offs);
542
543 val &= mask;
544 ADF_CSR_WR(csr, offs, val);
545 }
546
547 static inline void
adf_csr_fetch_and_or(struct resource * csr,size_t offs,unsigned long mask)548 adf_csr_fetch_and_or(struct resource *csr, size_t offs, unsigned long mask)
549 {
550 unsigned int val = ADF_CSR_RD(csr, offs);
551
552 val |= mask;
553 ADF_CSR_WR(csr, offs, val);
554 }
555
556 static inline void
adf_csr_fetch_and_update(enum operation op,struct resource * csr,size_t offs,unsigned long mask)557 adf_csr_fetch_and_update(enum operation op,
558 struct resource *csr,
559 size_t offs,
560 unsigned long mask)
561 {
562 switch (op) {
563 case AND:
564 adf_csr_fetch_and_and(csr, offs, mask);
565 break;
566 case OR:
567 adf_csr_fetch_and_or(csr, offs, mask);
568 break;
569 }
570 }
571
572 struct pfvf_stats {
573 struct dentry *stats_file;
574 /* Messages put in CSR */
575 unsigned int tx;
576 /* Messages read from CSR */
577 unsigned int rx;
578 /* Interrupt fired but int bit was clear */
579 unsigned int spurious;
580 /* Block messages sent */
581 unsigned int blk_tx;
582 /* Block messages received */
583 unsigned int blk_rx;
584 /* Blocks received with CRC errors */
585 unsigned int crc_err;
586 /* CSR in use by other side */
587 unsigned int busy;
588 /* Receiver did not acknowledge */
589 unsigned int no_ack;
590 /* Collision detected */
591 unsigned int collision;
592 /* Couldn't send a response */
593 unsigned int tx_timeout;
594 /* Didn't receive a response */
595 unsigned int rx_timeout;
596 /* Responses received */
597 unsigned int rx_rsp;
598 /* Messages re-transmitted */
599 unsigned int retry;
600 /* Event put timeout */
601 unsigned int event_timeout;
602 };
603
604 #define NUM_PFVF_COUNTERS 14
605
606 void adf_get_admin_info(struct admin_info *admin_csrs_info);
607 struct adf_admin_comms {
608 bus_addr_t phy_addr;
609 bus_addr_t const_tbl_addr;
610 bus_addr_t aram_map_phys_addr;
611 bus_addr_t phy_hb_addr;
612 bus_dmamap_t aram_map;
613 bus_dmamap_t const_tbl_map;
614 bus_dmamap_t hb_map;
615 char *virt_addr;
616 char *virt_hb_addr;
617 struct resource *mailbox_addr;
618 struct sx lock;
619 struct bus_dmamem dma_mem;
620 struct bus_dmamem dma_hb;
621 };
622
623 struct icp_qat_fw_loader_handle;
624 struct adf_fw_loader_data {
625 struct icp_qat_fw_loader_handle *fw_loader;
626 const struct firmware *uof_fw;
627 const struct firmware *mmp_fw;
628 };
629
630 struct adf_accel_vf_info {
631 struct adf_accel_dev *accel_dev;
632 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
633 u32 vf_nr;
634 bool init;
635 u8 compat_ver;
636 struct pfvf_stats pfvf_counters;
637 };
638
639 struct adf_fw_versions {
640 u8 fw_version_major;
641 u8 fw_version_minor;
642 u8 fw_version_patch;
643 u8 mmp_version_major;
644 u8 mmp_version_minor;
645 u8 mmp_version_patch;
646 };
647
648 struct adf_int_timer {
649 struct adf_accel_dev *accel_dev;
650 struct workqueue_struct *timer_irq_wq;
651 struct timer_list timer;
652 u32 timeout_val;
653 u32 int_cnt;
654 bool enabled;
655 };
656
657 #define ADF_COMPAT_CHECKER_MAX 8
658 typedef int (*adf_iov_compat_checker_t)(struct adf_accel_dev *accel_dev,
659 u8 vf_compat_ver);
660 struct adf_accel_compat_manager {
661 u8 num_chker;
662 adf_iov_compat_checker_t iov_compat_checkers[ADF_COMPAT_CHECKER_MAX];
663 };
664
665 struct adf_heartbeat;
666 struct adf_accel_dev {
667 struct adf_hw_aram_info *aram_info;
668 struct adf_accel_unit_info *au_info;
669 struct adf_etr_data *transport;
670 struct adf_hw_device_data *hw_device;
671 struct adf_cfg_device_data *cfg;
672 struct adf_fw_loader_data *fw_loader;
673 struct adf_admin_comms *admin;
674 struct adf_uio_control_accel *accel;
675 struct adf_heartbeat *heartbeat;
676 struct adf_int_timer *int_timer;
677 struct adf_fw_versions fw_versions;
678 unsigned int autoreset_on_error;
679 struct adf_fw_counters_data *fw_counters_data;
680 struct sysctl_oid *debugfs_ae_config;
681 struct list_head crypto_list;
682 atomic_t *ras_counters;
683 unsigned long status;
684 atomic_t ref_count;
685 bus_dma_tag_t dma_tag;
686 struct sysctl_ctx_list sysctl_ctx;
687 struct sysctl_oid *ras_correctable;
688 struct sysctl_oid *ras_uncorrectable;
689 struct sysctl_oid *ras_fatal;
690 struct sysctl_oid *ras_reset;
691 struct sysctl_oid *pke_replay_dbgfile;
692 struct sysctl_oid *misc_error_dbgfile;
693 struct sysctl_oid *fw_version_oid;
694 struct sysctl_oid *mmp_version_oid;
695 struct sysctl_oid *hw_version_oid;
696 struct sysctl_oid *cnv_error_oid;
697 struct list_head list;
698 struct adf_accel_pci accel_pci_dev;
699 struct adf_accel_compat_manager *cm;
700 u8 compat_ver;
701 #ifdef QAT_DISABLE_SAFE_DC_MODE
702 struct sysctl_oid *safe_dc_mode;
703 u8 disable_safe_dc_mode;
704 #endif /* QAT_DISABLE_SAFE_DC_MODE */
705 union {
706 struct {
707 /* vf_info is non-zero when SR-IOV is init'ed */
708 struct adf_accel_vf_info *vf_info;
709 int num_vfs;
710 } pf;
711 struct {
712 bool irq_enabled;
713 struct resource *irq;
714 void *cookie;
715 struct task pf2vf_bh_tasklet;
716 struct mutex vf2pf_lock; /* protect CSR access */
717 struct completion msg_received;
718 struct pfvf_message
719 response; /* temp field holding pf2vf response */
720 enum ring_reset_result rpreset_sts;
721 struct mutex rpreset_lock; /* protect rpreset_sts */
722 struct pfvf_stats pfvf_counters;
723 u8 pf_compat_ver;
724 } vf;
725 } u1;
726 bool is_vf;
727 u32 accel_id;
728 void *lac_dev;
729 struct mutex lock; /* protect accel_dev during start/stop e.t.c */
730 };
731 #endif
732