1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Analog Devices AD7768-1 SPI ADC driver
4 *
5 * Copyright 2017 Analog Devices Inc.
6 */
7 #include <linux/array_size.h>
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interrupt.h>
17 #include <linux/minmax.h>
18 #include <linux/module.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/sysfs.h>
23 #include <linux/spi/spi.h>
24 #include <linux/unaligned.h>
25 #include <linux/units.h>
26 #include <linux/util_macros.h>
27
28 #include <linux/iio/buffer.h>
29 #include <linux/iio/iio.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/iio/trigger_consumer.h>
34
35 #include <dt-bindings/iio/adc/adi,ad7768-1.h>
36
37 /* AD7768 registers definition */
38 #define AD7768_REG_CHIP_TYPE 0x3
39 #define AD7768_REG_PROD_ID_L 0x4
40 #define AD7768_REG_PROD_ID_H 0x5
41 #define AD7768_REG_CHIP_GRADE 0x6
42 #define AD7768_REG_SCRATCH_PAD 0x0A
43 #define AD7768_REG_VENDOR_L 0x0C
44 #define AD7768_REG_VENDOR_H 0x0D
45 #define AD7768_REG_INTERFACE_FORMAT 0x14
46 #define AD7768_REG_POWER_CLOCK 0x15
47 #define AD7768_REG_ANALOG 0x16
48 #define AD7768_REG_ANALOG2 0x17
49 #define AD7768_REG_CONVERSION 0x18
50 #define AD7768_REG_DIGITAL_FILTER 0x19
51 #define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A
52 #define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B
53 #define AD7768_REG_DUTY_CYCLE_RATIO 0x1C
54 #define AD7768_REG_SYNC_RESET 0x1D
55 #define AD7768_REG_GPIO_CONTROL 0x1E
56 #define AD7768_REG_GPIO_WRITE 0x1F
57 #define AD7768_REG_GPIO_READ 0x20
58 #define AD7768_REG_OFFSET_HI 0x21
59 #define AD7768_REG_OFFSET_MID 0x22
60 #define AD7768_REG_OFFSET_LO 0x23
61 #define AD7768_REG_GAIN_HI 0x24
62 #define AD7768_REG_GAIN_MID 0x25
63 #define AD7768_REG_GAIN_LO 0x26
64 #define AD7768_REG_SPI_DIAG_ENABLE 0x28
65 #define AD7768_REG_ADC_DIAG_ENABLE 0x29
66 #define AD7768_REG_DIG_DIAG_ENABLE 0x2A
67 #define AD7768_REG24_ADC_DATA 0x2C
68 #define AD7768_REG_MASTER_STATUS 0x2D
69 #define AD7768_REG_SPI_DIAG_STATUS 0x2E
70 #define AD7768_REG_ADC_DIAG_STATUS 0x2F
71 #define AD7768_REG_DIG_DIAG_STATUS 0x30
72 #define AD7768_REG_MCLK_COUNTER 0x31
73 #define AD7768_REG_COEFF_CONTROL 0x32
74 #define AD7768_REG24_COEFF_DATA 0x33
75 #define AD7768_REG_ACCESS_KEY 0x34
76
77 /* AD7768_REG_POWER_CLOCK */
78 #define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4)
79 #define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x)
80 #define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0)
81 #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x)
82
83 /* AD7768_REG_DIGITAL_FILTER */
84 #define AD7768_DIG_FIL_EN_60HZ_REJ BIT(7)
85 #define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4)
86 #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x)
87 #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0)
88 #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x)
89
90 /* AD7768_REG_CONVERSION */
91 #define AD7768_CONV_MODE_MSK GENMASK(2, 0)
92 #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x)
93
94 /* AD7768_REG_ANALOG2 */
95 #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0)
96 #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (x))
97
98 /* AD7768_REG_GPIO_CONTROL */
99 #define AD7768_GPIO_UNIVERSAL_EN BIT(7)
100 #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0)
101
102 /* AD7768_REG_GPIO_WRITE */
103 #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0)
104
105 /* AD7768_REG_GPIO_READ */
106 #define AD7768_GPIO_READ_MSK GENMASK(3, 0)
107
108 #define AD7768_VCM_OFF 0x07
109
110 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0
111
112 #define AD7768_MAX_CHANNELS 1
113
114 enum ad7768_conv_mode {
115 AD7768_CONTINUOUS,
116 AD7768_ONE_SHOT,
117 AD7768_SINGLE,
118 AD7768_PERIODIC,
119 AD7768_STANDBY
120 };
121
122 enum ad7768_pwrmode {
123 AD7768_ECO_MODE = 0,
124 AD7768_MED_MODE = 2,
125 AD7768_FAST_MODE = 3
126 };
127
128 enum ad7768_mclk_div {
129 AD7768_MCLK_DIV_16,
130 AD7768_MCLK_DIV_8,
131 AD7768_MCLK_DIV_4,
132 AD7768_MCLK_DIV_2
133 };
134
135 enum ad7768_filter_type {
136 AD7768_FILTER_SINC5,
137 AD7768_FILTER_SINC3,
138 AD7768_FILTER_WIDEBAND,
139 AD7768_FILTER_SINC3_REJ60,
140 };
141
142 enum ad7768_filter_regval {
143 AD7768_FILTER_REGVAL_SINC5 = 0,
144 AD7768_FILTER_REGVAL_SINC5_X8 = 1,
145 AD7768_FILTER_REGVAL_SINC5_X16 = 2,
146 AD7768_FILTER_REGVAL_SINC3 = 3,
147 AD7768_FILTER_REGVAL_WIDEBAND = 4,
148 AD7768_FILTER_REGVAL_SINC3_REJ60 = 11,
149 };
150
151 enum ad7768_scan_type {
152 AD7768_SCAN_TYPE_NORMAL,
153 AD7768_SCAN_TYPE_HIGH_SPEED,
154 };
155
156 /* -3dB cutoff frequency multipliers (relative to ODR) for each filter type. */
157 static const int ad7768_filter_3db_odr_multiplier[] = {
158 [AD7768_FILTER_SINC5] = 204, /* 0.204 */
159 [AD7768_FILTER_SINC3] = 262, /* 0.2617 */
160 [AD7768_FILTER_SINC3_REJ60] = 262, /* 0.2617 */
161 [AD7768_FILTER_WIDEBAND] = 433, /* 0.433 */
162 };
163
164 static const int ad7768_mclk_div_rates[] = {
165 16, 8, 4, 2,
166 };
167
168 static const int ad7768_dec_rate_values[8] = {
169 8, 16, 32, 64, 128, 256, 512, 1024,
170 };
171
172 /* Decimation rate range for sinc3 filter */
173 static const int ad7768_sinc3_dec_rate_range[3] = {
174 32, 32, 163840,
175 };
176
177 /*
178 * The AD7768-1 supports three primary filter types:
179 * Sinc5, Sinc3, and Wideband.
180 * However, the filter register values can also encode additional parameters
181 * such as decimation rates and 60Hz rejection. This utility array separates
182 * the filter type from these parameters.
183 */
184 static const int ad7768_filter_regval_to_type[] = {
185 [AD7768_FILTER_REGVAL_SINC5] = AD7768_FILTER_SINC5,
186 [AD7768_FILTER_REGVAL_SINC5_X8] = AD7768_FILTER_SINC5,
187 [AD7768_FILTER_REGVAL_SINC5_X16] = AD7768_FILTER_SINC5,
188 [AD7768_FILTER_REGVAL_SINC3] = AD7768_FILTER_SINC3,
189 [AD7768_FILTER_REGVAL_WIDEBAND] = AD7768_FILTER_WIDEBAND,
190 [AD7768_FILTER_REGVAL_SINC3_REJ60] = AD7768_FILTER_SINC3_REJ60,
191 };
192
193 static const char * const ad7768_filter_enum[] = {
194 [AD7768_FILTER_SINC5] = "sinc5",
195 [AD7768_FILTER_SINC3] = "sinc3",
196 [AD7768_FILTER_WIDEBAND] = "wideband",
197 [AD7768_FILTER_SINC3_REJ60] = "sinc3+rej60",
198 };
199
200 static const struct iio_scan_type ad7768_scan_type[] = {
201 [AD7768_SCAN_TYPE_NORMAL] = {
202 .sign = 's',
203 .realbits = 24,
204 .storagebits = 32,
205 .shift = 8,
206 .endianness = IIO_BE,
207 },
208 [AD7768_SCAN_TYPE_HIGH_SPEED] = {
209 .sign = 's',
210 .realbits = 16,
211 .storagebits = 16,
212 .endianness = IIO_BE,
213 },
214 };
215
216 struct ad7768_state {
217 struct spi_device *spi;
218 struct regmap *regmap;
219 struct regmap *regmap24;
220 struct regulator *vref;
221 struct regulator_dev *vcm_rdev;
222 unsigned int vcm_output_sel;
223 struct clk *mclk;
224 unsigned int mclk_freq;
225 unsigned int mclk_div;
226 unsigned int oversampling_ratio;
227 enum ad7768_filter_type filter_type;
228 unsigned int samp_freq;
229 unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)];
230 unsigned int samp_freq_avail_len;
231 struct completion completion;
232 struct iio_trigger *trig;
233 struct gpio_desc *gpio_sync_in;
234 struct gpio_desc *gpio_reset;
235 const char *labels[AD7768_MAX_CHANNELS];
236 struct gpio_chip gpiochip;
237 bool en_spi_sync;
238 /*
239 * DMA (thus cache coherency maintenance) may require the
240 * transfer buffers to live in their own cache lines.
241 */
242 union {
243 struct {
244 __be32 chan;
245 aligned_s64 timestamp;
246 } scan;
247 __be32 d32;
248 u8 d8[2];
249 } data __aligned(IIO_DMA_MINALIGN);
250 };
251
252 static const struct regmap_range ad7768_regmap_rd_ranges[] = {
253 regmap_reg_range(AD7768_REG_CHIP_TYPE, AD7768_REG_CHIP_GRADE),
254 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
255 regmap_reg_range(AD7768_REG_VENDOR_L, AD7768_REG_VENDOR_H),
256 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GAIN_LO),
257 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
258 regmap_reg_range(AD7768_REG_MASTER_STATUS, AD7768_REG_COEFF_CONTROL),
259 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
260 };
261
262 static const struct regmap_access_table ad7768_regmap_rd_table = {
263 .yes_ranges = ad7768_regmap_rd_ranges,
264 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_rd_ranges),
265 };
266
267 static const struct regmap_range ad7768_regmap_wr_ranges[] = {
268 regmap_reg_range(AD7768_REG_SCRATCH_PAD, AD7768_REG_SCRATCH_PAD),
269 regmap_reg_range(AD7768_REG_INTERFACE_FORMAT, AD7768_REG_GPIO_WRITE),
270 regmap_reg_range(AD7768_REG_OFFSET_HI, AD7768_REG_GAIN_LO),
271 regmap_reg_range(AD7768_REG_SPI_DIAG_ENABLE, AD7768_REG_DIG_DIAG_ENABLE),
272 regmap_reg_range(AD7768_REG_SPI_DIAG_STATUS, AD7768_REG_SPI_DIAG_STATUS),
273 regmap_reg_range(AD7768_REG_COEFF_CONTROL, AD7768_REG_COEFF_CONTROL),
274 regmap_reg_range(AD7768_REG_ACCESS_KEY, AD7768_REG_ACCESS_KEY),
275 };
276
277 static const struct regmap_access_table ad7768_regmap_wr_table = {
278 .yes_ranges = ad7768_regmap_wr_ranges,
279 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap_wr_ranges),
280 };
281
282 static const struct regmap_config ad7768_regmap_config = {
283 .name = "ad7768-1-8",
284 .reg_bits = 8,
285 .val_bits = 8,
286 .read_flag_mask = BIT(6),
287 .rd_table = &ad7768_regmap_rd_table,
288 .wr_table = &ad7768_regmap_wr_table,
289 .max_register = AD7768_REG_ACCESS_KEY,
290 .use_single_write = true,
291 .use_single_read = true,
292 };
293
294 static const struct regmap_range ad7768_regmap24_rd_ranges[] = {
295 regmap_reg_range(AD7768_REG24_ADC_DATA, AD7768_REG24_ADC_DATA),
296 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA),
297 };
298
299 static const struct regmap_access_table ad7768_regmap24_rd_table = {
300 .yes_ranges = ad7768_regmap24_rd_ranges,
301 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_rd_ranges),
302 };
303
304 static const struct regmap_range ad7768_regmap24_wr_ranges[] = {
305 regmap_reg_range(AD7768_REG24_COEFF_DATA, AD7768_REG24_COEFF_DATA),
306 };
307
308 static const struct regmap_access_table ad7768_regmap24_wr_table = {
309 .yes_ranges = ad7768_regmap24_wr_ranges,
310 .n_yes_ranges = ARRAY_SIZE(ad7768_regmap24_wr_ranges),
311 };
312
313 static const struct regmap_config ad7768_regmap24_config = {
314 .name = "ad7768-1-24",
315 .reg_bits = 8,
316 .val_bits = 24,
317 .read_flag_mask = BIT(6),
318 .rd_table = &ad7768_regmap24_rd_table,
319 .wr_table = &ad7768_regmap24_wr_table,
320 .max_register = AD7768_REG24_COEFF_DATA,
321 };
322
ad7768_send_sync_pulse(struct ad7768_state * st)323 static int ad7768_send_sync_pulse(struct ad7768_state *st)
324 {
325 if (st->en_spi_sync)
326 return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00);
327
328 /*
329 * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk,
330 * where Tmclk is the MCLK period. The supported MCLK frequencies range
331 * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse
332 * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz).
333 *
334 * Add a delay to ensure the pulse width is always sufficient to
335 * trigger synchronization.
336 */
337 gpiod_set_value_cansleep(st->gpio_sync_in, 1);
338 fsleep(3);
339 gpiod_set_value_cansleep(st->gpio_sync_in, 0);
340
341 return 0;
342 }
343
ad7768_fill_samp_freq_tbl(struct ad7768_state * st)344 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st)
345 {
346 unsigned int i, samp_freq_avail, freq_filtered;
347 unsigned int len = 0;
348
349 freq_filtered = DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio);
350 for (i = 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) {
351 samp_freq_avail = DIV_ROUND_CLOSEST(freq_filtered, ad7768_mclk_div_rates[i]);
352 /* Sampling frequency cannot be lower than the minimum of 50 SPS */
353 if (samp_freq_avail < 50)
354 continue;
355
356 st->samp_freq_avail[len++] = samp_freq_avail;
357 }
358
359 st->samp_freq_avail_len = len;
360 }
361
ad7768_set_mclk_div(struct ad7768_state * st,unsigned int mclk_div)362 static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_div)
363 {
364 unsigned int mclk_div_value;
365
366 mclk_div_value = AD7768_PWR_MCLK_DIV(mclk_div);
367 /*
368 * Set power mode based on mclk_div value.
369 * ECO_MODE is only recommended for MCLK_DIV = 16.
370 */
371 mclk_div_value |= mclk_div > AD7768_MCLK_DIV_16 ?
372 AD7768_PWR_PWRMODE(AD7768_FAST_MODE) :
373 AD7768_PWR_PWRMODE(AD7768_ECO_MODE);
374
375 return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK,
376 AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK,
377 mclk_div_value);
378 }
379
ad7768_set_mode(struct ad7768_state * st,enum ad7768_conv_mode mode)380 static int ad7768_set_mode(struct ad7768_state *st,
381 enum ad7768_conv_mode mode)
382 {
383 return regmap_update_bits(st->regmap, AD7768_REG_CONVERSION,
384 AD7768_CONV_MODE_MSK, AD7768_CONV_MODE(mode));
385 }
386
ad7768_scan_direct(struct iio_dev * indio_dev)387 static int ad7768_scan_direct(struct iio_dev *indio_dev)
388 {
389 struct ad7768_state *st = iio_priv(indio_dev);
390 int readval, ret;
391
392 reinit_completion(&st->completion);
393
394 ret = ad7768_set_mode(st, AD7768_ONE_SHOT);
395 if (ret < 0)
396 return ret;
397
398 ret = wait_for_completion_timeout(&st->completion,
399 msecs_to_jiffies(1000));
400 if (!ret)
401 return -ETIMEDOUT;
402
403 ret = regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &readval);
404 if (ret)
405 return ret;
406
407 /*
408 * When the decimation rate is set to x8, the ADC data precision is
409 * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA
410 * register provides 24-bit data, the precision is reduced by
411 * right-shifting the read value by 8 bits.
412 */
413 if (st->oversampling_ratio == 8)
414 readval >>= 8;
415
416 /*
417 * Any SPI configuration of the AD7768-1 can only be
418 * performed in continuous conversion mode.
419 */
420 ret = ad7768_set_mode(st, AD7768_CONTINUOUS);
421 if (ret < 0)
422 return ret;
423
424 return readval;
425 }
426
ad7768_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)427 static int ad7768_reg_access(struct iio_dev *indio_dev,
428 unsigned int reg,
429 unsigned int writeval,
430 unsigned int *readval)
431 {
432 struct ad7768_state *st = iio_priv(indio_dev);
433 int ret;
434
435 if (!iio_device_claim_direct(indio_dev))
436 return -EBUSY;
437
438 ret = -EINVAL;
439 if (readval) {
440 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_rd_table))
441 ret = regmap_read(st->regmap, reg, readval);
442
443 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_rd_table))
444 ret = regmap_read(st->regmap24, reg, readval);
445
446 } else {
447 if (regmap_check_range_table(st->regmap, reg, &ad7768_regmap_wr_table))
448 ret = regmap_write(st->regmap, reg, writeval);
449
450 if (regmap_check_range_table(st->regmap24, reg, &ad7768_regmap24_wr_table))
451 ret = regmap_write(st->regmap24, reg, writeval);
452
453 }
454
455 iio_device_release_direct(indio_dev);
456
457 return ret;
458 }
459
ad7768_set_sinc3_dec_rate(struct ad7768_state * st,unsigned int dec_rate)460 static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st,
461 unsigned int dec_rate)
462 {
463 unsigned int max_dec_rate;
464 u8 dec_rate_reg[2];
465 u16 regval;
466 int ret;
467
468 /*
469 * Maximum dec_rate is limited by the MCLK_DIV value and by the ODR.
470 * The edge case is for MCLK_DIV = 2, ODR = 50 SPS.
471 * max_dec_rate <= MCLK / (2 * 50)
472 */
473 max_dec_rate = st->mclk_freq / 100;
474 dec_rate = clamp(dec_rate, 32, max_dec_rate);
475 /*
476 * Calculate the equivalent value to sinc3 decimation ratio
477 * to be written on the SINC3_DEC_RATE register:
478 * Value = (DEC_RATE / 32) - 1
479 */
480 dec_rate = DIV_ROUND_UP(dec_rate, 32) - 1;
481
482 /*
483 * The SINC3_DEC_RATE value is a 13-bit value split across two
484 * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using
485 * FIELD_PREP() and store it with the right endianness in dec_rate_reg.
486 */
487 regval = FIELD_PREP(GENMASK(12, 0), dec_rate);
488 put_unaligned_be16(regval, dec_rate_reg);
489 ret = regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB,
490 dec_rate_reg, 2);
491 if (ret)
492 return ret;
493
494 st->oversampling_ratio = (dec_rate + 1) * 32;
495
496 return 0;
497 }
498
ad7768_configure_dig_fil(struct iio_dev * dev,enum ad7768_filter_type filter_type,unsigned int dec_rate)499 static int ad7768_configure_dig_fil(struct iio_dev *dev,
500 enum ad7768_filter_type filter_type,
501 unsigned int dec_rate)
502 {
503 struct ad7768_state *st = iio_priv(dev);
504 unsigned int dec_rate_idx, dig_filter_regval;
505 int ret;
506
507 switch (filter_type) {
508 case AD7768_FILTER_SINC3:
509 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3);
510 break;
511 case AD7768_FILTER_SINC3_REJ60:
512 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3) |
513 AD7768_DIG_FIL_EN_60HZ_REJ;
514 break;
515 case AD7768_FILTER_WIDEBAND:
516 /* Skip decimations 8 and 16, not supported by the wideband filter */
517 dec_rate_idx = find_closest(dec_rate, &ad7768_dec_rate_values[2],
518 ARRAY_SIZE(ad7768_dec_rate_values) - 2);
519 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) |
520 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx);
521 /* Correct the index offset */
522 dec_rate_idx += 2;
523 break;
524 case AD7768_FILTER_SINC5:
525 dec_rate_idx = find_closest(dec_rate, ad7768_dec_rate_values,
526 ARRAY_SIZE(ad7768_dec_rate_values));
527
528 /*
529 * Decimations 8 (idx 0) and 16 (idx 1) are set in the
530 * FILTER[6:4] field. The other decimations are set in the
531 * DEC_RATE[2:0] field, and the idx needs to be offsetted by two.
532 */
533 if (dec_rate_idx == 0)
534 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8);
535 else if (dec_rate_idx == 1)
536 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16);
537 else
538 dig_filter_regval = AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) |
539 AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2);
540 break;
541 }
542
543 ret = regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_regval);
544 if (ret)
545 return ret;
546
547 st->filter_type = filter_type;
548 /*
549 * The decimation for SINC3 filters are configured in different
550 * registers.
551 */
552 if (filter_type == AD7768_FILTER_SINC3 ||
553 filter_type == AD7768_FILTER_SINC3_REJ60) {
554 ret = ad7768_set_sinc3_dec_rate(st, dec_rate);
555 if (ret)
556 return ret;
557 } else {
558 st->oversampling_ratio = ad7768_dec_rate_values[dec_rate_idx];
559 }
560
561 ad7768_fill_samp_freq_tbl(st);
562
563 /* A sync-in pulse is required after every configuration change */
564 return ad7768_send_sync_pulse(st);
565 }
566
ad7768_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)567 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
568 {
569 struct iio_dev *indio_dev = gpiochip_get_data(chip);
570 struct ad7768_state *st = iio_priv(indio_dev);
571 int ret;
572
573 if (!iio_device_claim_direct(indio_dev))
574 return -EBUSY;
575
576 ret = regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL,
577 BIT(offset));
578 iio_device_release_direct(indio_dev);
579
580 return ret;
581 }
582
ad7768_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)583 static int ad7768_gpio_direction_output(struct gpio_chip *chip,
584 unsigned int offset, int value)
585 {
586 struct iio_dev *indio_dev = gpiochip_get_data(chip);
587 struct ad7768_state *st = iio_priv(indio_dev);
588 int ret;
589
590 if (!iio_device_claim_direct(indio_dev))
591 return -EBUSY;
592
593 ret = regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL,
594 BIT(offset));
595 iio_device_release_direct(indio_dev);
596
597 return ret;
598 }
599
ad7768_gpio_get(struct gpio_chip * chip,unsigned int offset)600 static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset)
601 {
602 struct iio_dev *indio_dev = gpiochip_get_data(chip);
603 struct ad7768_state *st = iio_priv(indio_dev);
604 unsigned int val;
605 int ret;
606
607 if (!iio_device_claim_direct(indio_dev))
608 return -EBUSY;
609
610 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val);
611 if (ret)
612 goto err_release;
613
614 /*
615 * If the GPIO is configured as an output, read the current value from
616 * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from
617 * AD7768_REG_GPIO_READ.
618 */
619 if (val & BIT(offset))
620 ret = regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val);
621 else
622 ret = regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val);
623 if (ret)
624 goto err_release;
625
626 ret = !!(val & BIT(offset));
627 err_release:
628 iio_device_release_direct(indio_dev);
629
630 return ret;
631 }
632
ad7768_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)633 static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
634 {
635 struct iio_dev *indio_dev = gpiochip_get_data(chip);
636 struct ad7768_state *st = iio_priv(indio_dev);
637 unsigned int val;
638 int ret;
639
640 if (!iio_device_claim_direct(indio_dev))
641 return -EBUSY;
642
643 ret = regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val);
644 if (ret)
645 goto err_release;
646
647 if (val & BIT(offset))
648 ret = regmap_assign_bits(st->regmap, AD7768_REG_GPIO_WRITE,
649 BIT(offset), value);
650
651 err_release:
652 iio_device_release_direct(indio_dev);
653
654 return ret;
655 }
656
ad7768_gpio_init(struct iio_dev * indio_dev)657 static int ad7768_gpio_init(struct iio_dev *indio_dev)
658 {
659 struct ad7768_state *st = iio_priv(indio_dev);
660 int ret;
661
662 ret = regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL,
663 AD7768_GPIO_UNIVERSAL_EN);
664 if (ret)
665 return ret;
666
667 st->gpiochip = (struct gpio_chip) {
668 .label = "ad7768_1_gpios",
669 .base = -1,
670 .ngpio = 4,
671 .parent = &st->spi->dev,
672 .can_sleep = true,
673 .direction_input = ad7768_gpio_direction_input,
674 .direction_output = ad7768_gpio_direction_output,
675 .get = ad7768_gpio_get,
676 .set_rv = ad7768_gpio_set,
677 .owner = THIS_MODULE,
678 };
679
680 return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev);
681 }
682
ad7768_set_freq(struct ad7768_state * st,unsigned int freq)683 static int ad7768_set_freq(struct ad7768_state *st,
684 unsigned int freq)
685 {
686 unsigned int idx, mclk_div;
687 int ret;
688
689 freq = clamp(freq, 50, 1024000);
690 if (freq == 0)
691 return -EINVAL;
692
693 mclk_div = DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio);
694 /* Find the closest match for the desired sampling frequency */
695 idx = find_closest_descending(mclk_div, ad7768_mclk_div_rates,
696 ARRAY_SIZE(ad7768_mclk_div_rates));
697 /* Set both the mclk_div and pwrmode */
698 ret = ad7768_set_mclk_div(st, idx);
699 if (ret)
700 return ret;
701
702 st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq,
703 ad7768_mclk_div_rates[idx] * st->oversampling_ratio);
704
705 /* A sync-in pulse is required after every configuration change */
706 return ad7768_send_sync_pulse(st);
707 }
708
ad7768_set_filter_type_attr(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int filter)709 static int ad7768_set_filter_type_attr(struct iio_dev *dev,
710 const struct iio_chan_spec *chan,
711 unsigned int filter)
712 {
713 struct ad7768_state *st = iio_priv(dev);
714 int ret;
715
716 ret = ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio);
717 if (ret)
718 return ret;
719
720 /* Update sampling frequency */
721 return ad7768_set_freq(st, st->samp_freq);
722 }
723
ad7768_get_filter_type_attr(struct iio_dev * dev,const struct iio_chan_spec * chan)724 static int ad7768_get_filter_type_attr(struct iio_dev *dev,
725 const struct iio_chan_spec *chan)
726 {
727 struct ad7768_state *st = iio_priv(dev);
728 int ret;
729 unsigned int mode, mask;
730
731 ret = regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode);
732 if (ret)
733 return ret;
734
735 mask = AD7768_DIG_FIL_EN_60HZ_REJ | AD7768_DIG_FIL_FIL_MSK;
736 /* From the register value, get the corresponding filter type */
737 return ad7768_filter_regval_to_type[FIELD_GET(mask, mode)];
738 }
739
740 static const struct iio_enum ad7768_filter_type_iio_enum = {
741 .items = ad7768_filter_enum,
742 .num_items = ARRAY_SIZE(ad7768_filter_enum),
743 .set = ad7768_set_filter_type_attr,
744 .get = ad7768_get_filter_type_attr,
745 };
746
747 static const struct iio_chan_spec_ext_info ad7768_ext_info[] = {
748 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum),
749 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum),
750 { }
751 };
752
753 static const struct iio_chan_spec ad7768_channels[] = {
754 {
755 .type = IIO_VOLTAGE,
756 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
757 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
758 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |
759 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
760 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),
761 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
762 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
763 .ext_info = ad7768_ext_info,
764 .indexed = 1,
765 .channel = 0,
766 .scan_index = 0,
767 .has_ext_scan_type = 1,
768 .ext_scan_type = ad7768_scan_type,
769 .num_ext_scan_type = ARRAY_SIZE(ad7768_scan_type),
770 },
771 };
772
ad7768_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)773 static int ad7768_read_raw(struct iio_dev *indio_dev,
774 struct iio_chan_spec const *chan,
775 int *val, int *val2, long info)
776 {
777 struct ad7768_state *st = iio_priv(indio_dev);
778 const struct iio_scan_type *scan_type;
779 int scale_uv, ret, temp;
780
781 scan_type = iio_get_current_scan_type(indio_dev, chan);
782 if (IS_ERR(scan_type))
783 return PTR_ERR(scan_type);
784
785 switch (info) {
786 case IIO_CHAN_INFO_RAW:
787 if (!iio_device_claim_direct(indio_dev))
788 return -EBUSY;
789
790 ret = ad7768_scan_direct(indio_dev);
791
792 iio_device_release_direct(indio_dev);
793 if (ret < 0)
794 return ret;
795 *val = sign_extend32(ret, scan_type->realbits - 1);
796
797 return IIO_VAL_INT;
798
799 case IIO_CHAN_INFO_SCALE:
800 scale_uv = regulator_get_voltage(st->vref);
801 if (scale_uv < 0)
802 return scale_uv;
803
804 *val = (scale_uv * 2) / 1000;
805 *val2 = scan_type->realbits;
806
807 return IIO_VAL_FRACTIONAL_LOG2;
808
809 case IIO_CHAN_INFO_SAMP_FREQ:
810 *val = st->samp_freq;
811
812 return IIO_VAL_INT;
813
814 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
815 *val = st->oversampling_ratio;
816
817 return IIO_VAL_INT;
818
819 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
820 temp = st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_type];
821 *val = DIV_ROUND_CLOSEST(temp, MILLI);
822
823 return IIO_VAL_INT;
824 }
825
826 return -EINVAL;
827 }
828
ad7768_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)829 static int ad7768_read_avail(struct iio_dev *indio_dev,
830 struct iio_chan_spec const *chan,
831 const int **vals, int *type, int *length,
832 long info)
833 {
834 struct ad7768_state *st = iio_priv(indio_dev);
835 unsigned int shift;
836
837 switch (info) {
838 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
839 /*
840 * Sinc3 filter allows a wider range of OSR values, so show
841 * the available values in range format.
842 */
843 if (st->filter_type == AD7768_FILTER_SINC3 ||
844 st->filter_type == AD7768_FILTER_SINC3_REJ60) {
845 *vals = (int *)ad7768_sinc3_dec_rate_range;
846 *type = IIO_VAL_INT;
847 return IIO_AVAIL_RANGE;
848 }
849
850 shift = st->filter_type == AD7768_FILTER_SINC5 ? 0 : 2;
851 *vals = (int *)&ad7768_dec_rate_values[shift];
852 *length = ARRAY_SIZE(ad7768_dec_rate_values) - shift;
853 *type = IIO_VAL_INT;
854 return IIO_AVAIL_LIST;
855 case IIO_CHAN_INFO_SAMP_FREQ:
856 *vals = (int *)st->samp_freq_avail;
857 *length = st->samp_freq_avail_len;
858 *type = IIO_VAL_INT;
859 return IIO_AVAIL_LIST;
860 default:
861 return -EINVAL;
862 }
863 }
864
__ad7768_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)865 static int __ad7768_write_raw(struct iio_dev *indio_dev,
866 struct iio_chan_spec const *chan,
867 int val, int val2, long info)
868 {
869 struct ad7768_state *st = iio_priv(indio_dev);
870 int ret;
871
872 switch (info) {
873 case IIO_CHAN_INFO_SAMP_FREQ:
874 return ad7768_set_freq(st, val);
875
876 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
877 ret = ad7768_configure_dig_fil(indio_dev, st->filter_type, val);
878 if (ret)
879 return ret;
880
881 /* Update sampling frequency */
882 return ad7768_set_freq(st, st->samp_freq);
883 default:
884 return -EINVAL;
885 }
886 }
887
ad7768_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)888 static int ad7768_write_raw(struct iio_dev *indio_dev,
889 struct iio_chan_spec const *chan,
890 int val, int val2, long info)
891 {
892 int ret;
893
894 if (!iio_device_claim_direct(indio_dev))
895 return -EBUSY;
896
897 ret = __ad7768_write_raw(indio_dev, chan, val, val2, info);
898 iio_device_release_direct(indio_dev);
899
900 return ret;
901 }
902
ad7768_read_label(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,char * label)903 static int ad7768_read_label(struct iio_dev *indio_dev,
904 const struct iio_chan_spec *chan, char *label)
905 {
906 struct ad7768_state *st = iio_priv(indio_dev);
907
908 return sprintf(label, "%s\n", st->labels[chan->channel]);
909 }
910
ad7768_get_current_scan_type(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)911 static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev,
912 const struct iio_chan_spec *chan)
913 {
914 struct ad7768_state *st = iio_priv(indio_dev);
915
916 return st->oversampling_ratio == 8 ?
917 AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL;
918 }
919
920 static const struct iio_info ad7768_info = {
921 .read_raw = &ad7768_read_raw,
922 .read_avail = &ad7768_read_avail,
923 .write_raw = &ad7768_write_raw,
924 .read_label = ad7768_read_label,
925 .get_current_scan_type = &ad7768_get_current_scan_type,
926 .debugfs_reg_access = &ad7768_reg_access,
927 };
928
929 static struct fwnode_handle *
ad7768_fwnode_find_reference_args(const struct fwnode_handle * fwnode,const char * name,const char * nargs_prop,unsigned int nargs,unsigned int index,struct fwnode_reference_args * args)930 ad7768_fwnode_find_reference_args(const struct fwnode_handle *fwnode,
931 const char *name, const char *nargs_prop,
932 unsigned int nargs, unsigned int index,
933 struct fwnode_reference_args *args)
934 {
935 int ret;
936
937 ret = fwnode_property_get_reference_args(fwnode, name, nargs_prop,
938 nargs, index, args);
939 return ret ? ERR_PTR(ret) : args->fwnode;
940 }
941
ad7768_trigger_sources_sync_setup(struct device * dev,struct fwnode_handle * fwnode,struct ad7768_state * st)942 static int ad7768_trigger_sources_sync_setup(struct device *dev,
943 struct fwnode_handle *fwnode,
944 struct ad7768_state *st)
945 {
946 struct fwnode_reference_args args;
947
948 struct fwnode_handle *ref __free(fwnode_handle) =
949 ad7768_fwnode_find_reference_args(fwnode, "trigger-sources",
950 "#trigger-source-cells", 0,
951 AD7768_TRIGGER_SOURCE_SYNC_IDX,
952 &args);
953 if (IS_ERR(ref))
954 return PTR_ERR(ref);
955
956 ref = args.fwnode;
957 /* First, try getting the GPIO trigger source */
958 if (fwnode_device_is_compatible(ref, "gpio-trigger")) {
959 st->gpio_sync_in = devm_fwnode_gpiod_get_index(dev, ref, NULL, 0,
960 GPIOD_OUT_LOW,
961 "sync-in");
962 return PTR_ERR_OR_ZERO(st->gpio_sync_in);
963 }
964
965 /*
966 * TODO: Support the other cases when we have a trigger subsystem
967 * to reliably handle other types of devices as trigger sources.
968 *
969 * For now, return an error message. For self triggering, omit the
970 * trigger-sources property.
971 */
972 return dev_err_probe(dev, -EOPNOTSUPP, "Invalid synchronization trigger source\n");
973 }
974
ad7768_trigger_sources_get_sync(struct device * dev,struct ad7768_state * st)975 static int ad7768_trigger_sources_get_sync(struct device *dev,
976 struct ad7768_state *st)
977 {
978 struct fwnode_handle *fwnode = dev_fwnode(dev);
979
980 /*
981 * The AD7768-1 allows two primary methods for driving the SYNC_IN pin
982 * to synchronize one or more devices:
983 * 1. Using an external GPIO.
984 * 2. Using a SPI command, where the SYNC_OUT pin generates a
985 * synchronization pulse that drives the SYNC_IN pin.
986 */
987 if (fwnode_property_present(fwnode, "trigger-sources"))
988 return ad7768_trigger_sources_sync_setup(dev, fwnode, st);
989
990 /*
991 * In the absence of trigger-sources property, enable self
992 * synchronization over SPI (SYNC_OUT).
993 */
994 st->en_spi_sync = true;
995
996 return 0;
997 }
998
ad7768_setup(struct iio_dev * indio_dev)999 static int ad7768_setup(struct iio_dev *indio_dev)
1000 {
1001 struct ad7768_state *st = iio_priv(indio_dev);
1002 int ret;
1003
1004 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
1005 GPIOD_OUT_HIGH);
1006 if (IS_ERR(st->gpio_reset))
1007 return PTR_ERR(st->gpio_reset);
1008
1009 if (st->gpio_reset) {
1010 fsleep(10);
1011 gpiod_set_value_cansleep(st->gpio_reset, 0);
1012 fsleep(200);
1013 } else {
1014 /*
1015 * Two writes to the SPI_RESET[1:0] bits are required to initiate
1016 * a software reset. The bits must first be set to 11, and then
1017 * to 10. When the sequence is detected, the reset occurs.
1018 * See the datasheet, page 70.
1019 */
1020 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x3);
1021 if (ret)
1022 return ret;
1023
1024 ret = regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x2);
1025 if (ret)
1026 return ret;
1027 }
1028
1029 /* For backwards compatibility, try the adi,sync-in-gpios property */
1030 st->gpio_sync_in = devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in",
1031 GPIOD_OUT_LOW);
1032 if (IS_ERR(st->gpio_sync_in))
1033 return PTR_ERR(st->gpio_sync_in);
1034
1035 /*
1036 * If the synchronization is not defined by adi,sync-in-gpios, try the
1037 * trigger-sources.
1038 */
1039 if (!st->gpio_sync_in) {
1040 ret = ad7768_trigger_sources_get_sync(&st->spi->dev, st);
1041 if (ret)
1042 return ret;
1043 }
1044
1045 /* Only create a Chip GPIO if flagged for it */
1046 if (device_property_read_bool(&st->spi->dev, "gpio-controller")) {
1047 ret = ad7768_gpio_init(indio_dev);
1048 if (ret)
1049 return ret;
1050 }
1051
1052 /*
1053 * Set Default Digital Filter configuration:
1054 * SINC5 filter with x32 Decimation rate
1055 */
1056 ret = ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32);
1057 if (ret)
1058 return ret;
1059
1060 /* Set the default sampling frequency to 32000 kSPS */
1061 return ad7768_set_freq(st, 32000);
1062 }
1063
ad7768_trigger_handler(int irq,void * p)1064 static irqreturn_t ad7768_trigger_handler(int irq, void *p)
1065 {
1066 struct iio_poll_func *pf = p;
1067 struct iio_dev *indio_dev = pf->indio_dev;
1068 struct ad7768_state *st = iio_priv(indio_dev);
1069 const struct iio_scan_type *scan_type;
1070 int ret;
1071
1072 scan_type = iio_get_current_scan_type(indio_dev, &indio_dev->channels[0]);
1073 if (IS_ERR(scan_type))
1074 goto out;
1075
1076 ret = spi_read(st->spi, &st->data.scan.chan,
1077 BITS_TO_BYTES(scan_type->realbits));
1078 if (ret < 0)
1079 goto out;
1080
1081 iio_push_to_buffers_with_ts(indio_dev, &st->data.scan,
1082 sizeof(st->data.scan),
1083 iio_get_time_ns(indio_dev));
1084
1085 out:
1086 iio_trigger_notify_done(indio_dev->trig);
1087
1088 return IRQ_HANDLED;
1089 }
1090
ad7768_interrupt(int irq,void * dev_id)1091 static irqreturn_t ad7768_interrupt(int irq, void *dev_id)
1092 {
1093 struct iio_dev *indio_dev = dev_id;
1094 struct ad7768_state *st = iio_priv(indio_dev);
1095
1096 if (iio_buffer_enabled(indio_dev))
1097 iio_trigger_poll(st->trig);
1098 else
1099 complete(&st->completion);
1100
1101 return IRQ_HANDLED;
1102 };
1103
ad7768_buffer_postenable(struct iio_dev * indio_dev)1104 static int ad7768_buffer_postenable(struct iio_dev *indio_dev)
1105 {
1106 struct ad7768_state *st = iio_priv(indio_dev);
1107
1108 /*
1109 * Write a 1 to the LSB of the INTERFACE_FORMAT register to enter
1110 * continuous read mode. Subsequent data reads do not require an
1111 * initial 8-bit write to query the ADC_DATA register.
1112 */
1113 return regmap_write(st->regmap, AD7768_REG_INTERFACE_FORMAT, 0x01);
1114 }
1115
ad7768_buffer_predisable(struct iio_dev * indio_dev)1116 static int ad7768_buffer_predisable(struct iio_dev *indio_dev)
1117 {
1118 struct ad7768_state *st = iio_priv(indio_dev);
1119 unsigned int unused;
1120
1121 /*
1122 * To exit continuous read mode, perform a single read of the ADC_DATA
1123 * reg (0x2C), which allows further configuration of the device.
1124 */
1125 return regmap_read(st->regmap24, AD7768_REG24_ADC_DATA, &unused);
1126 }
1127
1128 static const struct iio_buffer_setup_ops ad7768_buffer_ops = {
1129 .postenable = &ad7768_buffer_postenable,
1130 .predisable = &ad7768_buffer_predisable,
1131 };
1132
1133 static const struct iio_trigger_ops ad7768_trigger_ops = {
1134 .validate_device = iio_trigger_validate_own_device,
1135 };
1136
ad7768_regulator_disable(void * data)1137 static void ad7768_regulator_disable(void *data)
1138 {
1139 struct ad7768_state *st = data;
1140
1141 regulator_disable(st->vref);
1142 }
1143
ad7768_set_channel_label(struct iio_dev * indio_dev,int num_channels)1144 static int ad7768_set_channel_label(struct iio_dev *indio_dev,
1145 int num_channels)
1146 {
1147 struct ad7768_state *st = iio_priv(indio_dev);
1148 struct device *device = indio_dev->dev.parent;
1149 const char *label;
1150 int crt_ch = 0;
1151
1152 device_for_each_child_node_scoped(device, child) {
1153 if (fwnode_property_read_u32(child, "reg", &crt_ch))
1154 continue;
1155
1156 if (crt_ch >= num_channels)
1157 continue;
1158
1159 if (fwnode_property_read_string(child, "label", &label))
1160 continue;
1161
1162 st->labels[crt_ch] = label;
1163 }
1164
1165 return 0;
1166 }
1167
ad7768_triggered_buffer_alloc(struct iio_dev * indio_dev)1168 static int ad7768_triggered_buffer_alloc(struct iio_dev *indio_dev)
1169 {
1170 struct ad7768_state *st = iio_priv(indio_dev);
1171 int ret;
1172
1173 st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-dev%d",
1174 indio_dev->name,
1175 iio_device_id(indio_dev));
1176 if (!st->trig)
1177 return -ENOMEM;
1178
1179 st->trig->ops = &ad7768_trigger_ops;
1180 iio_trigger_set_drvdata(st->trig, indio_dev);
1181 ret = devm_iio_trigger_register(indio_dev->dev.parent, st->trig);
1182 if (ret)
1183 return ret;
1184
1185 indio_dev->trig = iio_trigger_get(st->trig);
1186
1187 return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev,
1188 &iio_pollfunc_store_time,
1189 &ad7768_trigger_handler,
1190 &ad7768_buffer_ops);
1191 }
1192
ad7768_vcm_enable(struct regulator_dev * rdev)1193 static int ad7768_vcm_enable(struct regulator_dev *rdev)
1194 {
1195 struct iio_dev *indio_dev = rdev_get_drvdata(rdev);
1196 struct ad7768_state *st = iio_priv(indio_dev);
1197 int ret, regval;
1198
1199 if (!iio_device_claim_direct(indio_dev))
1200 return -EBUSY;
1201
1202 /* To enable, set the last selected output */
1203 regval = AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1);
1204 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2,
1205 AD7768_REG_ANALOG2_VCM_MSK, regval);
1206 iio_device_release_direct(indio_dev);
1207
1208 return ret;
1209 }
1210
ad7768_vcm_disable(struct regulator_dev * rdev)1211 static int ad7768_vcm_disable(struct regulator_dev *rdev)
1212 {
1213 struct iio_dev *indio_dev = rdev_get_drvdata(rdev);
1214 struct ad7768_state *st = iio_priv(indio_dev);
1215 int ret;
1216
1217 if (!iio_device_claim_direct(indio_dev))
1218 return -EBUSY;
1219
1220 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2,
1221 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF);
1222 iio_device_release_direct(indio_dev);
1223
1224 return ret;
1225 }
1226
ad7768_vcm_is_enabled(struct regulator_dev * rdev)1227 static int ad7768_vcm_is_enabled(struct regulator_dev *rdev)
1228 {
1229 struct iio_dev *indio_dev = rdev_get_drvdata(rdev);
1230 struct ad7768_state *st = iio_priv(indio_dev);
1231 int ret, val;
1232
1233 if (!iio_device_claim_direct(indio_dev))
1234 return -EBUSY;
1235
1236 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val);
1237 iio_device_release_direct(indio_dev);
1238 if (ret)
1239 return ret;
1240
1241 return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) != AD7768_VCM_OFF;
1242 }
1243
ad7768_set_voltage_sel(struct regulator_dev * rdev,unsigned int selector)1244 static int ad7768_set_voltage_sel(struct regulator_dev *rdev,
1245 unsigned int selector)
1246 {
1247 unsigned int regval = AD7768_REG_ANALOG2_VCM(selector + 1);
1248 struct iio_dev *indio_dev = rdev_get_drvdata(rdev);
1249 struct ad7768_state *st = iio_priv(indio_dev);
1250 int ret;
1251
1252 if (!iio_device_claim_direct(indio_dev))
1253 return -EBUSY;
1254
1255 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2,
1256 AD7768_REG_ANALOG2_VCM_MSK, regval);
1257 iio_device_release_direct(indio_dev);
1258 if (ret)
1259 return ret;
1260
1261 st->vcm_output_sel = selector;
1262
1263 return 0;
1264 }
1265
ad7768_get_voltage_sel(struct regulator_dev * rdev)1266 static int ad7768_get_voltage_sel(struct regulator_dev *rdev)
1267 {
1268 struct iio_dev *indio_dev = rdev_get_drvdata(rdev);
1269 struct ad7768_state *st = iio_priv(indio_dev);
1270 int ret, val;
1271
1272 if (!iio_device_claim_direct(indio_dev))
1273 return -EBUSY;
1274
1275 ret = regmap_read(st->regmap, AD7768_REG_ANALOG2, &val);
1276 iio_device_release_direct(indio_dev);
1277 if (ret)
1278 return ret;
1279
1280 val = FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val);
1281
1282 return clamp(val, 1, rdev->desc->n_voltages) - 1;
1283 }
1284
1285 static const struct regulator_ops vcm_regulator_ops = {
1286 .enable = ad7768_vcm_enable,
1287 .disable = ad7768_vcm_disable,
1288 .is_enabled = ad7768_vcm_is_enabled,
1289 .list_voltage = regulator_list_voltage_table,
1290 .set_voltage_sel = ad7768_set_voltage_sel,
1291 .get_voltage_sel = ad7768_get_voltage_sel,
1292 };
1293
1294 static const unsigned int vcm_voltage_table[] = {
1295 2500000,
1296 2050000,
1297 1650000,
1298 1900000,
1299 1100000,
1300 900000,
1301 };
1302
1303 static const struct regulator_desc vcm_desc = {
1304 .name = "ad7768-1-vcm",
1305 .of_match = "vcm-output",
1306 .regulators_node = "regulators",
1307 .n_voltages = ARRAY_SIZE(vcm_voltage_table),
1308 .volt_table = vcm_voltage_table,
1309 .ops = &vcm_regulator_ops,
1310 .type = REGULATOR_VOLTAGE,
1311 .owner = THIS_MODULE,
1312 };
1313
ad7768_register_regulators(struct device * dev,struct ad7768_state * st,struct iio_dev * indio_dev)1314 static int ad7768_register_regulators(struct device *dev, struct ad7768_state *st,
1315 struct iio_dev *indio_dev)
1316 {
1317 struct regulator_config config = {
1318 .dev = dev,
1319 .driver_data = indio_dev,
1320 };
1321 int ret;
1322
1323 /* Disable the regulator before registering it */
1324 ret = regmap_update_bits(st->regmap, AD7768_REG_ANALOG2,
1325 AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF);
1326 if (ret)
1327 return ret;
1328
1329 st->vcm_rdev = devm_regulator_register(dev, &vcm_desc, &config);
1330 if (IS_ERR(st->vcm_rdev))
1331 return dev_err_probe(dev, PTR_ERR(st->vcm_rdev),
1332 "failed to register VCM regulator\n");
1333
1334 return 0;
1335 }
1336
ad7768_probe(struct spi_device * spi)1337 static int ad7768_probe(struct spi_device *spi)
1338 {
1339 struct ad7768_state *st;
1340 struct iio_dev *indio_dev;
1341 int ret;
1342
1343 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1344 if (!indio_dev)
1345 return -ENOMEM;
1346
1347 st = iio_priv(indio_dev);
1348 /*
1349 * Datasheet recommends SDI line to be kept high when data is not being
1350 * clocked out of the controller and the spi clock is free running,
1351 * to prevent accidental reset.
1352 * Since many controllers do not support the SPI_MOSI_IDLE_HIGH flag
1353 * yet, only request the MOSI idle state to enable if the controller
1354 * supports it.
1355 */
1356 if (spi->controller->mode_bits & SPI_MOSI_IDLE_HIGH) {
1357 spi->mode |= SPI_MOSI_IDLE_HIGH;
1358 ret = spi_setup(spi);
1359 if (ret < 0)
1360 return ret;
1361 }
1362
1363 st->spi = spi;
1364
1365 st->regmap = devm_regmap_init_spi(spi, &ad7768_regmap_config);
1366 if (IS_ERR(st->regmap))
1367 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap),
1368 "Failed to initialize regmap");
1369
1370 st->regmap24 = devm_regmap_init_spi(spi, &ad7768_regmap24_config);
1371 if (IS_ERR(st->regmap24))
1372 return dev_err_probe(&spi->dev, PTR_ERR(st->regmap24),
1373 "Failed to initialize regmap24");
1374
1375 st->vref = devm_regulator_get(&spi->dev, "vref");
1376 if (IS_ERR(st->vref))
1377 return PTR_ERR(st->vref);
1378
1379 ret = regulator_enable(st->vref);
1380 if (ret) {
1381 dev_err(&spi->dev, "Failed to enable specified vref supply\n");
1382 return ret;
1383 }
1384
1385 ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st);
1386 if (ret)
1387 return ret;
1388
1389 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
1390 if (IS_ERR(st->mclk))
1391 return PTR_ERR(st->mclk);
1392
1393 st->mclk_freq = clk_get_rate(st->mclk);
1394
1395 indio_dev->channels = ad7768_channels;
1396 indio_dev->num_channels = ARRAY_SIZE(ad7768_channels);
1397 indio_dev->name = spi_get_device_id(spi)->name;
1398 indio_dev->info = &ad7768_info;
1399 indio_dev->modes = INDIO_DIRECT_MODE;
1400
1401 /* Register VCM output regulator */
1402 ret = ad7768_register_regulators(&spi->dev, st, indio_dev);
1403 if (ret)
1404 return ret;
1405
1406 ret = ad7768_setup(indio_dev);
1407 if (ret < 0) {
1408 dev_err(&spi->dev, "AD7768 setup failed\n");
1409 return ret;
1410 }
1411
1412 init_completion(&st->completion);
1413
1414 ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels));
1415 if (ret)
1416 return ret;
1417
1418 ret = devm_request_irq(&spi->dev, spi->irq,
1419 &ad7768_interrupt,
1420 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1421 indio_dev->name, indio_dev);
1422 if (ret)
1423 return ret;
1424
1425 ret = ad7768_triggered_buffer_alloc(indio_dev);
1426 if (ret)
1427 return ret;
1428
1429 return devm_iio_device_register(&spi->dev, indio_dev);
1430 }
1431
1432 static const struct spi_device_id ad7768_id_table[] = {
1433 { "ad7768-1", 0 },
1434 { }
1435 };
1436 MODULE_DEVICE_TABLE(spi, ad7768_id_table);
1437
1438 static const struct of_device_id ad7768_of_match[] = {
1439 { .compatible = "adi,ad7768-1" },
1440 { }
1441 };
1442 MODULE_DEVICE_TABLE(of, ad7768_of_match);
1443
1444 static struct spi_driver ad7768_driver = {
1445 .driver = {
1446 .name = "ad7768-1",
1447 .of_match_table = ad7768_of_match,
1448 },
1449 .probe = ad7768_probe,
1450 .id_table = ad7768_id_table,
1451 };
1452 module_spi_driver(ad7768_driver);
1453
1454 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1455 MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver");
1456 MODULE_LICENSE("GPL v2");
1457