1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_CONTROL_MODE GENMASK(5, 2)
48 #define AD7124_ADC_CONTROL_MODE_CONTINUOUS 0
49 #define AD7124_ADC_CONTROL_MODE_SINGLE 1
50 #define AD7124_ADC_CONTROL_MODE_STANDBY 2
51 #define AD7124_ADC_CONTROL_MODE_POWERDOWN 3
52 #define AD7124_ADC_CONTROL_MODE_IDLE 4
53 #define AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB 5 /* Internal Zero-Scale Calibration */
54 #define AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB 6 /* Internal Full-Scale Calibration */
55 #define AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB 7 /* System Zero-Scale Calibration */
56 #define AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB 8 /* System Full-Scale Calibration */
57 #define AD7124_ADC_CONTROL_POWER_MODE GENMASK(7, 6)
58 #define AD7124_ADC_CONTROL_POWER_MODE_LOW 0
59 #define AD7124_ADC_CONTROL_POWER_MODE_MID 1
60 #define AD7124_ADC_CONTROL_POWER_MODE_FULL 2
61 #define AD7124_ADC_CONTROL_REF_EN BIT(8)
62 #define AD7124_ADC_CONTROL_DATA_STATUS BIT(10)
63
64 /* AD7124_ID */
65 #define AD7124_ID_SILICON_REVISION GENMASK(3, 0)
66 #define AD7124_ID_DEVICE_ID GENMASK(7, 4)
67 #define AD7124_ID_DEVICE_ID_AD7124_4 0x0
68 #define AD7124_ID_DEVICE_ID_AD7124_8 0x1
69
70 /* AD7124_CHANNEL_X */
71 #define AD7124_CHANNEL_ENABLE BIT(15)
72 #define AD7124_CHANNEL_SETUP GENMASK(14, 12)
73 #define AD7124_CHANNEL_AINP GENMASK(9, 5)
74 #define AD7124_CHANNEL_AINM GENMASK(4, 0)
75 #define AD7124_CHANNEL_AINx_TEMPSENSOR 16
76 #define AD7124_CHANNEL_AINx_AVSS 17
77
78 /* AD7124_CONFIG_X */
79 #define AD7124_CONFIG_BIPOLAR BIT(11)
80 #define AD7124_CONFIG_IN_BUFF GENMASK(6, 5)
81 #define AD7124_CONFIG_AIN_BUFP BIT(6)
82 #define AD7124_CONFIG_AIN_BUFM BIT(5)
83 #define AD7124_CONFIG_REF_SEL GENMASK(4, 3)
84 #define AD7124_CONFIG_PGA GENMASK(2, 0)
85
86 /* AD7124_FILTER_X */
87 #define AD7124_FILTER_FS GENMASK(10, 0)
88 #define AD7124_FILTER_FILTER GENMASK(23, 21)
89 #define AD7124_FILTER_FILTER_SINC4 0
90 #define AD7124_FILTER_FILTER_SINC3 2
91
92 #define AD7124_MAX_CONFIGS 8
93 #define AD7124_MAX_CHANNELS 16
94
95 /* AD7124 input sources */
96
97 enum ad7124_ref_sel {
98 AD7124_REFIN1,
99 AD7124_REFIN2,
100 AD7124_INT_REF,
101 AD7124_AVDD_REF,
102 };
103
104 enum ad7124_power_mode {
105 AD7124_LOW_POWER,
106 AD7124_MID_POWER,
107 AD7124_FULL_POWER,
108 };
109
110 static const unsigned int ad7124_gain[8] = {
111 1, 2, 4, 8, 16, 32, 64, 128
112 };
113
114 static const unsigned int ad7124_reg_size[] = {
115 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
116 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
117 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
118 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
119 3, 3, 3, 3, 3
120 };
121
122 static const int ad7124_master_clk_freq_hz[3] = {
123 [AD7124_LOW_POWER] = 76800,
124 [AD7124_MID_POWER] = 153600,
125 [AD7124_FULL_POWER] = 614400,
126 };
127
128 static const char * const ad7124_ref_names[] = {
129 [AD7124_REFIN1] = "refin1",
130 [AD7124_REFIN2] = "refin2",
131 [AD7124_INT_REF] = "int",
132 [AD7124_AVDD_REF] = "avdd",
133 };
134
135 struct ad7124_chip_info {
136 const char *name;
137 unsigned int chip_id;
138 unsigned int num_inputs;
139 };
140
141 struct ad7124_channel_config {
142 bool live;
143 unsigned int cfg_slot;
144 /*
145 * Following fields are used to compare for equality. If you
146 * make adaptations in it, you most likely also have to adapt
147 * ad7124_find_similar_live_cfg(), too.
148 */
149 struct_group(config_props,
150 enum ad7124_ref_sel refsel;
151 bool bipolar;
152 bool buf_positive;
153 bool buf_negative;
154 unsigned int vref_mv;
155 unsigned int pga_bits;
156 unsigned int odr;
157 unsigned int odr_sel_bits;
158 unsigned int filter_type;
159 unsigned int calibration_offset;
160 unsigned int calibration_gain;
161 );
162 };
163
164 struct ad7124_channel {
165 unsigned int nr;
166 struct ad7124_channel_config cfg;
167 unsigned int ain;
168 unsigned int slot;
169 u8 syscalib_mode;
170 };
171
172 struct ad7124_state {
173 const struct ad7124_chip_info *chip_info;
174 struct ad_sigma_delta sd;
175 struct ad7124_channel *channels;
176 struct regulator *vref[4];
177 struct clk *mclk;
178 unsigned int adc_control;
179 unsigned int num_channels;
180 struct mutex cfgs_lock; /* lock for configs access */
181 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
182
183 /*
184 * Stores the power-on reset value for the GAIN(x) registers which are
185 * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0)
186 */
187 unsigned int gain_default;
188 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
189 };
190
191 static const struct ad7124_chip_info ad7124_4_chip_info = {
192 .name = "ad7124-4",
193 .chip_id = AD7124_ID_DEVICE_ID_AD7124_4,
194 .num_inputs = 8,
195 };
196
197 static const struct ad7124_chip_info ad7124_8_chip_info = {
198 .name = "ad7124-8",
199 .chip_id = AD7124_ID_DEVICE_ID_AD7124_8,
200 .num_inputs = 16,
201 };
202
ad7124_find_closest_match(const int * array,unsigned int size,int val)203 static int ad7124_find_closest_match(const int *array,
204 unsigned int size, int val)
205 {
206 int i, idx;
207 unsigned int diff_new, diff_old;
208
209 diff_old = U32_MAX;
210 idx = 0;
211
212 for (i = 0; i < size; i++) {
213 diff_new = abs(val - array[i]);
214 if (diff_new < diff_old) {
215 diff_old = diff_new;
216 idx = i;
217 }
218 }
219
220 return idx;
221 }
222
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)223 static int ad7124_spi_write_mask(struct ad7124_state *st,
224 unsigned int addr,
225 unsigned long mask,
226 unsigned int val,
227 unsigned int bytes)
228 {
229 unsigned int readval;
230 int ret;
231
232 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
233 if (ret < 0)
234 return ret;
235
236 readval &= ~mask;
237 readval |= val;
238
239 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
240 }
241
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)242 static int ad7124_set_mode(struct ad_sigma_delta *sd,
243 enum ad_sigma_delta_mode mode)
244 {
245 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
246
247 st->adc_control &= ~AD7124_ADC_CONTROL_MODE;
248 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, mode);
249
250 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
251 }
252
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)253 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
254 {
255 unsigned int fclk, odr_sel_bits;
256
257 fclk = clk_get_rate(st->mclk);
258 /*
259 * FS[10:0] = fCLK / (fADC x 32) where:
260 * fADC is the output data rate
261 * fCLK is the master clock frequency
262 * FS[10:0] are the bits in the filter register
263 * FS[10:0] can have a value from 1 to 2047
264 */
265 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
266 if (odr_sel_bits < 1)
267 odr_sel_bits = 1;
268 else if (odr_sel_bits > 2047)
269 odr_sel_bits = 2047;
270
271 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
272 st->channels[channel].cfg.live = false;
273
274 /* fADC = fCLK / (FS[10:0] x 32) */
275 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
276 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
277 }
278
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)279 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
280 unsigned int channel)
281 {
282 unsigned int fadc;
283
284 fadc = st->channels[channel].cfg.odr;
285
286 switch (st->channels[channel].cfg.filter_type) {
287 case AD7124_FILTER_FILTER_SINC3:
288 return DIV_ROUND_CLOSEST(fadc * 272, 1000);
289 case AD7124_FILTER_FILTER_SINC4:
290 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
291 default:
292 return -EINVAL;
293 }
294 }
295
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)296 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
297 struct ad7124_channel_config *cfg)
298 {
299 struct ad7124_channel_config *cfg_aux;
300 int i;
301
302 /*
303 * This is just to make sure that the comparison is adapted after
304 * struct ad7124_channel_config was changed.
305 */
306 static_assert(sizeof_field(struct ad7124_channel_config, config_props) ==
307 sizeof(struct {
308 enum ad7124_ref_sel refsel;
309 bool bipolar;
310 bool buf_positive;
311 bool buf_negative;
312 unsigned int vref_mv;
313 unsigned int pga_bits;
314 unsigned int odr;
315 unsigned int odr_sel_bits;
316 unsigned int filter_type;
317 unsigned int calibration_offset;
318 unsigned int calibration_gain;
319 }));
320
321 for (i = 0; i < st->num_channels; i++) {
322 cfg_aux = &st->channels[i].cfg;
323
324 if (cfg_aux->live &&
325 cfg->refsel == cfg_aux->refsel &&
326 cfg->bipolar == cfg_aux->bipolar &&
327 cfg->buf_positive == cfg_aux->buf_positive &&
328 cfg->buf_negative == cfg_aux->buf_negative &&
329 cfg->vref_mv == cfg_aux->vref_mv &&
330 cfg->pga_bits == cfg_aux->pga_bits &&
331 cfg->odr == cfg_aux->odr &&
332 cfg->odr_sel_bits == cfg_aux->odr_sel_bits &&
333 cfg->filter_type == cfg_aux->filter_type &&
334 cfg->calibration_offset == cfg_aux->calibration_offset &&
335 cfg->calibration_gain == cfg_aux->calibration_gain)
336 return cfg_aux;
337 }
338
339 return NULL;
340 }
341
ad7124_find_free_config_slot(struct ad7124_state * st)342 static int ad7124_find_free_config_slot(struct ad7124_state *st)
343 {
344 unsigned int free_cfg_slot;
345
346 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
347 if (free_cfg_slot == AD7124_MAX_CONFIGS)
348 return -1;
349
350 return free_cfg_slot;
351 }
352
353 /* Only called during probe, so dev_err_probe() can be used */
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)354 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
355 {
356 struct device *dev = &st->sd.spi->dev;
357 unsigned int refsel = cfg->refsel;
358
359 switch (refsel) {
360 case AD7124_REFIN1:
361 case AD7124_REFIN2:
362 case AD7124_AVDD_REF:
363 if (IS_ERR(st->vref[refsel]))
364 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]),
365 "Error, trying to use external voltage reference without a %s regulator.\n",
366 ad7124_ref_names[refsel]);
367
368 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
369 /* Conversion from uV to mV */
370 cfg->vref_mv /= 1000;
371 return 0;
372 case AD7124_INT_REF:
373 cfg->vref_mv = 2500;
374 st->adc_control |= AD7124_ADC_CONTROL_REF_EN;
375 return 0;
376 default:
377 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel);
378 }
379 }
380
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)381 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
382 unsigned int cfg_slot)
383 {
384 unsigned int tmp;
385 unsigned int val;
386 int ret;
387
388 cfg->cfg_slot = cfg_slot;
389
390 ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg->cfg_slot), 3, cfg->calibration_offset);
391 if (ret)
392 return ret;
393
394 ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg->cfg_slot), 3, cfg->calibration_gain);
395 if (ret)
396 return ret;
397
398 val = FIELD_PREP(AD7124_CONFIG_BIPOLAR, cfg->bipolar) |
399 FIELD_PREP(AD7124_CONFIG_REF_SEL, cfg->refsel) |
400 (cfg->buf_positive ? AD7124_CONFIG_AIN_BUFP : 0) |
401 (cfg->buf_negative ? AD7124_CONFIG_AIN_BUFM : 0) |
402 FIELD_PREP(AD7124_CONFIG_PGA, cfg->pga_bits);
403
404 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
405 if (ret < 0)
406 return ret;
407
408 tmp = FIELD_PREP(AD7124_FILTER_FILTER, cfg->filter_type) |
409 FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits);
410 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot),
411 AD7124_FILTER_FILTER | AD7124_FILTER_FS,
412 tmp, 3);
413 }
414
ad7124_pop_config(struct ad7124_state * st)415 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
416 {
417 struct ad7124_channel_config *lru_cfg;
418 struct ad7124_channel_config *cfg;
419 int ret;
420 int i;
421
422 /*
423 * Pop least recently used config from the fifo
424 * in order to make room for the new one
425 */
426 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
427 if (ret <= 0)
428 return NULL;
429
430 lru_cfg->live = false;
431
432 /* mark slot as free */
433 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
434
435 /* invalidate all other configs that pointed to this one */
436 for (i = 0; i < st->num_channels; i++) {
437 cfg = &st->channels[i].cfg;
438
439 if (cfg->cfg_slot == lru_cfg->cfg_slot)
440 cfg->live = false;
441 }
442
443 return lru_cfg;
444 }
445
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)446 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
447 {
448 struct ad7124_channel_config *lru_cfg;
449 int free_cfg_slot;
450
451 free_cfg_slot = ad7124_find_free_config_slot(st);
452 if (free_cfg_slot >= 0) {
453 /* push the new config in configs queue */
454 kfifo_put(&st->live_cfgs_fifo, cfg);
455 } else {
456 /* pop one config to make room for the new one */
457 lru_cfg = ad7124_pop_config(st);
458 if (!lru_cfg)
459 return -EINVAL;
460
461 /* push the new config in configs queue */
462 free_cfg_slot = lru_cfg->cfg_slot;
463 kfifo_put(&st->live_cfgs_fifo, cfg);
464 }
465
466 /* mark slot as used */
467 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
468
469 return ad7124_write_config(st, cfg, free_cfg_slot);
470 }
471
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)472 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
473 {
474 ch->cfg.live = true;
475 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
476 FIELD_PREP(AD7124_CHANNEL_SETUP, ch->cfg.cfg_slot) |
477 AD7124_CHANNEL_ENABLE);
478 }
479
ad7124_prepare_read(struct ad7124_state * st,int address)480 static int ad7124_prepare_read(struct ad7124_state *st, int address)
481 {
482 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
483 struct ad7124_channel_config *live_cfg;
484
485 /*
486 * Before doing any reads assign the channel a configuration.
487 * Check if channel's config is on the device
488 */
489 if (!cfg->live) {
490 /* check if config matches another one */
491 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
492 if (!live_cfg)
493 ad7124_push_config(st, cfg);
494 else
495 cfg->cfg_slot = live_cfg->cfg_slot;
496 }
497
498 /* point channel to the config slot and enable */
499 return ad7124_enable_channel(st, &st->channels[address]);
500 }
501
__ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)502 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
503 {
504 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
505
506 return ad7124_prepare_read(st, channel);
507 }
508
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)509 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
510 {
511 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
512 int ret;
513
514 mutex_lock(&st->cfgs_lock);
515 ret = __ad7124_set_channel(sd, channel);
516 mutex_unlock(&st->cfgs_lock);
517
518 return ret;
519 }
520
ad7124_append_status(struct ad_sigma_delta * sd,bool append)521 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
522 {
523 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
524 unsigned int adc_control = st->adc_control;
525 int ret;
526
527 if (append)
528 adc_control |= AD7124_ADC_CONTROL_DATA_STATUS;
529 else
530 adc_control &= ~AD7124_ADC_CONTROL_DATA_STATUS;
531
532 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
533 if (ret < 0)
534 return ret;
535
536 st->adc_control = adc_control;
537
538 return 0;
539 }
540
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)541 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
542 {
543 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
544
545 /* The relevant thing here is that AD7124_CHANNEL_ENABLE is cleared. */
546 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0);
547 }
548
ad7124_disable_all(struct ad_sigma_delta * sd)549 static int ad7124_disable_all(struct ad_sigma_delta *sd)
550 {
551 int ret;
552 int i;
553
554 for (i = 0; i < 16; i++) {
555 ret = ad7124_disable_one(sd, i);
556 if (ret < 0)
557 return ret;
558 }
559
560 return 0;
561 }
562
563 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
564 .set_channel = ad7124_set_channel,
565 .append_status = ad7124_append_status,
566 .disable_all = ad7124_disable_all,
567 .disable_one = ad7124_disable_one,
568 .set_mode = ad7124_set_mode,
569 .has_registers = true,
570 .addr_shift = 0,
571 .read_mask = BIT(6),
572 .status_ch_mask = GENMASK(3, 0),
573 .data_reg = AD7124_DATA,
574 .num_slots = 8,
575 .irq_flags = IRQF_TRIGGER_FALLING,
576 .num_resetclks = 64,
577 };
578
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)579 static int ad7124_read_raw(struct iio_dev *indio_dev,
580 struct iio_chan_spec const *chan,
581 int *val, int *val2, long info)
582 {
583 struct ad7124_state *st = iio_priv(indio_dev);
584 int idx, ret;
585
586 switch (info) {
587 case IIO_CHAN_INFO_RAW:
588 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
589 if (ret < 0)
590 return ret;
591
592 return IIO_VAL_INT;
593 case IIO_CHAN_INFO_SCALE:
594 switch (chan->type) {
595 case IIO_VOLTAGE:
596 mutex_lock(&st->cfgs_lock);
597
598 idx = st->channels[chan->address].cfg.pga_bits;
599 *val = st->channels[chan->address].cfg.vref_mv;
600 if (st->channels[chan->address].cfg.bipolar)
601 *val2 = chan->scan_type.realbits - 1 + idx;
602 else
603 *val2 = chan->scan_type.realbits + idx;
604
605 mutex_unlock(&st->cfgs_lock);
606 return IIO_VAL_FRACTIONAL_LOG2;
607
608 case IIO_TEMP:
609 /*
610 * According to the data sheet
611 * Temperature (°C)
612 * = ((Conversion − 0x800000)/13584) − 272.5
613 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584
614 * = (Conversion − 12090248) / 13584
615 * So scale with 1000/13584 to yield °mC. Reduce by 8 to
616 * 125/1698.
617 */
618 *val = 125;
619 *val2 = 1698;
620 return IIO_VAL_FRACTIONAL;
621
622 default:
623 return -EINVAL;
624 }
625
626 case IIO_CHAN_INFO_OFFSET:
627 switch (chan->type) {
628 case IIO_VOLTAGE:
629 mutex_lock(&st->cfgs_lock);
630 if (st->channels[chan->address].cfg.bipolar)
631 *val = -(1 << (chan->scan_type.realbits - 1));
632 else
633 *val = 0;
634
635 mutex_unlock(&st->cfgs_lock);
636 return IIO_VAL_INT;
637
638 case IIO_TEMP:
639 /* see calculation above */
640 *val = -12090248;
641 return IIO_VAL_INT;
642
643 default:
644 return -EINVAL;
645 }
646
647 case IIO_CHAN_INFO_SAMP_FREQ:
648 mutex_lock(&st->cfgs_lock);
649 *val = st->channels[chan->address].cfg.odr;
650 mutex_unlock(&st->cfgs_lock);
651
652 return IIO_VAL_INT;
653 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
654 mutex_lock(&st->cfgs_lock);
655 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
656 mutex_unlock(&st->cfgs_lock);
657
658 return IIO_VAL_INT;
659 default:
660 return -EINVAL;
661 }
662 }
663
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)664 static int ad7124_write_raw(struct iio_dev *indio_dev,
665 struct iio_chan_spec const *chan,
666 int val, int val2, long info)
667 {
668 struct ad7124_state *st = iio_priv(indio_dev);
669 unsigned int res, gain, full_scale, vref;
670 int ret = 0;
671
672 mutex_lock(&st->cfgs_lock);
673
674 switch (info) {
675 case IIO_CHAN_INFO_SAMP_FREQ:
676 if (val2 != 0 || val == 0) {
677 ret = -EINVAL;
678 break;
679 }
680
681 ad7124_set_channel_odr(st, chan->address, val);
682 break;
683 case IIO_CHAN_INFO_SCALE:
684 if (val != 0) {
685 ret = -EINVAL;
686 break;
687 }
688
689 if (st->channels[chan->address].cfg.bipolar)
690 full_scale = 1 << (chan->scan_type.realbits - 1);
691 else
692 full_scale = 1 << chan->scan_type.realbits;
693
694 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
695 res = DIV_ROUND_CLOSEST(vref, full_scale);
696 gain = DIV_ROUND_CLOSEST(res, val2);
697 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
698
699 if (st->channels[chan->address].cfg.pga_bits != res)
700 st->channels[chan->address].cfg.live = false;
701
702 st->channels[chan->address].cfg.pga_bits = res;
703 break;
704 default:
705 ret = -EINVAL;
706 }
707
708 mutex_unlock(&st->cfgs_lock);
709 return ret;
710 }
711
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)712 static int ad7124_reg_access(struct iio_dev *indio_dev,
713 unsigned int reg,
714 unsigned int writeval,
715 unsigned int *readval)
716 {
717 struct ad7124_state *st = iio_priv(indio_dev);
718 int ret;
719
720 if (reg >= ARRAY_SIZE(ad7124_reg_size))
721 return -EINVAL;
722
723 if (readval)
724 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
725 readval);
726 else
727 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
728 writeval);
729
730 return ret;
731 }
732
733 static IIO_CONST_ATTR(in_voltage_scale_available,
734 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
735
736 static struct attribute *ad7124_attributes[] = {
737 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
738 NULL,
739 };
740
741 static const struct attribute_group ad7124_attrs_group = {
742 .attrs = ad7124_attributes,
743 };
744
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)745 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
746 const unsigned long *scan_mask)
747 {
748 struct ad7124_state *st = iio_priv(indio_dev);
749 bool bit_set;
750 int ret;
751 int i;
752
753 mutex_lock(&st->cfgs_lock);
754 for (i = 0; i < st->num_channels; i++) {
755 bit_set = test_bit(i, scan_mask);
756 if (bit_set)
757 ret = __ad7124_set_channel(&st->sd, i);
758 else
759 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_ENABLE,
760 0, 2);
761 if (ret < 0) {
762 mutex_unlock(&st->cfgs_lock);
763
764 return ret;
765 }
766 }
767
768 mutex_unlock(&st->cfgs_lock);
769
770 return 0;
771 }
772
773 static const struct iio_info ad7124_info = {
774 .read_raw = ad7124_read_raw,
775 .write_raw = ad7124_write_raw,
776 .debugfs_reg_access = &ad7124_reg_access,
777 .validate_trigger = ad_sd_validate_trigger,
778 .update_scan_mode = ad7124_update_scan_mode,
779 .attrs = &ad7124_attrs_group,
780 };
781
782 /* Only called during probe, so dev_err_probe() can be used */
ad7124_soft_reset(struct ad7124_state * st)783 static int ad7124_soft_reset(struct ad7124_state *st)
784 {
785 struct device *dev = &st->sd.spi->dev;
786 unsigned int readval, timeout;
787 int ret;
788
789 ret = ad_sd_reset(&st->sd);
790 if (ret < 0)
791 return ret;
792
793 fsleep(200);
794 timeout = 100;
795 do {
796 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
797 if (ret < 0)
798 return dev_err_probe(dev, ret, "Error reading status register\n");
799
800 if (!(readval & AD7124_STATUS_POR_FLAG))
801 break;
802
803 /* The AD7124 requires typically 2ms to power up and settle */
804 usleep_range(100, 2000);
805 } while (--timeout);
806
807 if (readval & AD7124_STATUS_POR_FLAG)
808 return dev_err_probe(dev, -EIO, "Soft reset failed\n");
809
810 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->gain_default);
811 if (ret < 0)
812 return dev_err_probe(dev, ret, "Error reading gain register\n");
813
814 dev_dbg(dev, "Reset value of GAIN register is 0x%x\n", st->gain_default);
815
816 return 0;
817 }
818
ad7124_check_chip_id(struct ad7124_state * st)819 static int ad7124_check_chip_id(struct ad7124_state *st)
820 {
821 struct device *dev = &st->sd.spi->dev;
822 unsigned int readval, chip_id, silicon_rev;
823 int ret;
824
825 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
826 if (ret < 0)
827 return dev_err_probe(dev, ret, "Failure to read ID register\n");
828
829 chip_id = FIELD_GET(AD7124_ID_DEVICE_ID, readval);
830 silicon_rev = FIELD_GET(AD7124_ID_SILICON_REVISION, readval);
831
832 if (chip_id != st->chip_info->chip_id)
833 return dev_err_probe(dev, -ENODEV,
834 "Chip ID mismatch: expected %u, got %u\n",
835 st->chip_info->chip_id, chip_id);
836
837 if (silicon_rev == 0)
838 return dev_err_probe(dev, -ENODEV,
839 "Silicon revision empty. Chip may not be present\n");
840
841 return 0;
842 }
843
844 enum {
845 AD7124_SYSCALIB_ZERO_SCALE,
846 AD7124_SYSCALIB_FULL_SCALE,
847 };
848
ad7124_syscalib_locked(struct ad7124_state * st,const struct iio_chan_spec * chan)849 static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan_spec *chan)
850 {
851 struct device *dev = &st->sd.spi->dev;
852 struct ad7124_channel *ch = &st->channels[chan->channel];
853 int ret;
854
855 if (ch->syscalib_mode == AD7124_SYSCALIB_ZERO_SCALE) {
856 ch->cfg.calibration_offset = 0x800000;
857
858 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB,
859 chan->address);
860 if (ret < 0)
861 return ret;
862
863 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(ch->cfg.cfg_slot), 3,
864 &ch->cfg.calibration_offset);
865 if (ret < 0)
866 return ret;
867
868 dev_dbg(dev, "offset for channel %d after zero-scale calibration: 0x%x\n",
869 chan->channel, ch->cfg.calibration_offset);
870 } else {
871 ch->cfg.calibration_gain = st->gain_default;
872
873 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB,
874 chan->address);
875 if (ret < 0)
876 return ret;
877
878 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(ch->cfg.cfg_slot), 3,
879 &ch->cfg.calibration_gain);
880 if (ret < 0)
881 return ret;
882
883 dev_dbg(dev, "gain for channel %d after full-scale calibration: 0x%x\n",
884 chan->channel, ch->cfg.calibration_gain);
885 }
886
887 return 0;
888 }
889
ad7124_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)890 static ssize_t ad7124_write_syscalib(struct iio_dev *indio_dev,
891 uintptr_t private,
892 const struct iio_chan_spec *chan,
893 const char *buf, size_t len)
894 {
895 struct ad7124_state *st = iio_priv(indio_dev);
896 bool sys_calib;
897 int ret;
898
899 ret = kstrtobool(buf, &sys_calib);
900 if (ret)
901 return ret;
902
903 if (!sys_calib)
904 return len;
905
906 if (!iio_device_claim_direct(indio_dev))
907 return -EBUSY;
908
909 ret = ad7124_syscalib_locked(st, chan);
910
911 iio_device_release_direct(indio_dev);
912
913 return ret ?: len;
914 }
915
916 static const char * const ad7124_syscalib_modes[] = {
917 [AD7124_SYSCALIB_ZERO_SCALE] = "zero_scale",
918 [AD7124_SYSCALIB_FULL_SCALE] = "full_scale",
919 };
920
ad7124_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)921 static int ad7124_set_syscalib_mode(struct iio_dev *indio_dev,
922 const struct iio_chan_spec *chan,
923 unsigned int mode)
924 {
925 struct ad7124_state *st = iio_priv(indio_dev);
926
927 st->channels[chan->channel].syscalib_mode = mode;
928
929 return 0;
930 }
931
ad7124_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)932 static int ad7124_get_syscalib_mode(struct iio_dev *indio_dev,
933 const struct iio_chan_spec *chan)
934 {
935 struct ad7124_state *st = iio_priv(indio_dev);
936
937 return st->channels[chan->channel].syscalib_mode;
938 }
939
940 static const struct iio_enum ad7124_syscalib_mode_enum = {
941 .items = ad7124_syscalib_modes,
942 .num_items = ARRAY_SIZE(ad7124_syscalib_modes),
943 .set = ad7124_set_syscalib_mode,
944 .get = ad7124_get_syscalib_mode
945 };
946
947 static const struct iio_chan_spec_ext_info ad7124_calibsys_ext_info[] = {
948 {
949 .name = "sys_calibration",
950 .write = ad7124_write_syscalib,
951 .shared = IIO_SEPARATE,
952 },
953 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
954 &ad7124_syscalib_mode_enum),
955 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
956 &ad7124_syscalib_mode_enum),
957 { }
958 };
959
960 static const struct iio_chan_spec ad7124_channel_template = {
961 .type = IIO_VOLTAGE,
962 .indexed = 1,
963 .differential = 1,
964 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
965 BIT(IIO_CHAN_INFO_SCALE) |
966 BIT(IIO_CHAN_INFO_OFFSET) |
967 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
968 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
969 .scan_type = {
970 .sign = 'u',
971 .realbits = 24,
972 .storagebits = 32,
973 .endianness = IIO_BE,
974 },
975 .ext_info = ad7124_calibsys_ext_info,
976 };
977
978 /*
979 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4
980 * while they are fine for ad7124-8. Values above 31 don't fit
981 * into the register field and so are invalid for sure.
982 */
ad7124_valid_input_select(unsigned int ain,const struct ad7124_chip_info * info)983 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info)
984 {
985 if (ain >= info->num_inputs && ain < 16)
986 return false;
987
988 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM);
989 }
990
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)991 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
992 struct device *dev)
993 {
994 struct ad7124_state *st = iio_priv(indio_dev);
995 struct ad7124_channel_config *cfg;
996 struct ad7124_channel *channels;
997 struct iio_chan_spec *chan;
998 unsigned int ain[2], channel = 0, tmp;
999 unsigned int num_channels;
1000 int ret;
1001
1002 num_channels = device_get_child_node_count(dev);
1003
1004 /*
1005 * The driver assigns each logical channel defined in the device tree
1006 * statically one channel register. So only accept 16 such logical
1007 * channels to not treat CONFIG_0 (i.e. the register following
1008 * CHANNEL_15) as an additional channel register. The driver could be
1009 * improved to lift this limitation.
1010 */
1011 if (num_channels > AD7124_MAX_CHANNELS)
1012 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n");
1013
1014 /* Add one for temperature */
1015 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS);
1016
1017 chan = devm_kcalloc(dev, st->num_channels,
1018 sizeof(*chan), GFP_KERNEL);
1019 if (!chan)
1020 return -ENOMEM;
1021
1022 channels = devm_kcalloc(dev, st->num_channels, sizeof(*channels),
1023 GFP_KERNEL);
1024 if (!channels)
1025 return -ENOMEM;
1026
1027 indio_dev->channels = chan;
1028 indio_dev->num_channels = st->num_channels;
1029 st->channels = channels;
1030
1031 device_for_each_child_node_scoped(dev, child) {
1032 ret = fwnode_property_read_u32(child, "reg", &channel);
1033 if (ret)
1034 return dev_err_probe(dev, ret,
1035 "Failed to parse reg property of %pfwP\n", child);
1036
1037 if (channel >= num_channels)
1038 return dev_err_probe(dev, -EINVAL,
1039 "Channel index >= number of channels in %pfwP\n", child);
1040
1041 ret = fwnode_property_read_u32_array(child, "diff-channels",
1042 ain, 2);
1043 if (ret)
1044 return dev_err_probe(dev, ret,
1045 "Failed to parse diff-channels property of %pfwP\n", child);
1046
1047 if (!ad7124_valid_input_select(ain[0], st->chip_info) ||
1048 !ad7124_valid_input_select(ain[1], st->chip_info))
1049 return dev_err_probe(dev, -EINVAL,
1050 "diff-channels property of %pfwP contains invalid data\n", child);
1051
1052 st->channels[channel].nr = channel;
1053 st->channels[channel].ain = FIELD_PREP(AD7124_CHANNEL_AINP, ain[0]) |
1054 FIELD_PREP(AD7124_CHANNEL_AINM, ain[1]);
1055
1056 cfg = &st->channels[channel].cfg;
1057 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
1058
1059 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
1060 if (ret)
1061 cfg->refsel = AD7124_INT_REF;
1062 else
1063 cfg->refsel = tmp;
1064
1065 cfg->buf_positive =
1066 fwnode_property_read_bool(child, "adi,buffered-positive");
1067 cfg->buf_negative =
1068 fwnode_property_read_bool(child, "adi,buffered-negative");
1069
1070 chan[channel] = ad7124_channel_template;
1071 chan[channel].address = channel;
1072 chan[channel].scan_index = channel;
1073 chan[channel].channel = ain[0];
1074 chan[channel].channel2 = ain[1];
1075 }
1076
1077 if (num_channels < AD7124_MAX_CHANNELS) {
1078 st->channels[num_channels] = (struct ad7124_channel) {
1079 .nr = num_channels,
1080 .ain = FIELD_PREP(AD7124_CHANNEL_AINP, AD7124_CHANNEL_AINx_TEMPSENSOR) |
1081 FIELD_PREP(AD7124_CHANNEL_AINM, AD7124_CHANNEL_AINx_AVSS),
1082 .cfg = {
1083 .bipolar = true,
1084 },
1085 };
1086
1087 chan[num_channels] = (struct iio_chan_spec) {
1088 .type = IIO_TEMP,
1089 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1090 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1091 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1092 .scan_type = {
1093 /*
1094 * You might find it strange that a bipolar
1095 * measurement yields an unsigned value, but
1096 * this matches the device's manual.
1097 */
1098 .sign = 'u',
1099 .realbits = 24,
1100 .storagebits = 32,
1101 .endianness = IIO_BE,
1102 },
1103 .address = num_channels,
1104 .scan_index = num_channels,
1105 };
1106 }
1107
1108 return 0;
1109 }
1110
ad7124_setup(struct ad7124_state * st)1111 static int ad7124_setup(struct ad7124_state *st)
1112 {
1113 struct device *dev = &st->sd.spi->dev;
1114 unsigned int fclk, power_mode;
1115 int i, ret;
1116
1117 fclk = clk_get_rate(st->mclk);
1118 if (!fclk)
1119 return dev_err_probe(dev, -EINVAL, "Failed to get mclk rate\n");
1120
1121 /* The power mode changes the master clock frequency */
1122 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
1123 ARRAY_SIZE(ad7124_master_clk_freq_hz),
1124 fclk);
1125 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
1126 ret = clk_set_rate(st->mclk, fclk);
1127 if (ret)
1128 return dev_err_probe(dev, ret, "Failed to set mclk rate\n");
1129 }
1130
1131 /* Set the power mode */
1132 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE;
1133 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, power_mode);
1134
1135 st->adc_control &= ~AD7124_ADC_CONTROL_MODE;
1136 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, AD_SD_MODE_IDLE);
1137
1138 mutex_init(&st->cfgs_lock);
1139 INIT_KFIFO(st->live_cfgs_fifo);
1140 for (i = 0; i < st->num_channels; i++) {
1141
1142 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
1143 if (ret < 0)
1144 return ret;
1145
1146 /*
1147 * 9.38 SPS is the minimum output data rate supported
1148 * regardless of the selected power mode. Round it up to 10 and
1149 * set all channels to this default value.
1150 */
1151 ad7124_set_channel_odr(st, i, 10);
1152 }
1153
1154 ad7124_disable_all(&st->sd);
1155
1156 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
1157 if (ret < 0)
1158 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n");
1159
1160 return ret;
1161 }
1162
__ad7124_calibrate_all(struct ad7124_state * st,struct iio_dev * indio_dev)1163 static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev)
1164 {
1165 struct device *dev = &st->sd.spi->dev;
1166 int ret, i;
1167
1168 for (i = 0; i < st->num_channels; i++) {
1169
1170 if (indio_dev->channels[i].type != IIO_VOLTAGE)
1171 continue;
1172
1173 /*
1174 * For calibration the OFFSET register should hold its reset default
1175 * value. For the GAIN register there is no such requirement but
1176 * for gain 1 it should hold the reset default value, too. So to
1177 * simplify matters use the reset default value for both.
1178 */
1179 st->channels[i].cfg.calibration_offset = 0x800000;
1180 st->channels[i].cfg.calibration_gain = st->gain_default;
1181
1182 /*
1183 * Full-scale calibration isn't supported at gain 1, so skip in
1184 * that case. Note that untypically full-scale calibration has
1185 * to happen before zero-scale calibration. This only applies to
1186 * the internal calibration. For system calibration it's as
1187 * usual: first zero-scale then full-scale calibration.
1188 */
1189 if (st->channels[i].cfg.pga_bits > 0) {
1190 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB, i);
1191 if (ret < 0)
1192 return ret;
1193
1194 /*
1195 * read out the resulting value of GAIN
1196 * after full-scale calibration because the next
1197 * ad_sd_calibrate() call overwrites this via
1198 * ad_sigma_delta_set_channel() -> ad7124_set_channel()
1199 * ... -> ad7124_enable_channel().
1200 */
1201 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(st->channels[i].cfg.cfg_slot), 3,
1202 &st->channels[i].cfg.calibration_gain);
1203 if (ret < 0)
1204 return ret;
1205 }
1206
1207 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB, i);
1208 if (ret < 0)
1209 return ret;
1210
1211 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(st->channels[i].cfg.cfg_slot), 3,
1212 &st->channels[i].cfg.calibration_offset);
1213 if (ret < 0)
1214 return ret;
1215
1216 dev_dbg(dev, "offset and gain for channel %d = 0x%x + 0x%x\n", i,
1217 st->channels[i].cfg.calibration_offset,
1218 st->channels[i].cfg.calibration_gain);
1219 }
1220
1221 return 0;
1222 }
1223
ad7124_calibrate_all(struct ad7124_state * st,struct iio_dev * indio_dev)1224 static int ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev)
1225 {
1226 int ret;
1227 unsigned int adc_control = st->adc_control;
1228
1229 /*
1230 * Calibration isn't supported at full power, so speed down a bit.
1231 * Setting .adc_control is enough here because the control register is
1232 * written as part of ad_sd_calibrate() -> ad_sigma_delta_set_mode().
1233 * The resulting calibration is then also valid for high-speed, so just
1234 * restore adc_control afterwards.
1235 */
1236 if (FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, adc_control) >= AD7124_FULL_POWER) {
1237 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE;
1238 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, AD7124_MID_POWER);
1239 }
1240
1241 ret = __ad7124_calibrate_all(st, indio_dev);
1242
1243 st->adc_control = adc_control;
1244
1245 return ret;
1246 }
1247
ad7124_reg_disable(void * r)1248 static void ad7124_reg_disable(void *r)
1249 {
1250 regulator_disable(r);
1251 }
1252
ad7124_probe(struct spi_device * spi)1253 static int ad7124_probe(struct spi_device *spi)
1254 {
1255 const struct ad7124_chip_info *info;
1256 struct device *dev = &spi->dev;
1257 struct ad7124_state *st;
1258 struct iio_dev *indio_dev;
1259 int i, ret;
1260
1261 info = spi_get_device_match_data(spi);
1262 if (!info)
1263 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n");
1264
1265 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1266 if (!indio_dev)
1267 return -ENOMEM;
1268
1269 st = iio_priv(indio_dev);
1270
1271 st->chip_info = info;
1272
1273 indio_dev->name = st->chip_info->name;
1274 indio_dev->modes = INDIO_DIRECT_MODE;
1275 indio_dev->info = &ad7124_info;
1276
1277 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
1278 if (ret < 0)
1279 return ret;
1280
1281 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
1282 if (ret < 0)
1283 return ret;
1284
1285 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
1286 if (i == AD7124_INT_REF)
1287 continue;
1288
1289 st->vref[i] = devm_regulator_get_optional(&spi->dev,
1290 ad7124_ref_names[i]);
1291 if (PTR_ERR(st->vref[i]) == -ENODEV)
1292 continue;
1293 else if (IS_ERR(st->vref[i]))
1294 return PTR_ERR(st->vref[i]);
1295
1296 ret = regulator_enable(st->vref[i]);
1297 if (ret)
1298 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i);
1299
1300 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
1301 st->vref[i]);
1302 if (ret)
1303 return dev_err_probe(dev, ret, "Failed to register disable handler for regulator #%d\n", i);
1304 }
1305
1306 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
1307 if (IS_ERR(st->mclk))
1308 return dev_err_probe(dev, PTR_ERR(st->mclk), "Failed to get mclk\n");
1309
1310 ret = ad7124_soft_reset(st);
1311 if (ret < 0)
1312 return ret;
1313
1314 ret = ad7124_check_chip_id(st);
1315 if (ret)
1316 return ret;
1317
1318 ret = ad7124_setup(st);
1319 if (ret < 0)
1320 return ret;
1321
1322 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1323 if (ret < 0)
1324 return dev_err_probe(dev, ret, "Failed to setup triggers\n");
1325
1326 ret = ad7124_calibrate_all(st, indio_dev);
1327 if (ret)
1328 return ret;
1329
1330 ret = devm_iio_device_register(&spi->dev, indio_dev);
1331 if (ret < 0)
1332 return dev_err_probe(dev, ret, "Failed to register iio device\n");
1333
1334 return 0;
1335 }
1336
1337 static const struct of_device_id ad7124_of_match[] = {
1338 { .compatible = "adi,ad7124-4", .data = &ad7124_4_chip_info },
1339 { .compatible = "adi,ad7124-8", .data = &ad7124_8_chip_info },
1340 { }
1341 };
1342 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1343
1344 static const struct spi_device_id ad71124_ids[] = {
1345 { "ad7124-4", (kernel_ulong_t)&ad7124_4_chip_info },
1346 { "ad7124-8", (kernel_ulong_t)&ad7124_8_chip_info },
1347 { }
1348 };
1349 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1350
1351 static struct spi_driver ad71124_driver = {
1352 .driver = {
1353 .name = "ad7124",
1354 .of_match_table = ad7124_of_match,
1355 },
1356 .probe = ad7124_probe,
1357 .id_table = ad71124_ids,
1358 };
1359 module_spi_driver(ad71124_driver);
1360
1361 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1362 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1363 MODULE_LICENSE("GPL");
1364 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1365