xref: /linux/arch/arm64/include/asm/insn.h (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Huawei Ltd.
4  * Author: Jiang Liu <liuj97@gmail.com>
5  *
6  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
7  */
8 #ifndef	__ASM_INSN_H
9 #define	__ASM_INSN_H
10 #include <linux/build_bug.h>
11 #include <linux/types.h>
12 
13 #include <asm/insn-def.h>
14 
15 #ifndef __ASSEMBLY__
16 
17 enum aarch64_insn_hint_cr_op {
18 	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
19 	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
20 	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
21 	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
22 	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
23 	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
24 
25 	AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
26 	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 	AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
29 	AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
30 	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
31 	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
32 	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
33 	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
34 	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
35 	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
36 	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
37 	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
38 
39 	AARCH64_INSN_HINT_ESB  = 0x10 << 5,
40 	AARCH64_INSN_HINT_PSB  = 0x11 << 5,
41 	AARCH64_INSN_HINT_TSB  = 0x12 << 5,
42 	AARCH64_INSN_HINT_CSDB = 0x14 << 5,
43 	AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
44 
45 	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
46 	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
47 	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
48 	AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
49 };
50 
51 enum aarch64_insn_imm_type {
52 	AARCH64_INSN_IMM_ADR,
53 	AARCH64_INSN_IMM_26,
54 	AARCH64_INSN_IMM_19,
55 	AARCH64_INSN_IMM_16,
56 	AARCH64_INSN_IMM_14,
57 	AARCH64_INSN_IMM_12,
58 	AARCH64_INSN_IMM_9,
59 	AARCH64_INSN_IMM_7,
60 	AARCH64_INSN_IMM_6,
61 	AARCH64_INSN_IMM_S,
62 	AARCH64_INSN_IMM_R,
63 	AARCH64_INSN_IMM_N,
64 	AARCH64_INSN_IMM_MAX
65 };
66 
67 enum aarch64_insn_register_type {
68 	AARCH64_INSN_REGTYPE_RT,
69 	AARCH64_INSN_REGTYPE_RN,
70 	AARCH64_INSN_REGTYPE_RT2,
71 	AARCH64_INSN_REGTYPE_RM,
72 	AARCH64_INSN_REGTYPE_RD,
73 	AARCH64_INSN_REGTYPE_RA,
74 	AARCH64_INSN_REGTYPE_RS,
75 };
76 
77 enum aarch64_insn_register {
78 	AARCH64_INSN_REG_0  = 0,
79 	AARCH64_INSN_REG_1  = 1,
80 	AARCH64_INSN_REG_2  = 2,
81 	AARCH64_INSN_REG_3  = 3,
82 	AARCH64_INSN_REG_4  = 4,
83 	AARCH64_INSN_REG_5  = 5,
84 	AARCH64_INSN_REG_6  = 6,
85 	AARCH64_INSN_REG_7  = 7,
86 	AARCH64_INSN_REG_8  = 8,
87 	AARCH64_INSN_REG_9  = 9,
88 	AARCH64_INSN_REG_10 = 10,
89 	AARCH64_INSN_REG_11 = 11,
90 	AARCH64_INSN_REG_12 = 12,
91 	AARCH64_INSN_REG_13 = 13,
92 	AARCH64_INSN_REG_14 = 14,
93 	AARCH64_INSN_REG_15 = 15,
94 	AARCH64_INSN_REG_16 = 16,
95 	AARCH64_INSN_REG_17 = 17,
96 	AARCH64_INSN_REG_18 = 18,
97 	AARCH64_INSN_REG_19 = 19,
98 	AARCH64_INSN_REG_20 = 20,
99 	AARCH64_INSN_REG_21 = 21,
100 	AARCH64_INSN_REG_22 = 22,
101 	AARCH64_INSN_REG_23 = 23,
102 	AARCH64_INSN_REG_24 = 24,
103 	AARCH64_INSN_REG_25 = 25,
104 	AARCH64_INSN_REG_26 = 26,
105 	AARCH64_INSN_REG_27 = 27,
106 	AARCH64_INSN_REG_28 = 28,
107 	AARCH64_INSN_REG_29 = 29,
108 	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
109 	AARCH64_INSN_REG_30 = 30,
110 	AARCH64_INSN_REG_LR = 30, /* Link register */
111 	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
112 	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
113 };
114 
115 enum aarch64_insn_special_register {
116 	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
117 	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
118 	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
119 	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
120 	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
121 	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
122 	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
123 	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
124 	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
125 	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
126 	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
127 	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
128 	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
129 	AARCH64_INSN_SPCLREG_SPSR_INQ	= 0xE218,
130 	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
131 	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
132 	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
133 	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
134 	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
135 	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF210
136 };
137 
138 enum aarch64_insn_system_register {
139 	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0x4684,
140 	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0x6682,
141 	AARCH64_INSN_SYSREG_SP_EL0	= 0x4208,
142 };
143 
144 enum aarch64_insn_variant {
145 	AARCH64_INSN_VARIANT_32BIT,
146 	AARCH64_INSN_VARIANT_64BIT
147 };
148 
149 enum aarch64_insn_condition {
150 	AARCH64_INSN_COND_EQ = 0x0, /* == */
151 	AARCH64_INSN_COND_NE = 0x1, /* != */
152 	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
153 	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
154 	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
155 	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
156 	AARCH64_INSN_COND_VS = 0x6, /* overflow */
157 	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
158 	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
159 	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
160 	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
161 	AARCH64_INSN_COND_LT = 0xb, /* signed < */
162 	AARCH64_INSN_COND_GT = 0xc, /* signed > */
163 	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
164 	AARCH64_INSN_COND_AL = 0xe, /* always */
165 };
166 
167 enum aarch64_insn_branch_type {
168 	AARCH64_INSN_BRANCH_NOLINK,
169 	AARCH64_INSN_BRANCH_LINK,
170 	AARCH64_INSN_BRANCH_RETURN,
171 	AARCH64_INSN_BRANCH_COMP_ZERO,
172 	AARCH64_INSN_BRANCH_COMP_NONZERO,
173 };
174 
175 enum aarch64_insn_size_type {
176 	AARCH64_INSN_SIZE_8,
177 	AARCH64_INSN_SIZE_16,
178 	AARCH64_INSN_SIZE_32,
179 	AARCH64_INSN_SIZE_64,
180 };
181 
182 enum aarch64_insn_ldst_type {
183 	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
184 	AARCH64_INSN_LDST_STORE_REG_OFFSET,
185 	AARCH64_INSN_LDST_LOAD_IMM_OFFSET,
186 	AARCH64_INSN_LDST_STORE_IMM_OFFSET,
187 	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
188 	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
189 	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
190 	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
191 	AARCH64_INSN_LDST_LOAD_EX,
192 	AARCH64_INSN_LDST_LOAD_ACQ_EX,
193 	AARCH64_INSN_LDST_STORE_EX,
194 	AARCH64_INSN_LDST_STORE_REL_EX,
195 	AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET,
196 	AARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET,
197 };
198 
199 enum aarch64_insn_adsb_type {
200 	AARCH64_INSN_ADSB_ADD,
201 	AARCH64_INSN_ADSB_SUB,
202 	AARCH64_INSN_ADSB_ADD_SETFLAGS,
203 	AARCH64_INSN_ADSB_SUB_SETFLAGS
204 };
205 
206 enum aarch64_insn_movewide_type {
207 	AARCH64_INSN_MOVEWIDE_ZERO,
208 	AARCH64_INSN_MOVEWIDE_KEEP,
209 	AARCH64_INSN_MOVEWIDE_INVERSE
210 };
211 
212 enum aarch64_insn_bitfield_type {
213 	AARCH64_INSN_BITFIELD_MOVE,
214 	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
215 	AARCH64_INSN_BITFIELD_MOVE_SIGNED
216 };
217 
218 enum aarch64_insn_data1_type {
219 	AARCH64_INSN_DATA1_REVERSE_16,
220 	AARCH64_INSN_DATA1_REVERSE_32,
221 	AARCH64_INSN_DATA1_REVERSE_64,
222 };
223 
224 enum aarch64_insn_data2_type {
225 	AARCH64_INSN_DATA2_UDIV,
226 	AARCH64_INSN_DATA2_SDIV,
227 	AARCH64_INSN_DATA2_LSLV,
228 	AARCH64_INSN_DATA2_LSRV,
229 	AARCH64_INSN_DATA2_ASRV,
230 	AARCH64_INSN_DATA2_RORV,
231 };
232 
233 enum aarch64_insn_data3_type {
234 	AARCH64_INSN_DATA3_MADD,
235 	AARCH64_INSN_DATA3_MSUB,
236 };
237 
238 enum aarch64_insn_logic_type {
239 	AARCH64_INSN_LOGIC_AND,
240 	AARCH64_INSN_LOGIC_BIC,
241 	AARCH64_INSN_LOGIC_ORR,
242 	AARCH64_INSN_LOGIC_ORN,
243 	AARCH64_INSN_LOGIC_EOR,
244 	AARCH64_INSN_LOGIC_EON,
245 	AARCH64_INSN_LOGIC_AND_SETFLAGS,
246 	AARCH64_INSN_LOGIC_BIC_SETFLAGS
247 };
248 
249 enum aarch64_insn_prfm_type {
250 	AARCH64_INSN_PRFM_TYPE_PLD,
251 	AARCH64_INSN_PRFM_TYPE_PLI,
252 	AARCH64_INSN_PRFM_TYPE_PST,
253 };
254 
255 enum aarch64_insn_prfm_target {
256 	AARCH64_INSN_PRFM_TARGET_L1,
257 	AARCH64_INSN_PRFM_TARGET_L2,
258 	AARCH64_INSN_PRFM_TARGET_L3,
259 };
260 
261 enum aarch64_insn_prfm_policy {
262 	AARCH64_INSN_PRFM_POLICY_KEEP,
263 	AARCH64_INSN_PRFM_POLICY_STRM,
264 };
265 
266 enum aarch64_insn_adr_type {
267 	AARCH64_INSN_ADR_TYPE_ADRP,
268 	AARCH64_INSN_ADR_TYPE_ADR,
269 };
270 
271 enum aarch64_insn_mem_atomic_op {
272 	AARCH64_INSN_MEM_ATOMIC_ADD,
273 	AARCH64_INSN_MEM_ATOMIC_CLR,
274 	AARCH64_INSN_MEM_ATOMIC_EOR,
275 	AARCH64_INSN_MEM_ATOMIC_SET,
276 	AARCH64_INSN_MEM_ATOMIC_SWP,
277 };
278 
279 enum aarch64_insn_mem_order_type {
280 	AARCH64_INSN_MEM_ORDER_NONE,
281 	AARCH64_INSN_MEM_ORDER_ACQ,
282 	AARCH64_INSN_MEM_ORDER_REL,
283 	AARCH64_INSN_MEM_ORDER_ACQREL,
284 };
285 
286 enum aarch64_insn_mb_type {
287 	AARCH64_INSN_MB_SY,
288 	AARCH64_INSN_MB_ST,
289 	AARCH64_INSN_MB_LD,
290 	AARCH64_INSN_MB_ISH,
291 	AARCH64_INSN_MB_ISHST,
292 	AARCH64_INSN_MB_ISHLD,
293 	AARCH64_INSN_MB_NSH,
294 	AARCH64_INSN_MB_NSHST,
295 	AARCH64_INSN_MB_NSHLD,
296 	AARCH64_INSN_MB_OSH,
297 	AARCH64_INSN_MB_OSHST,
298 	AARCH64_INSN_MB_OSHLD,
299 };
300 
301 #define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\
302 static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\
303 {									\
304 	BUILD_BUG_ON(~(mask) & (val));					\
305 	return (code & (mask)) == (val);				\
306 }									\
307 static __always_inline u32 aarch64_insn_get_##abbr##_value(void)	\
308 {									\
309 	return (val);							\
310 }
311 
312 /*
313  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
314  * Section C3.1 "A64 instruction index by encoding":
315  * AArch64 main encoding table
316  *  Bit position
317  *   28 27 26 25	Encoding Group
318  *   0  0  -  -		Unallocated
319  *   1  0  0  -		Data processing, immediate
320  *   1  0  1  -		Branch, exception generation and system instructions
321  *   -  1  -  0		Loads and stores
322  *   -  1  0  1		Data processing - register
323  *   0  1  1  1		Data processing - SIMD and floating point
324  *   1  1  1  1		Data processing - SIMD and floating point
325  * "-" means "don't care"
326  */
327 __AARCH64_INSN_FUNCS(class_branch_sys,	0x1c000000, 0x14000000)
328 
329 __AARCH64_INSN_FUNCS(adr,	0x9F000000, 0x10000000)
330 __AARCH64_INSN_FUNCS(adrp,	0x9F000000, 0x90000000)
331 __AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)
332 __AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)
333 __AARCH64_INSN_FUNCS(store_imm,	0x3FC00000, 0x39000000)
334 __AARCH64_INSN_FUNCS(load_imm,	0x3FC00000, 0x39400000)
335 __AARCH64_INSN_FUNCS(signed_load_imm, 0X3FC00000, 0x39800000)
336 __AARCH64_INSN_FUNCS(store_pre,	0x3FE00C00, 0x38000C00)
337 __AARCH64_INSN_FUNCS(load_pre,	0x3FE00C00, 0x38400C00)
338 __AARCH64_INSN_FUNCS(store_post,	0x3FE00C00, 0x38000400)
339 __AARCH64_INSN_FUNCS(load_post,	0x3FE00C00, 0x38400400)
340 __AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)
341 __AARCH64_INSN_FUNCS(str_imm,	0x3FC00000, 0x39000000)
342 __AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0x38200000)
343 __AARCH64_INSN_FUNCS(ldclr,	0x3F20FC00, 0x38201000)
344 __AARCH64_INSN_FUNCS(ldeor,	0x3F20FC00, 0x38202000)
345 __AARCH64_INSN_FUNCS(ldset,	0x3F20FC00, 0x38203000)
346 __AARCH64_INSN_FUNCS(swp,	0x3F20FC00, 0x38208000)
347 __AARCH64_INSN_FUNCS(cas,	0x3FA07C00, 0x08A07C00)
348 __AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)
349 __AARCH64_INSN_FUNCS(signed_ldr_reg, 0X3FE0FC00, 0x38A0E800)
350 __AARCH64_INSN_FUNCS(ldr_imm,	0x3FC00000, 0x39400000)
351 __AARCH64_INSN_FUNCS(ldr_lit,	0xBF000000, 0x18000000)
352 __AARCH64_INSN_FUNCS(ldrsw_lit,	0xFF000000, 0x98000000)
353 __AARCH64_INSN_FUNCS(exclusive,	0x3F800000, 0x08000000)
354 __AARCH64_INSN_FUNCS(load_ex,	0x3F400000, 0x08400000)
355 __AARCH64_INSN_FUNCS(store_ex,	0x3F400000, 0x08000000)
356 __AARCH64_INSN_FUNCS(stp,	0x7FC00000, 0x29000000)
357 __AARCH64_INSN_FUNCS(ldp,	0x7FC00000, 0x29400000)
358 __AARCH64_INSN_FUNCS(stp_post,	0x7FC00000, 0x28800000)
359 __AARCH64_INSN_FUNCS(ldp_post,	0x7FC00000, 0x28C00000)
360 __AARCH64_INSN_FUNCS(stp_pre,	0x7FC00000, 0x29800000)
361 __AARCH64_INSN_FUNCS(ldp_pre,	0x7FC00000, 0x29C00000)
362 __AARCH64_INSN_FUNCS(add_imm,	0x7F000000, 0x11000000)
363 __AARCH64_INSN_FUNCS(adds_imm,	0x7F000000, 0x31000000)
364 __AARCH64_INSN_FUNCS(sub_imm,	0x7F000000, 0x51000000)
365 __AARCH64_INSN_FUNCS(subs_imm,	0x7F000000, 0x71000000)
366 __AARCH64_INSN_FUNCS(movn,	0x7F800000, 0x12800000)
367 __AARCH64_INSN_FUNCS(sbfm,	0x7F800000, 0x13000000)
368 __AARCH64_INSN_FUNCS(bfm,	0x7F800000, 0x33000000)
369 __AARCH64_INSN_FUNCS(movz,	0x7F800000, 0x52800000)
370 __AARCH64_INSN_FUNCS(ubfm,	0x7F800000, 0x53000000)
371 __AARCH64_INSN_FUNCS(movk,	0x7F800000, 0x72800000)
372 __AARCH64_INSN_FUNCS(add,	0x7F200000, 0x0B000000)
373 __AARCH64_INSN_FUNCS(adds,	0x7F200000, 0x2B000000)
374 __AARCH64_INSN_FUNCS(sub,	0x7F200000, 0x4B000000)
375 __AARCH64_INSN_FUNCS(subs,	0x7F200000, 0x6B000000)
376 __AARCH64_INSN_FUNCS(madd,	0x7FE08000, 0x1B000000)
377 __AARCH64_INSN_FUNCS(msub,	0x7FE08000, 0x1B008000)
378 __AARCH64_INSN_FUNCS(udiv,	0x7FE0FC00, 0x1AC00800)
379 __AARCH64_INSN_FUNCS(sdiv,	0x7FE0FC00, 0x1AC00C00)
380 __AARCH64_INSN_FUNCS(lslv,	0x7FE0FC00, 0x1AC02000)
381 __AARCH64_INSN_FUNCS(lsrv,	0x7FE0FC00, 0x1AC02400)
382 __AARCH64_INSN_FUNCS(asrv,	0x7FE0FC00, 0x1AC02800)
383 __AARCH64_INSN_FUNCS(rorv,	0x7FE0FC00, 0x1AC02C00)
384 __AARCH64_INSN_FUNCS(rev16,	0x7FFFFC00, 0x5AC00400)
385 __AARCH64_INSN_FUNCS(rev32,	0x7FFFFC00, 0x5AC00800)
386 __AARCH64_INSN_FUNCS(rev64,	0x7FFFFC00, 0x5AC00C00)
387 __AARCH64_INSN_FUNCS(and,	0x7F200000, 0x0A000000)
388 __AARCH64_INSN_FUNCS(bic,	0x7F200000, 0x0A200000)
389 __AARCH64_INSN_FUNCS(orr,	0x7F200000, 0x2A000000)
390 __AARCH64_INSN_FUNCS(mov_reg,	0x7FE0FFE0, 0x2A0003E0)
391 __AARCH64_INSN_FUNCS(orn,	0x7F200000, 0x2A200000)
392 __AARCH64_INSN_FUNCS(eor,	0x7F200000, 0x4A000000)
393 __AARCH64_INSN_FUNCS(eon,	0x7F200000, 0x4A200000)
394 __AARCH64_INSN_FUNCS(ands,	0x7F200000, 0x6A000000)
395 __AARCH64_INSN_FUNCS(bics,	0x7F200000, 0x6A200000)
396 __AARCH64_INSN_FUNCS(and_imm,	0x7F800000, 0x12000000)
397 __AARCH64_INSN_FUNCS(orr_imm,	0x7F800000, 0x32000000)
398 __AARCH64_INSN_FUNCS(eor_imm,	0x7F800000, 0x52000000)
399 __AARCH64_INSN_FUNCS(ands_imm,	0x7F800000, 0x72000000)
400 __AARCH64_INSN_FUNCS(extr,	0x7FA00000, 0x13800000)
401 __AARCH64_INSN_FUNCS(b,		0xFC000000, 0x14000000)
402 __AARCH64_INSN_FUNCS(bl,	0xFC000000, 0x94000000)
403 __AARCH64_INSN_FUNCS(cbz,	0x7F000000, 0x34000000)
404 __AARCH64_INSN_FUNCS(cbnz,	0x7F000000, 0x35000000)
405 __AARCH64_INSN_FUNCS(tbz,	0x7F000000, 0x36000000)
406 __AARCH64_INSN_FUNCS(tbnz,	0x7F000000, 0x37000000)
407 __AARCH64_INSN_FUNCS(bcond,	0xFF000010, 0x54000000)
408 __AARCH64_INSN_FUNCS(svc,	0xFFE0001F, 0xD4000001)
409 __AARCH64_INSN_FUNCS(hvc,	0xFFE0001F, 0xD4000002)
410 __AARCH64_INSN_FUNCS(smc,	0xFFE0001F, 0xD4000003)
411 __AARCH64_INSN_FUNCS(brk,	0xFFE0001F, 0xD4200000)
412 __AARCH64_INSN_FUNCS(exception,	0xFF000000, 0xD4000000)
413 __AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
414 __AARCH64_INSN_FUNCS(br,	0xFFFFFC1F, 0xD61F0000)
415 __AARCH64_INSN_FUNCS(br_auth,	0xFEFFF800, 0xD61F0800)
416 __AARCH64_INSN_FUNCS(blr,	0xFFFFFC1F, 0xD63F0000)
417 __AARCH64_INSN_FUNCS(blr_auth,	0xFEFFF800, 0xD63F0800)
418 __AARCH64_INSN_FUNCS(ret,	0xFFFFFC1F, 0xD65F0000)
419 __AARCH64_INSN_FUNCS(ret_auth,	0xFFFFFBFF, 0xD65F0BFF)
420 __AARCH64_INSN_FUNCS(eret,	0xFFFFFFFF, 0xD69F03E0)
421 __AARCH64_INSN_FUNCS(eret_auth,	0xFFFFFBFF, 0xD69F0BFF)
422 __AARCH64_INSN_FUNCS(mrs,	0xFFF00000, 0xD5300000)
423 __AARCH64_INSN_FUNCS(msr_imm,	0xFFF8F01F, 0xD500401F)
424 __AARCH64_INSN_FUNCS(msr_reg,	0xFFF00000, 0xD5100000)
425 __AARCH64_INSN_FUNCS(dmb,	0xFFFFF0FF, 0xD50330BF)
426 __AARCH64_INSN_FUNCS(dsb_base,	0xFFFFF0FF, 0xD503309F)
427 __AARCH64_INSN_FUNCS(dsb_nxs,	0xFFFFF3FF, 0xD503323F)
428 __AARCH64_INSN_FUNCS(isb,	0xFFFFF0FF, 0xD50330DF)
429 __AARCH64_INSN_FUNCS(sb,	0xFFFFFFFF, 0xD50330FF)
430 __AARCH64_INSN_FUNCS(clrex,	0xFFFFF0FF, 0xD503305F)
431 __AARCH64_INSN_FUNCS(ssbb,	0xFFFFFFFF, 0xD503309F)
432 __AARCH64_INSN_FUNCS(pssbb,	0xFFFFFFFF, 0xD503349F)
433 __AARCH64_INSN_FUNCS(bti,	0xFFFFFF3F, 0xD503241f)
434 
435 #undef	__AARCH64_INSN_FUNCS
436 
aarch64_insn_is_steppable_hint(u32 insn)437 static __always_inline bool aarch64_insn_is_steppable_hint(u32 insn)
438 {
439 	if (!aarch64_insn_is_hint(insn))
440 		return false;
441 
442 	switch (insn & 0xFE0) {
443 	case AARCH64_INSN_HINT_XPACLRI:
444 	case AARCH64_INSN_HINT_PACIA_1716:
445 	case AARCH64_INSN_HINT_PACIB_1716:
446 	case AARCH64_INSN_HINT_PACIAZ:
447 	case AARCH64_INSN_HINT_PACIASP:
448 	case AARCH64_INSN_HINT_PACIBZ:
449 	case AARCH64_INSN_HINT_PACIBSP:
450 	case AARCH64_INSN_HINT_BTI:
451 	case AARCH64_INSN_HINT_BTIC:
452 	case AARCH64_INSN_HINT_BTIJ:
453 	case AARCH64_INSN_HINT_BTIJC:
454 	case AARCH64_INSN_HINT_NOP:
455 		return true;
456 	default:
457 		return false;
458 	}
459 }
460 
aarch64_insn_is_branch(u32 insn)461 static __always_inline bool aarch64_insn_is_branch(u32 insn)
462 {
463 	/* b, bl, cb*, tb*, ret*, b.cond, br*, blr* */
464 
465 	return aarch64_insn_is_b(insn) ||
466 	       aarch64_insn_is_bl(insn) ||
467 	       aarch64_insn_is_cbz(insn) ||
468 	       aarch64_insn_is_cbnz(insn) ||
469 	       aarch64_insn_is_tbz(insn) ||
470 	       aarch64_insn_is_tbnz(insn) ||
471 	       aarch64_insn_is_ret(insn) ||
472 	       aarch64_insn_is_ret_auth(insn) ||
473 	       aarch64_insn_is_br(insn) ||
474 	       aarch64_insn_is_br_auth(insn) ||
475 	       aarch64_insn_is_blr(insn) ||
476 	       aarch64_insn_is_blr_auth(insn) ||
477 	       aarch64_insn_is_bcond(insn);
478 }
479 
aarch64_insn_is_branch_imm(u32 insn)480 static __always_inline bool aarch64_insn_is_branch_imm(u32 insn)
481 {
482 	return aarch64_insn_is_b(insn) ||
483 	       aarch64_insn_is_bl(insn) ||
484 	       aarch64_insn_is_tbz(insn) ||
485 	       aarch64_insn_is_tbnz(insn) ||
486 	       aarch64_insn_is_cbz(insn) ||
487 	       aarch64_insn_is_cbnz(insn) ||
488 	       aarch64_insn_is_bcond(insn);
489 }
490 
aarch64_insn_is_adr_adrp(u32 insn)491 static __always_inline bool aarch64_insn_is_adr_adrp(u32 insn)
492 {
493 	return aarch64_insn_is_adr(insn) ||
494 	       aarch64_insn_is_adrp(insn);
495 }
496 
aarch64_insn_is_dsb(u32 insn)497 static __always_inline bool aarch64_insn_is_dsb(u32 insn)
498 {
499 	return aarch64_insn_is_dsb_base(insn) ||
500 	       aarch64_insn_is_dsb_nxs(insn);
501 }
502 
aarch64_insn_is_barrier(u32 insn)503 static __always_inline bool aarch64_insn_is_barrier(u32 insn)
504 {
505 	return aarch64_insn_is_dmb(insn) ||
506 	       aarch64_insn_is_dsb(insn) ||
507 	       aarch64_insn_is_isb(insn) ||
508 	       aarch64_insn_is_sb(insn) ||
509 	       aarch64_insn_is_clrex(insn) ||
510 	       aarch64_insn_is_ssbb(insn) ||
511 	       aarch64_insn_is_pssbb(insn);
512 }
513 
aarch64_insn_is_store_single(u32 insn)514 static __always_inline bool aarch64_insn_is_store_single(u32 insn)
515 {
516 	return aarch64_insn_is_store_imm(insn) ||
517 	       aarch64_insn_is_store_pre(insn) ||
518 	       aarch64_insn_is_store_post(insn);
519 }
520 
aarch64_insn_is_store_pair(u32 insn)521 static __always_inline bool aarch64_insn_is_store_pair(u32 insn)
522 {
523 	return aarch64_insn_is_stp(insn) ||
524 	       aarch64_insn_is_stp_pre(insn) ||
525 	       aarch64_insn_is_stp_post(insn);
526 }
527 
aarch64_insn_is_load_single(u32 insn)528 static __always_inline bool aarch64_insn_is_load_single(u32 insn)
529 {
530 	return aarch64_insn_is_load_imm(insn) ||
531 	       aarch64_insn_is_load_pre(insn) ||
532 	       aarch64_insn_is_load_post(insn);
533 }
534 
aarch64_insn_is_load_pair(u32 insn)535 static __always_inline bool aarch64_insn_is_load_pair(u32 insn)
536 {
537 	return aarch64_insn_is_ldp(insn) ||
538 	       aarch64_insn_is_ldp_pre(insn) ||
539 	       aarch64_insn_is_ldp_post(insn);
540 }
541 
aarch64_insn_uses_literal(u32 insn)542 static __always_inline bool aarch64_insn_uses_literal(u32 insn)
543 {
544 	/* ldr/ldrsw (literal), prfm */
545 
546 	return aarch64_insn_is_ldr_lit(insn) ||
547 	       aarch64_insn_is_ldrsw_lit(insn) ||
548 	       aarch64_insn_is_adr_adrp(insn) ||
549 	       aarch64_insn_is_prfm_lit(insn);
550 }
551 
552 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
553 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
554 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
555 				  u32 insn, u64 imm);
556 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
557 					 u32 insn);
558 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
559 				enum aarch64_insn_branch_type type);
560 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
561 				     enum aarch64_insn_register reg,
562 				     enum aarch64_insn_variant variant,
563 				     enum aarch64_insn_branch_type type);
564 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
565 				     enum aarch64_insn_condition cond);
566 
567 static __always_inline u32
aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)568 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
569 {
570 	return aarch64_insn_get_hint_value() | op;
571 }
572 
aarch64_insn_gen_nop(void)573 static __always_inline u32 aarch64_insn_gen_nop(void)
574 {
575 	return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
576 }
577 
578 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
579 				enum aarch64_insn_branch_type type);
580 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
581 				    enum aarch64_insn_register base,
582 				    enum aarch64_insn_register offset,
583 				    enum aarch64_insn_size_type size,
584 				    enum aarch64_insn_ldst_type type);
585 u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
586 				    enum aarch64_insn_register base,
587 				    unsigned int imm,
588 				    enum aarch64_insn_size_type size,
589 				    enum aarch64_insn_ldst_type type);
590 u32 aarch64_insn_gen_load_literal(unsigned long pc, unsigned long addr,
591 				  enum aarch64_insn_register reg,
592 				  bool is64bit);
593 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
594 				     enum aarch64_insn_register reg2,
595 				     enum aarch64_insn_register base,
596 				     int offset,
597 				     enum aarch64_insn_variant variant,
598 				     enum aarch64_insn_ldst_type type);
599 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
600 				   enum aarch64_insn_register base,
601 				   enum aarch64_insn_register state,
602 				   enum aarch64_insn_size_type size,
603 				   enum aarch64_insn_ldst_type type);
604 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
605 				 enum aarch64_insn_register src,
606 				 int imm, enum aarch64_insn_variant variant,
607 				 enum aarch64_insn_adsb_type type);
608 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
609 			 enum aarch64_insn_register reg,
610 			 enum aarch64_insn_adr_type type);
611 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
612 			      enum aarch64_insn_register src,
613 			      int immr, int imms,
614 			      enum aarch64_insn_variant variant,
615 			      enum aarch64_insn_bitfield_type type);
616 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
617 			      int imm, int shift,
618 			      enum aarch64_insn_variant variant,
619 			      enum aarch64_insn_movewide_type type);
620 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
621 					 enum aarch64_insn_register src,
622 					 enum aarch64_insn_register reg,
623 					 int shift,
624 					 enum aarch64_insn_variant variant,
625 					 enum aarch64_insn_adsb_type type);
626 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
627 			   enum aarch64_insn_register src,
628 			   enum aarch64_insn_variant variant,
629 			   enum aarch64_insn_data1_type type);
630 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
631 			   enum aarch64_insn_register src,
632 			   enum aarch64_insn_register reg,
633 			   enum aarch64_insn_variant variant,
634 			   enum aarch64_insn_data2_type type);
635 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
636 			   enum aarch64_insn_register src,
637 			   enum aarch64_insn_register reg1,
638 			   enum aarch64_insn_register reg2,
639 			   enum aarch64_insn_variant variant,
640 			   enum aarch64_insn_data3_type type);
641 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
642 					 enum aarch64_insn_register src,
643 					 enum aarch64_insn_register reg,
644 					 int shift,
645 					 enum aarch64_insn_variant variant,
646 					 enum aarch64_insn_logic_type type);
647 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
648 			      enum aarch64_insn_register src,
649 			      enum aarch64_insn_variant variant);
650 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
651 				       enum aarch64_insn_variant variant,
652 				       enum aarch64_insn_register Rn,
653 				       enum aarch64_insn_register Rd,
654 				       u64 imm);
655 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
656 			  enum aarch64_insn_register Rm,
657 			  enum aarch64_insn_register Rn,
658 			  enum aarch64_insn_register Rd,
659 			  u8 lsb);
660 #ifdef CONFIG_ARM64_LSE_ATOMICS
661 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
662 				  enum aarch64_insn_register address,
663 				  enum aarch64_insn_register value,
664 				  enum aarch64_insn_size_type size,
665 				  enum aarch64_insn_mem_atomic_op op,
666 				  enum aarch64_insn_mem_order_type order);
667 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
668 			 enum aarch64_insn_register address,
669 			 enum aarch64_insn_register value,
670 			 enum aarch64_insn_size_type size,
671 			 enum aarch64_insn_mem_order_type order);
672 #else
673 static inline
aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_atomic_op op,enum aarch64_insn_mem_order_type order)674 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
675 				  enum aarch64_insn_register address,
676 				  enum aarch64_insn_register value,
677 				  enum aarch64_insn_size_type size,
678 				  enum aarch64_insn_mem_atomic_op op,
679 				  enum aarch64_insn_mem_order_type order)
680 {
681 	return AARCH64_BREAK_FAULT;
682 }
683 
684 static inline
aarch64_insn_gen_cas(enum aarch64_insn_register result,enum aarch64_insn_register address,enum aarch64_insn_register value,enum aarch64_insn_size_type size,enum aarch64_insn_mem_order_type order)685 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
686 			 enum aarch64_insn_register address,
687 			 enum aarch64_insn_register value,
688 			 enum aarch64_insn_size_type size,
689 			 enum aarch64_insn_mem_order_type order)
690 {
691 	return AARCH64_BREAK_FAULT;
692 }
693 #endif
694 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
695 u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
696 			 enum aarch64_insn_system_register sysreg);
697 
698 s32 aarch64_get_branch_offset(u32 insn);
699 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
700 
701 s32 aarch64_insn_adrp_get_offset(u32 insn);
702 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
703 
704 bool aarch32_insn_is_wide(u32 insn);
705 
706 #define A32_RN_OFFSET	16
707 #define A32_RT_OFFSET	12
708 #define A32_RT2_OFFSET	 0
709 
710 u32 aarch64_insn_extract_system_reg(u32 insn);
711 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
712 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
713 u32 aarch32_insn_mcr_extract_crm(u32 insn);
714 
715 typedef bool (pstate_check_t)(unsigned long);
716 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
717 
718 #endif /* __ASSEMBLY__ */
719 
720 #endif	/* __ASM_INSN_H */
721